Sony CXP85232A, CXP85228A, CXP85224A, CXP85220A, CXP85116B Datasheet

CMOS 8-bit Single-chip Microcomputer

Description

The CXP85112B/85116B, CXP85220A/85224A/
85228A/85232A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, vector interruption, on-screen display function,
I2C bus interface, PWM generator, remote control
reception circuit, HSYNC counter, power source
frequency counter and watch dog timer besides the
basic configurations of 8-bit CPU, ROM, RAM, and
l/O port.

The CXP85112B/85116B, CXP85220A/85224A/
85228A/85232A also provides a power-on reset
function and a sleep function that enables lower
power consumption.

Features

• Wide-range instruction system (213 instructions) to cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 1µs at 4MHz operation

• Incorporated ROM capacity 12K bytes (CXP85112B)

16K bytes (CXP85116B)
20K bytes (CXP85220A)
24K bytes (CXP85224A)
28K bytes (CXP85228A)
32K bytes (CXP85232A)

• Incorporated RAM capacity 352 bytes (CXP85112B/85116B)

448 bytes (CXP85220A/85224A/85228A/85232A)

• Peripheral functions

— On-screen display function 12 × 16 dots, 128 types

21 words × 4 Iines (more than 4 Iines possible)

Double scan mode compatible, jitter elimination circuit
— I2C bus interface
— PWM output 14 bits, 1 channel

6 bits, 8 channels
— Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO
— A/D converter 4 bits, 4channels, successive approximation method

(Conversion time of 40µs/4MHz)
— HSYNC counter
— Power supply frequency counter
— Watch dog timer
— Serial I/O 8-bit clock synchronization
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer

• Interruption 14 factors, 14 vectors, multi-interruption possible

• Standby mode Sleep

• Package 64-pin plastic SDIP/QFP

• Piggyback/evaluation chip CXP85100A, CXP85190 (Custom font compatible)

CXP85200A, CXP85290 (Custom font compatible)

– 1 –

E93Z17B86

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP85112B/85116B

CXP85220A/85224A/85228A/85232A

64 pin SDIP (Plastic) 64 pin QFP (Plastic)

Structure

Silicon gate CMOS IC

Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

– 2 –

CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

ON SCREEN DISPLAY

SERIAL I/O

TIMER/COUNTER

REMOCON FIFO

HSYNC COUNTER

AC TIMER

A/D CONVERTER

I

2

C INTERFACE UNIT

WATCH DOG TIMER

14 BIT PWM

6 BIT PWM 8CH

CLOCK GEN./

SYSTEM CONTROL

RAM

352/448 BYTES

SPC700

CPU CORE

PRESCALER/

TIME BASE TIMER

PORT APORT BPORT CPORT DPORT EPORT F

2

2

V

SS

V

DD

MP

XTAL
EXTAL

RST

PF0/PWM0

to

PF7/PWM7

INTERRUPT CONTROLLER

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE5

PE6 to PE7

PF0 to PF7

XLC

B

R

BLK

HSYNC

VSYNC

PD3/SI

PD2/SO

PD1/SCK

PD7/EC

PE7/TO

PD6/RMC

PD4/HSI

PD5/ACI

PE2/AN0

to

PE5/AN3

PF4/SCL0

PF5/SCL1

PF6/SDA0

PF7/SDA1

PE6/PWM

PE0/INT0

PE1/INT1

PD0/INT2

G

EXLC

ROM

12K/16K/20K/24K/28K/32K

BYTES

Block Diagram

– 3 –

CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

VDD
NC
V

SS

MP

PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3

BLK
R
G
B
VSYNC
HSYNC
EXLC
XLC
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3
PE6/PWM
PE7/TO
RST

EXTAL
XTAL
PD0/INT2

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

61

63

64

62

53

54

55

56

57

58

59

60

PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1

PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1

PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

PD7/EC

PD6/RMC

PD5/ACI
PD4/HSI

PD3/SI

PD2/SO

PD1/SCK

V

SS

4
5
6
7
8
9

10

2
3

1

11
12
13
14
15
16
17

18

19

20
21

22

23

24
25
26

27

28

29
30

31

32

Note) 1. NC (Pin 63) must be connected to VDD.

2. Vss for both Pins 32 and 62 must be grounded.

3. MP (Pin 61) must be connected to GND.

Pin Assignment 1 (Top View) 64 pin SDIP Package

– 4 –

CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

PF3/PWM3

BLK
R
G
B
VSYNC
HSYNC
EXLC

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

61

63

64

62

53

54

55

56

57

58

59

60

PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1

PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0

PD7/EC

4

5

6
7
8
9

10

2

3

1

11

12

13
14
15
16

17
18

19

20

21

22

23

24

25

26

27

28

29

30

PA2

PA3

PA4

PA5

PA7

V

SS

PA6

V

DD

NC

MP

PF0/PWM0

PF2/PWM2

PF1/PWM1

PA1
PA0

PD6/RMC

PD5/ACI

PD4/HSI

PD3/SI

PD1/SCK

V

SS

PD2/SO

PD0/INT2

XTAL

EXTAL

RST

PE6/PWM

PE7/TO

31

32

XLC
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3

Note) 1. NC (Pin 56) must be connected to VDD.

2. Vss for both Pins 26 and 58 must be grounded.

3. MP (Pin 55) must be connected to GND.

Pin Assignment 2 (Top View) 64 pin QFP Package

– 5 –

CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.

(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port.
I/O can be set ina a
unit of single bits.
Capable of driving
12mA sink current.
(8 pins)

(Port E)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.

(Port F)
8-bit output port,
operating as N-ch
open drain output
for high current
(12mA).
Lower 4 bits are
medium voltage
drive outputs (12V),
upper 4bits are 5V
drive outputs.
(8 pins)

4-bit outputs for CRT display.
Horizontal synchronizing signal input for CRT display.
Vertical synchronizing signal input for CRT display.

Pin Description

Symbol

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0/INT2
PD1/SCK

PD2/SO
PD3/SI
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC

PE0/INT0
PE1/INT1

PE2/AN0

to

PE5/AN3
PE6/PWM

PE7/TO
PF0/PWM0

to

PF3/PWM3
PF4/PWM4/

SCL0
PF5/PWM5/
SCL1

PF6/PWM6/
SDA0
PF7/PWM7/
SDA1

R, G, B, BLK
HSYNC
VSYNC

I/O

I/O

I/O

I/O/Input
I/O/I/O

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Input/Input

Input/Input

Output/Output

Output/Output

Output/Output

Output/Output/
I/O

Output/Output/
I/O

Output
Input
Input

I/O Description

External interruption request input.
Active at falling edge.

Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter input.
Input for power supply frequency counter.
Input for remote control reception circuit.
External event input for timer/counter.
External interruption request inputs.

Active at falling edge.
(2 pins)

Analog inputs for A/D converter.
(4 pins)

14-bit PWM output.
(CMOS output)

Rectangular waveform output for Timer 1.
(Duty output 50%)

6-bit PWM outputs.
(8 pins)

Transfer clock I/Os for I2C bus
interface.

Transfer data I/Os for I2C data bus.

– 6 –

CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

Symbol
EXLC
XLC
EXTAL
XTAL

RST

MP
VDD
Vss

Input
Output
Input
Output

I/O

Input

Clock oscillation I/Os for CRT display.
Oscillation frequency is set using the external L and C.

Crystai connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

Low-level active, system reset. RST is an I/O, from whlch Low level is
output when the built-in power-on reset function is activated at the rise
of power on. (Mask option)

Microprocessor mode input. For this device, this pin must be grounded.
Vcc supply.
GND. Both Vss must be grounded.

I/O Description