Skyworth 42E68 Instruction Manual

SERVICE MANUAL

Description:

MODEL.

Engineering Dept:

Artwork By:

Checked By:

Approved By:

Brand Name:

JOB NO.

Date:

Date:

Date:

SERVICE MANUAL 8M48A

2012-02-28

SKYWORTH

SIZE:A5

Design and specifications are subject to change without prior notice.

(Only Referrence)

5M92A CHASSIS

Content--------------------------------------------------------------2

11-

41

42

43-44

45-53

54-80

81-84

85-94

LED 8M26A

TOSHIBA CODE

Component

PAL SECAM / BG DK PAL / I
NTSC / M

VHF LOW K1~S6
VHF HIGH S7~S36
VHF S37~DS57

44.25MHz ~ 140.25MHz

147.25MHz ~ 423.25MHz

431.25MHz ~ 863.25MHz

Asia\Europe

40

55

80

For 22” LED

For 24” LED

For 32” LED

(24 inches is 3W)

(24 inches is 4 ohm)

40

40

3

2

1

4.2
50

0.5

80

40

3

12000

(26inches is 8 ohm)

40

YES

8
6

46

46

NO

NO

Standard

Spanish

Standard

20

4
2

4

0 40 7 0

0 40 7 0

0 40

40 85

-Y 0 50

30000

AP1117

1A LOW DROPOUT POSITIVE ADJUSTABLE OR

FIXED-MODE REGULATOR

ʳ

ʳ

AP1117 Rev. 3 2 of 11 SEPTEMBER 2006

www.diodes.com © Diodes Incorporated

Typical Application Circuit ʳ

C2

22uF

5V

3.3V/1A

Tab is V

out

V

in

V

out

GND

C1
10uF

( 5V/3.3V fixed output ) ʳ

R1

121

R2

121

C2
22uF

5V

2.5V/1A

Tab is V

out

V

in

V

out

Adj

C1
10uF

o

V

( 5V/2.5V ADJ output ) ʳ

)

1

2

REFo

R

R

(1VV 

Note:

ȍ

ȍ

ʳ

ʳ
ʳ

3 PIN SOT223 3 PIN TO252 / TO263

3 PIN TO220

(

Top View )

3

2

1

V

in

V

out

Adj ( GND)

Tab is V

out

Tab is V

out

V

in

V

out

Adj ( GND)

(

Top View )

3

2

1

3 PIN SOT89

V

in

V

out

Adj ( GND)

Tab is V

out

3

2

1

Adj ( GND)

V

in

V

out

Tab is V

out

3

2

1

ʳ

Connection Diagramʳ

AP1117

1A LOW DROPOUT POSITIVE ADJUSTABLE OR

FIXED-MODE REGULATOR

ʳ

ʳ

AP1117 Rev. 3 3 of 11 SEPTEMBER 2006

www.diodes.com © Diodes Incorporated

Block Diagramʳ

NAME I/O PIN # FUNCTION

Adj (GND) I 1

A resistor divider from this pin to the V

out

pin and ground sets the output voltage

(Ground only for Fixed-Mode).

V

out

O 2

The output of the regulator. A minimum of 10uF capacitor (0.15ȍ ESR  20ȍ)

must be connected from this pin to ground to insure stability.

V

in

I 3

The input pin of regulator. Typically a large storage capacitor (0.15ȍ ESR  20ȍ)

is connected from this pin to ground to insure that the input voltage does not sag
below the minimum dropout voltage during the load transient response. This pin

must always be 1.3V higher than V

out

in order for the device to regulate properly.

Pin Descriptionsʳ

3

Thermal

Shutdown

1

2

V

out

Adj

1.25V

+

+

CURRENT

LIMIT

V

in

-

+

+

1

GND

(FIXED)

-

AI SEMI ELECTRONICS LTD. 2

L Package

(SOT-223)

T Package

(TO-220) (TO-252)

Pin Configurations

INPUT

OUTPUT

ADJ/GND

V

OUT

INPUT

OUTPUT

ADJ/GND

V

OUT

INPUT

OUTPUT

ADJ/GND

V

OUT

Figure 2. Pin Configurations of AS111 7

1

2

3

1

2

3

1

2

3

U Package

ADJ/GND

OUTPUT

INPUT

V

OUT

S Package

(TO-263)

R Package

INPUT

OUTPUT

ADJ/GND

(SOT-89)

1

2

3

1

2

3

V

OUT

http://www.a1semi.com

AS1117

A1semi 1A Fixed and Adjustable Low

Electronics Ltd Dropout Linear Regulator(LDO)

A1

A1

A1

A1 SEMI ELECTRONICS LTD. 3

Functional Block Diagram

GND (Fixed Output)

ADJ (Adjustable Output)

Thermal

Shutdown

Out

+

-

INPUT

OUTPUT

Figure 3. Functional Block Diagram of AS1117

http://www.a1semi.com

AS1117

A1semi 1A Fixed and Adjustable Low

Electronics Ltd Dropout Linear Regulator(LDO)

A1

A1

A1

Rev. 1.0 June 2011 www.aosmd.com Page 1 of 14

AOZ1051PI

EZBuck™ 3 A Synchronous Buck Regulator

General Description

The AOZ1051PI is a high efficiency, easy to use, 3 A
synchronous buck regulator. The AOZ1051PI works from

4.5 V to 18 V input voltage range, and provides up to 3 A
of continuous output current with an output voltage
adjustable down to 0.8 V.

The AOZ1051PI comes in an exposed pad SO-8
package and is rated over a -40 °C to +85 °C operating
ambient temperature range.

Features

z 4.5 V to 18 V operating input voltage range

z Synchronous Buck: 70 m internal high-side switch

and 40 m internal low-side switch (at 12 V)

z Up to 95 % efficiency

z External soft start

z Output voltage adjustable to 0.8 V

z 3 A continuous output current

z 500 kHz PWM operation

z Cycle-by-cycle current limit

z Pre-bias start-up

z Short-circuit protection

z Thermal shutdown

z Exposed pad SO-8 package

Applications

z Point of load DC/DC converters

z LCD TV

z Set top boxes

z DVD and Blu-ray players/recorders

z Cable modems

Typical Application

Figure 1. 3.3 V 3 A Synchronous Buck Regulator, Fs = 500 kHz

LX

VIN

VIN

VOUT

FB

PGND

EN

COMP

AGND

C2, C3
22μF

R1

R2

C

C

C

SS

R

C

C1
10μF

L1 4.7μH

AOZ1051PI

SS

AOZ1051PI

Rev. 1.0 June 2011 www.aosmd.com Page 2 of 14

Ordering Information

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration

Pin Description

Part Number Ambient Temperature Range Package Environmental

AOZ1051PI -40 °C to +85 °C EPAD SO-8 Green Product

1

2

3

4

PGND

VIN

A

GND

FB

Exposed Pad SO-8

(Top View)

PAD
(LX)

NC

SS

EN

COMP

8

7

6

5

Pin Number Pin Name Pin Function

1 PGND Power ground. PGND needs to be electrically connected to AGND.

2 VIN Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,

the device starts up.

3 AGND Analog ground. AGND is the reference point for controller section. AGND needs to be

electrically connected to PGND.

4 FB Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider

between the output and AGND.

5 COMP External loop compensation pin. Connect a RC network between COMP and AGND to

compensate the control loop.

6 EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the

device. If on/off control in not needed, connect EN to VIN and do not leave it open.

7 SS Soft-start pin. 5 μA current charging current.

8 NC No Connect Pin. Pin 8 is not internally connected. Connect this pin externally to LX and

use it for better thermal performance.

Exposed pad LX Switching node. LX is the drain of the internal PFET. LX is used as the thermal pad of the

power stage.

AOZ1051PI

Rev. 1.0 June 2011 www.aosmd.com Page 3 of 14

Block Diagram

Absolute Maximum Ratings

Exceeding the Absolute Maximum Ratings may damage the
device.

Note:

1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 k

 in series with 100 pF.

Recommended Operating Conditions

The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.

Note:

2. The value of

4

JA

is measured with the device mounted on a 1-in

2

FR-4 board with 2 oz. Copper, in a still air environment with
T

A

= 25 °C. The value in any given application depends on the

user’s specific board design.

500kHz

Oscillator

AGND

PGND

VIN

EN

FB

SS

COMP

LX

OTP

Internal

+5V

ILimit

PWM

Control

Logic

5V LDO

Regulator

UVLO

& POR

Softstart

Reference

& Bias

0.8V

SS

5μA

Q1

Q2

PWM
Comp

Level

Shifter

+

FET

Driver

ISen

EAmp

+

–

+

–

+

–

+

Parameter Rating

Supply Voltage (VIN) 20 V

LX to AGND -0.7 V to V

IN

+0.3 V

LX to AGND (20 ns) -5 V to 22 V

EN to AGND -0.3 V to V

IN

+0.3 V

FB, SS, COMP to AGND -0.3 V to 6.0 V

PGND to AGND -0.3 V to +0.3 V

Junction Temperature (T

J

) +150 °C

Storage Temperature (T

S

) -65 °C to +150 °C

ESD Rating

(1)

2.0 kV

Parameter Rating

Supply Voltage (VIN) 4.5 V to 18 V

Output Voltage Range 0.8 V to 0.85 • V

IN

Ambient Temperature (TA) -40 °C to +85 °C

Package Thermal Resistance
Exposed Pad SO-8 (4

JA

)

(2)

50 °C/W

SY8086

High Efficiency 1.4MHz, 1A

Synchronous Step Down Regulator

Preliminary Specification

SY8086 Rev. 0.11 Silergy Corp. Confidential- Prepared for Customer Use Only 1

General Description

The SY8086 is a high-efficiency 1.4MHz synchronous
step-down DC-DC regulator ICs capable of delivering
up to 1A output current. The SY8086 operates over a
wide input voltage range from 2.5V to 5.5V and
integrate main switch and synchronous switch with
very low R

DS(ON)

to minimize the conduction loss.

Low output vol tage ripple and sm all external induct or
and capacitor sizes are achieved with 1.4MHz
switching frequency. This along with small SOT-23
footprint provides small PCB area application.

Ordering Information

Temperature Code

Package Code

Optional Spec Code

SY8086

ƶƶƶƶ(ƶƶ

ƶƶƶƶ

ƶƶ)ƶƶƶƶ

Temperature Code

Package Code

Optional Spec Code

SY8086

ƶƶƶƶ(ƶƶ

ƶƶƶƶ

ƶƶ)ƶƶƶƶ

Temperature Range: -40

e

C to 85eC

Features

•

Low R

DS(ON)

for inter n al sw itches (top/bottom):

250m

Ω

/200m

Ω

•

2.5-5.5V input voltage range

•

1.4MHz switching frequency minimizes the
external components

•

Internal softstart limits the inrush current

•

RoHS Compli an t a nd Hal oge n Fr ee

•

Compact package: SOT23 5 pin

Applications

•

Portable Navigation Device

•

Smart phone

•

USB Dongle

•

Set Top Box

•

Media Player

Typical Applications

LX

IN

GND

FB

EN

V

IN

C

IN

L

R

1

R

2

V

OUT

C

OUT

C1(opt.)

Figure 1. Schematic Diagram Figure2 Efficiency vs Load Current

Ordering Number Package type Note

SY8086AAC SOT23-5 1A

SY8086

SY8086 Rev. 0.11 Silergy Corp. Confidential- Prepared for Customer Use Only 2

Pinout (top view)

EN

GND

LX

IN

FB

1

2

3

5

4

EN

GND

LX

IN

FB

1

2

3

5

4

SOT23-5

Top mark:

BE

xyz

(Device code: BE, x=year code, y=week code, z= lot number code)

Pin Name Pin Number Pin Description

EN 1 Enable control. Pull high to turn on. Do not float.

GND 2 Ground pin

LX 3 Inductor pin. Connect this pin to the switching node of inductor

IN 4 Input pin. Decouple this pin to GND pin with at least 1uF ceramic cap

FB 5 Output Feedback Pin. Connect this pin to the center point of the output

resistor divid e r ( as sh ow n in Fi gu r e 1) to pr o gra m th e out p ut voltage:
Vout=0.6*(1+R

1/R2

)

Absolute Maximum Ratings

(Note 1)
Supply Input Voltage --------------------------------------------------------------------------------------------- 6.0V
Enable, FB Voltage------------------------------------------------------------------------------------------------ V

IN

+ 0.6V

Power Dissipation, P

D

@ TA = 25°C SOT-23-5 -------------------------------------------------------------- 0.4W

Package Thermal Resistance (Note 2)

SOT23-5,

θ

JA

------------------------------------------------------------------------------------------ 250°C/W

SOT23-5,

θ

JC

-------------------------------------------------------------------------------------------130°C/W
Junction Temperature Range ------------------------------------------------------------------------------------ 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C

Storage Temperature Range -------------------------------------------------------------------------------------

-

65°C to 150°C

ESD Susceptibility (Note 2)

HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------200V

Recommended Operating Conditions

(Note 3)

Supply Input Voltage --------------------------------------------------- ---- ------------------------------------- 2.5V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------------------- -40°C to 125°C

Ambient Temperature Range ----------------------------------------------------------------------------------

-

40°C to 85°C

IC Block Diagram

-13-

U10(LCDTV CONTROLLER WITH VIDEO ECODE)MST6E181VS

PIN DIAGRAM (MST6E181VS)

MST6E181VS

198
199

217

2

1

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108
107
106
105
104
103
102
101

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

545352515049484746

45

4443424140393837363534333231302928

2726252423222120191817161514131211

10

9876543

DM_P1

DP_P1

E-pad

CEC

IRIN

GPIO9/PM6/CS1

GPIO8/PM5/RX

GPIO7/PM4/POWER_ON

GPIO6/PM1/TX

DDCA_DA

DDCA_CK

GPIO10/PMGPIO

GPIO13/SAR2

GPIO12/SAR1

GPIO11/SAR0

SPI_CZ

SPI_DO

SPI_DI

SPI_CK

GND_EFUSE

DVDD_NODIE

AVDD_NODIE

DP_P0

DM_P0

TESTPIN

DDCR_CK

VDDP_3

DDCR_DA

VDDC

A_DDR1_A4

A_DDR1_A5

A_DDR1_A6

A_DDR1_A7

A_DDR1_A8

AVDDIO_2.5V

A_DDR1_A9

A_DDR1_A11

A_DDR1_A12

A_DDR1_CKE

NC

A_DDR1_MCLK

AVDDIO_2.5V

A_DDR1_MCLKZ

A_DDR1_DQ15

AVDDIO_2.5V

A_DDR1_DQ14

A_MVREF

A_DDR1_DQ13

A_DDR1_DQ12

A_DDR1_DQ11

A_DDR1_DQ10

AVDDIO_2.5V

A_DDR1_DQ9

A_DDR1_DQ8

UDQS0

UDQM0

AVDD_PLL

DVDD_DDR_1.2V

LDQM0

LDQS0

AVDDIO_2.5V

NC

NC

A_DDR1_DQ7

A_DDR1_DQ6

A_DDR1_DQ5

AVDDIO_2.5V

A_DDR1_DQ4

A_DDR1_DQ3

A_DDR1_DQ2

A_DDR1_DQ1

AVDDIO_2.5V

A_DDR1_DQ0

A_DDR1_WEZ

A_DDR1_CAS

A_DDR1_RAS

A_DDR1_BA0

AVDDIO_2.5V

A_DDR1_BA1

A_DDR1_A10

A_DDR1_A0

A_DDR1_A1

A_DDR1_A2

A_DDR1_A3

NC

NC

VDDC

GPIO21/PWM1

GPIO20/PWM0

VDDP_2

GPIO77/I2S_OUT_MUTE/PWM3/LVSYNC

GPIO76/I2S_IN_BCK/PWM2/LHSYNC

GPIO75/I2S_IN_SD/PWM5/TX3/LDE

GPIO74/I2S_IN_WS/PWM4/RX3/LCK

AVDD_LPLL

AVDD2P5_MOD

VDDC

R_ODD7/RXO0-

R_ODD6/RXO0+

R_ODD5/RXO1-

R_ODD4/RXO1+

R_ODD3/RXO2-

R_ODD2/RXO2+

R_ODD1/RXOC-

R_ODD0/RXOC+

G_ODD7/RXO3-

G_ODD6/RXO3+

G_ODD5/RXO4-

G_ODD4/RXO4+

G_ODD3/RXE0-

G_ODD2/RXE0+

AVDD2P5_MOD
G_ODD1/RXE1­G_ODD0/RXE1+
B_ODD7/RXE2­B_ODD6/RXE2+
B_ODD5/RXEC­B_ODD4/RXEC+
B_ODD3/RXE3­B_ODD2/RXE3+
B_ODD1/RXE4­B_ODD0/RXE4+

NC

GPIO49
GPIO47
GPIO45
GPIO38
GPIO37
GPIO36
GPIO32/I2S_OUT_BCK

GPIO30/I2S_OUT_MCK

GPIO28

VDDP_1

VDDC
GPIO27/SPDIF_OUT

GPIO26/SPDIF_IN/RX1/PWM3
GPIO25/TUNER_SDA
GPIO24/TUNER_SCL

GPIO23/I2S_OUT_SD/TX2
GPIO22/I2S_OUT_WS/RX2
TAGC
SIFM
SIFP

AVDD25_PGA

VIFP
VIFM

AVSS_PGA
AVDD25_REF

AVDD_DMPLL

XTAL_OUT
XTAL_IN

NC
NC
NC

LINEOUT_R0
LINEOUT_L0
LINEOUT_R3
LINEOUT_L3

AVDD_AU33
LINEIN_R5
LINEIN_L5
LINEIN_R4
LINEIN_L4
LINEIN_R3
LINEIN_L3

AVDD_AU25

VAG

VRP

VRM

LINEIN_R1

LINEIN_L1

LINEIN_R0

LINEIN_L0

CVBS_OUT1

VCOM

CVBS0

CVBS1

CVBS2

CVBS3

CVBS4

AVDD3P3_ADC

RIN1P

GIN1M

GIN1P

SOGIN1

BIN1P

AVDD2P5_ADC

AVDD1P2

VSYNC0

RIN0P

GIN0M

GIN0P

SOGIN0

BIN0P

HSYNC0

VDDC

NC

NC

NCNCNCNCNC

ARC

DDCDA_CK

RX2P

RX2N

DDCDA_DA

RX1P

RX1N

AVDD_DVI_3.3V

RX0P

RX0N

RXCP

RXCN

HOTPLUGA

RESET

U?

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MStar Confidential

for Skyworth

Internal Use Only

MST6M181VG/MST6M182VG

LCD Television System-on-Chip

Preliminary Pin Diagram/Description and Mechanical Dimensions Version 0.2

- 1 - 8/29/2011

Copyright

2011 MStar Semiconductor, Inc. All rights reserved.

PIN DIAGRAM (MST6M181VG/MST6M182VG)

1 2 3 4 5 6 7 8 9 10111213141516

A RXCKP RXCKN NC NC HWRESET GPIO7 GPIO6 GND USB1_DM USB0_DP USB0_DM A

B RX1N RX 0P RX0N NC NC NC NC IRIN GPIO8 SAR0 PWM0 USB1_DP DDCR_CK SCZ SDO B

C RX2N RX2 P RX1 P NC NC NC NC GPIO9 SAR2 SAR 1 P WM1 GND DDCR_D A SC K S DI C

D DDCD_CK ARC

DDCD_DAHOTPLUG

A

NC CEC BYPA SS

AVDD_D

DR

DDCA_CK DDC A_DA GPIO10 GND LEDON HCON DP M D

ESOGIN0BIN0PHSYNC0

AVDD_DDRSCAN_BL

K

POL

GOE/

GCLK2

E

F RIN0P GIN0M GIN0P VSYNC0 GND

SCAN_BL

K1

WPWM OPT_ P F

G GND GND GND

AVDD_D

DR

GND SAR3 OPT_N GCLK4 G

H SOGIN1 BIN1P

AVDD_AL

IVE

AVDD_25

AVDD_126DVDD_D

DR

GND GND GND

GSP/

VST

SOE FLK3 H

J RIN1P GIN1M GIN1P AVDD_33

AVDD_ME

MPLL

AVDD_AU

25

VDDC VDDC GND GND GND

GSP_R/

GCLK1

GSC/

GCLK 3

FLK J

K CV BS2 CVB S1 NC

AVDD_D

MPLL

AVDD_MODAVDD_ RE

F

VDDC VDDC GND GND GND MVREF

VGH_OD

D

GCLK 5

VGH_EVE

N

K

L CVBS0 VCOM AUVA G AUVRP

AVDD_M

OD

VDDP VDDC V DDC FLK2 GCLK6 R LV2P L

M CVBSOUT AUL0 AUL3 GND

AVDD_AU

33

VDDP

AVDD_ DDRAVDD_D

DR

RLVCKM RLVCKP RLV2M M

N AUR0 AUL1 AUR3 AUOUTL1

AVDD_PG

A

GND N C NC RLV1 M RLV1P RLV0M RLV0P RLV3M RLV3 P N

PAUR1 AUL2AUOUTR1 GND PGA_COM GND GND

I2S_OUT

_SD

SPDIFI LLV5M LLV4M LLV3P LLV2M LLV1M RLV4M RLV4P P

RAUR2AUOUTL0 XOUT GND GND VIFM GND

I2S_OUT

_MCK

I2S_OUT

_BCK

LLV5P LLV4P LLV CKP LLV2P LLV1P RLV5M RLV5P R

T AUOUTR0 XIN TAGC GND VIFP GND

I2S_OUT

_WS

SPDIFO LLV3M LLVCKM LLV0M LLV0P T

1 2 3 4 5 6 7 8 9 10111213141516

Doc. No.:

2012010018

Doc. No.:

2012010018

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