Silicon Laboratories SI5351A-B-C User Manual

Si5351A/B/C

I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK

GENERATOR + VCXO

Features

Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz

I2C user definable configuration

Exact frequency synthesis at each output (0 ppm error)

Highly linear VCXO

Optional clock input (CLKIN)

Low output period jitter: 100 ps pp

Configurable spread spectrum selectable at each output

Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz

Supports static phase offset

Programmable rise/fall time control

Glitchless frequency changes

Separate voltage supply pins: Core VDD: 2.5 or 3.3 V Output VDDO: 1.8, 2.5, or 3.3 V

Excellent PSRR eliminates external

power supply filtering

Very low power consumption

Adjustable output-output delay

Available in 3 packages types: 10-MSOP: 3 outputs 24-QSOP: 8 outputs 20-QFN (4x4 mm): 8 outputs

PCIE Gen 1 compliant

Supports HCSL compatible swing

Applications

 HDTV, DVD/Blu-ray, set-top box			Residential gateways
	Audio/video equipment, gaming		Networking/communication
	Printers, scanners, projectors		Servers, storage
			XO replacement

Description

The Si5351 is an I2C configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide variety of applications. The Si5351A generates up to 8 free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an internal VCXO and provides the flexibility to replace both free-running clocks and synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable crystals while providing reliable operation over a wide tuning range. The Si5351C offers the same flexibility but synchronizes to an external reference clock (CLKIN).

10-MSOP

24-QSOP

20-QFN

Ordering Information:

See page 66

Functional Block Diagram

		Multi	XA		Multi	XA			Multi
XA	PLLA
		Synth			Synth				Synth
		0	OSC	PLL	0		OSC	PLLA	0
	OSC	Multi			Multi				Multi
		Synth			Synth	XB			Synth
			XB
XB	PLLB	1			1				1
					Multi				Multi
			VC	VCXO	Synth			PLLB	Synth
					2	CLKIN			2
					Multi				Multi
		Multi
I2C					Synth				Synth
		Synth
		N			3				3
SSEN					Multi				Multi
		Si5351A			Synth				Synth
OEB					4				4
					Multi				Multi
	N = 2 or 7				Synth				Synth
					5				5
					Multi				Multi
					Synth				Synth
					6	I2C			6
			I2C		Multi				Multi
					Synth				Synth
			SSEN		7	INTR			7
			OEB		Si5351B	OEB			Si5351C
Preliminary Rev. 0.95 8/11			Copyright © 2011 by Silicon Laboratories						Si5351A/B/C

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5351A/B/C

2	Preliminary Rev. 0.95

Si5351A/B/C

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .19

5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.6. Replacing a Crystal with a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . .62 10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .63 11. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . .64 12. Si5351A Pin Descriptions (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 14. Package Outline (24-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 15. Package Outline (20-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 16. Package Outline (10-Pin MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Ambient Temperature	TA		–40	25	85	°C
Core Supply Voltage	VDD		3.0	3.3	3.60	V
			2.25	2.5	2.75	V
			1.71	1.8	1.89	V
Output Buffer Voltage	VDDOx		2.25	2.5	2.75	V
			3.0	3.3	3.60	V

Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages.

Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time.

Table 2. DC Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

	Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
			Enabled 3 outputs	—	22	35	mA
	Core Supply Current	IDD	Enabled 8 outputs	—	27	45	mA
			Power Down (PDN = VDD)	—	—	20	µA
	Output Buffer Supply Current	IDDOx	CL = 5 pF	—	2.2	5	mA
	(Per Output)*
		ICLKIN	CLKIN, SDA, SCL	—	—	10	µA
	Input Current		Vin < 3.6 V
		IVC	VC	—	—	30	µA
	Output Impedance	ZO	8 mA output drive current.
			See "6. Design Consider-	—	85	—
			ations" on page 21.

*Note: Output clocks less than or equal to 100 MHz.

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Table 3. AC Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

	Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
	Power-up Time	TRDY	From VDD = VDDmin to valid
			output clock, CL = 5 pF,	—	1	10	ms
			fCLKn > 1 MHz
			From OEB pulled low to valid
	Output Enable Time	TOE	clock output, CL = 5 pF,	—	—	10	µs
			fCLKn > 1 MHz
	Output Phase Offset	PSTEP		—	333	—	ps/step
	Spread Spectrum Frequency	SSDEV	Down spread	–0.1	—	–2.5	%
	Deviation		Center spread	±0.1	—	±1.5	%
	Spread Spectrum Modulation	SSMOD		30	31.5	33	kHz
	Rate
	VCXO Specifications (Si5351B only)
	VCXO Control Voltage Range	Vc		0	VDD/2	VDD	V
	VCXO Gain (configurable)	Kv	Vc = 10–90% of VDD, VDD = 3.3 V	18	—	150	ppm/V
	VCXO Control Voltage Linearity	KVL	Vc = 10–90% of VDD	–5	—	+5	%
	VCXO Pull Range	PR	VDD = 3.3 V*	±30	0	±240	ppm
	(configurable)
	VCXO Modulation Bandwidth			—	10	—	kHz

*Note: Contact Silicon Labs for 2.5 V VCXO operation.

Table 4. Input Clock Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter	Symbol	Test Condition	Min	Typ	Max	Units
CLKIN Input Low Voltage	VIL		–0.1	—	0.3 x VDD	V
CLKIN Input High Voltage	VIH		0.7 x VDD	—	3.60	V
CLKIN Frequency Range	fCLKIN		10	—	100	MHz

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Table 5. Output Clock Characteristics

(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

	Parameter	Symbol	Test Condition	Min	Typ	Max	Units
	Frequency Range	FCLK		0.008	—	160	MHz
	Load Capacitance	CL		—	5	15	pF
	Duty Cycle	DC	Measured at VDD/2,	45	50	55	%
			fCLK = 50 MHz
	Rise/Fall Time	tr	20%–80%, CL = 5 pF,	0.5	1	1.5	ns
		tf	Drive Strength = 8 mA	0.5	1	1.5	ns
	Output High Voltage	VOH	CL = 5 pF	VDD – 0.6	—	—	V
	Output Low Voltage	VOL		—	—	0.6	V
	Period Jitter	JPER	Measured over 10k cycles	—	35	100	ps pk-pk
	Period Jitter VCXO	JPER_VCXO		—	60	110	ps pk-pk
	Cycle-to-Cycle Jitter	JCC		—	30	90	ps pk
			Measured over 10k cycles
	Cycle-to-Cycle Jitter	JCC_VCXO		—	50	95	ps pk
	VCXO
	RMS Phase Jitter	JRMS	12 kHz–20 MHz	—	3.5	11	ps rms
	RMS Phase Jitter VCXO	JRMS_VCXO		—	8.5	18.5	ps rms

Table 6. Crystal Requirements1,2

Parameter	Symbol	Min	Typ	Max	Unit
Crystal Frequency	fXTAL	25	—	27	MHz
Load Capacitance	CL	6	—	12	pF
Equivalent Series Resistance	rESR	—	—	150
Crystal Max Drive Level	dL	—	—	100	µW

Notes:

1.Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10 pF load capacitors in addition to external 2 pF load capacitors.

2.Refer to “AN551: Crystal Selection Guide” for more details.

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Table 7. I2C Specifications (SCL,SDA)1

Parameter	Symbol	Test Condition			Standard Mode		Fast Mode				Unit
					100 kbps		400 kbps
					Min	Max	Min		Max
LOW Level	VILI2C				–0.5	0.3 x VDDI2	–0.5		0.3 x VDDI2C	2	V
Input Voltage						C
HIGH Level	VIHI2C				0.7 x VDDI2	3.63	0.7 x VDDI2C	2	3.63		V
Input Voltage					C
Hysteresis of					—	—	0.1		—		V
Schmitt Trigger	VHYS
Inputs
LOW Level		VDDI2C2 = 2.5/3.3 V			0	0.4	0		0.4		V
Output Voltage
(open drain or	VOLI2C2
open collector)		VDDI2C	2	= 1.8 V	—	—	0		0.2 x VDDI2C		V
at 3 mA Sink
Current
Input Current	III2C				–10	10	–10		10		µA
Capacitance for	CII2C	VIN = –0.1 to VDDI2C			—	4	—		4		pF
Each I/O Pin
I2C Bus	TTO	Timeout Enabled			25	35	25		35		ms
Timeout
Notes:

1. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details, go to: www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.

2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.

Table 8. Thermal Characteristics

	Parameter	Symbol	Test Condition	Package	Value	Unit
				10-MSOP	131	°C/W
	Thermal Resistance	JA
			Still Air	24-QSOP	80	°C/W
	Junction to Ambient
				20-QFN	51	°C/W
				10-MSOP	43	°C/W
	Thermal Resistance	JC
			Still Air	24-QSOP	31	°C/W
	Junction to Case
				20-QFN	16	°C/W

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Si5351A/B/C

Table 9. Absolute Maximum Ratings1

Parameter	Symbol	Test Condition	Value	Unit
DC Supply Voltage	VDD_max		–0.5 to 3.8	V
	VIN_CLKIN	CLKIN, SCL, SDA	–0.5 to 3.8	V
Input Voltage	VIN_VC	VC	–0.5 to (VDD+0.3)	V
	VIN_XA/B	Pins XA, XB	–0.5 to 1.3 V	V
Junction Temperature	TJ		–55 to 150	°C
Soldering Temperature (Pb-free	TPEAK		260	°C
profile)2
Soldering Temperature Time at	TP		20–40	Sec
TPEAK (Pb-free profile)2

Notes:

1.Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2.The device is compliant with JEDEC J-STD-020.

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Si5351A/B/C

2. Detailed Block Diagrams

XA
	OSC
XB
SDA	I2C
SCL	Interface

	VDD	Si5351A 3-Output		VDDO
	PLL	MultiSynth	R0	CLK0
	A
		0
	PLL	MultiSynth	R1	CLK1
	B
		1
		MultiSynth	R2	CLK2
		2
	GND			10-MSOP

		VDD	Si5351A 8-Output
			MultiSynth	R0	VDDOA
		PLL			CLK0
			0
		A
	XA		MultiSynth		CLK1
				R1
		OSC	1
					VDDOB
	XB	PLL	MultiSynth	R2
		B			CLK2
			2
			MultiSynth	R3	CLK3
			3
	A0				VDDOC
		I2C	MultiSynth	R4
					CLK4
	SDA		4
		Interface
			MultiSynth		CLK5
	SCL			R5
			5
					VDDOD
			MultiSynth	R6
	OEB				CLK6
		Control	6
	SSEN	Logic	MultiSynth	R7	CLK7
			7
		GND	20-QFN, 24-QSOP

Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices

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Si5351A/B/C

VDD	Si5351B

XA		PLL
	OSC
XB
		VCXO
VC
SDA	I2C
SCL	Interface
OEB	Control
SSEN	Logic

		GND
		VDD
XA		PLL
	OSC
		A
XB

PLL

CLKIN B

SDA

I2C

SCL Interface

INTR

	OEB	Control
		Logic

GND

	MultiSynth	R0	VDDOA
			CLK0
	0
	MultiSynth	R1	CLK1
	1
			VDDOB
	MultiSynth	R2
			CLK2
	2
	MultiSynth	R3	CLK3
	3
			VDDOC
	MultiSynth	R4
			CLK4
	4
	MultiSynth	R5	CLK5
	5
			VDDOD
	MultiSynth	R6
			CLK6
	6
	MultiSynth	R7	CLK7
	7
	20-QFN, 24-QSOP
		Si5351C
	MultiSynth	R0	VDDOA
			CLK0
	0
	MultiSynth	R1	CLK1
	1
			VDDOB
	MultiSynth	R2
			CLK2
	2
	MultiSynth	R3	CLK3
	3
			VDDOC
	MultiSynth	R4
			CLK4
	4
	MultiSynth	R5	CLK5
	5
			VDDOD
	MultiSynth	R6
			CLK6
	6
	MultiSynth	R7	CLK7
	7

20-QFN, 24-QSOP

Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices

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3. Functional Description

The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.

The input stage accepts an external crystal (XTAL), a clock input (CLKIN), or a control voltage input (VC) depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for generating output frequencies as low as 8 kHz. Crosspoint switches at each of the synthesis stages allows total flexibility in routing any of the inputs to any of the outputs.

Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to synthesize clocks for multiple clock domains in a design.

	Input	Synthesis	Synthesis
	Stage	Stage 1	Stage 2
			Multi
			Synth
			0
			Multi
CLKIN	Div		Synth
		PLL A	1
			Multi
		(SSC)
			Synth
	XA	PLL B	2
			Multi
XTAL	OSC	(VCXO)	Synth
			3
	XB		Multi
			Synth
			4
			Multi
			Synth
VC	VCXO		5
			Multi
			Synth
			6
			Multi
			Synth
			7

		Output
		Stage
	R0	VDDOA
		CLK0
	R1	CLK1
	R2	VDDOB
		CLK2
	R3	CLK3
	R4	VDDOC
		CLK4
	R5	CLK5
	R6	VDDOD
		CLK6
	R7	CLK7

Figure 3. Si5351 Block Diagram

3.1. Input Stage

3.1.1. Crystal Inputs (XA, XB)

The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or 27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.

Internal load capacitors (CL) are provided to eliminate the need for external components when connecting a crystal to the Si5351. Options for internal load capacitors are 6, 8, or 10 pF. Crystals with alternate load capacitance requirements are supported using additional external load capacitors as shown in Figure 4. Refer to application note AN551 for crystal recommendations.

CL XA

XB

CL

Optional

CL

CL Selectable internal

Additional external

load capacitors

load capacitors

6 pF, 8 pF, 10 pF

(< 2 pF)

Figure 4. External XTAL with Optional Load Capacitors

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3.1.2. External Clock Input (CLKIN)

The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs. CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to 30 MHz.

3.1.3. Voltage Control Input (VC)

The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, lowcost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.

The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.

A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same reference. An example is illustrated in Figure 9 on page 15.

3.2. Synthesis Stages

The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply the lower frequency input references to a high-frequency intermediate clock. The second stage uses highresolution MultiSynth fractional dividers to generate frequencies in the range of 1 MHz to 100 MHz. It is also possible to generate two unique frequencies up to 160 MHz on two or more of the outputs.

A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input. This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.

Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the range of ~391 kHz to 160 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.

Frequencies down to 8 kHz can be generated by applying the R divider at the output of the Multisynth (see Figure 5 below).

	XA	XB	Fixed Frequency
			Crystal (non-pullable)
	OSC		Multi	R0	CLK0
			Synth
			0
Control	VC		Multi	R1	CLK1
Voltage	VCXO		Synth
			1
			Multi	R2	CLK2
			Synth
			2

The clock frequency generated from CLK0 is controlled by the VC input

Additional MultiSynths can be “linked” to the VCXO to generate additional clock frequencies

Figure 5. Using the Si5351 as a Multi-Output VCXO

3.3. Output Stage

An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.

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3.4. Spread Spectrum

Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. See “AN554: Si5350/51 PCB Layout Guide” for details. Note that spread spectrum is not available on clocks synchronized to PLLB or to the VCXO.

The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise between system performance and EMI compliance.

	Center	Reduced	Reduced
		Amplitude	Amplitude
	Frequency
		and EMI	and EMI
	Amplitude

	fc	fc	fc
	No Spread	Center Spread	Down Spread
	Spectrum
		Figure 6. Available Spread Spectrum Profiles

3.5. Control Pins (OEB, SSEN)

The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.

3.5.1. Output Enable (OEB)

The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is held low, and disabled when pulled high. When disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance.

The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before going into a disabled state.

3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only

This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.

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4. I2C Interface

Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the I2C interface. The following is a list of the common features that are controllable through the I2C interface. A summary of register functions is shown in Section 7.

 Read Status Indicators

Loss of signal (LOS) for the CLKIN input Loss of lock (LOL) for PLLA and PLLB

Configuration of multiplication and divider values for the PLLs, MultiSynth dividers

Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)

Control of the cross point switch selection for each of the PLLs and MultiSynth dividers

Set output clock options

Enable/disable for each clock output Invert/non-invert for each clock output

Output divider values (2n, n=1.. 7)

Output state when disabled (stop hi, stop low, Hi-Z) Output phase offset

The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.

The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7. Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the I2C specification.

	VDD
>1k	>1k
	Si5351
	SCL
I2C Bus	SDA
4.7 k	INTR
I2C Address Select:	A0
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)

Figure 7. I2C and Control Signals

The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that require more than one Si5351 on a single I2C bus.

	6	5	4	3	2	1	0
Slave Address
	1	1	0	0	0	0	0/1

A0

Figure 8. Si5351 I2C Slave Address

Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7- bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write burst operation is also shown where every additional data word is written using to an auto-incremented address.

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Write Operation – Single Byte

S

Slv Addr [6:0]

0

A

Reg Addr [7:0]

A

Data [7:0]

A

P

Write Operation - Burst (Auto Address Increment)

S

Slv Addr [6:0]

0

A

Reg Addr [7:0]

A

Data [7:0]

A

Data [7:0]

A

P

Reg Addr +1

Fromslave to master

1 – Read

0 – Write

Frommaster to slave

A – Acknowledge (SDA LOW)

N– Not Acknowledge (SDAHIGH)

S – START condition

P – STOP condition

Figure 9. I2C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in Figure 10.

ReadOperation – Single Byte

S

Slv Addr [6:0]

0

A

Reg Addr [7:0]

A

P

S

Slv Addr [6:0]

1

A

Data [7:0]

N

P

ReadOperation - Burst (Auto Address Increment)

S

Slv Addr [6:0]

0

A

Reg Addr [7:0]

A

P

S

Slv Addr [6:0]

1

A

Data [7:0]

A

Data [7:0]

N

P

Reg Addr +1

Fromslave to master

1 – Read

0 – Write

Frommaster to slave

A – Acknowledge (SDA LOW)

N– Not Acknowledge (SDAHIGH)

S – START condition

P – STOP condition

Figure 10. I2C Read Operation

AC and DC electrical specifications for the SCL and SDA pins are shown in Table 7. The timing specifications and timing diagram for the I2C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility with SMBus interfaces.

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5. Configuring the Si5351

The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for applications that need a clock present at power-up (e.g., for providing a clock to a processor).

Power-Up

NVM

(OTP)

RAM

Default

Config

I2C

Figure 11. Si5351 Memory Configuration

During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the device configuration that will be used during normal operation. Any changes to the device configuration after power-up are made by reading and writing to registers in the RAM space through the I2C interface. A detailed register map is shown in Section "8. Register Descriptions" on page 25.

5.1. Writing a Custom Configuration to RAM

To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the EVB when connected to a host PC.

The optimal configuration can be saved from the software in text files that can be used in any system, which configures the device over I2C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and runs on Windows XP, Windows Vista, and Windows 7.

Once the configuration file has been saved, the device can be programmed via I2C by following the steps shown in Figure 12.

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Register

Map

Use ClockBuilder Desktop v3.1 or later

Disable Outputs

Set CLKx_DIS high; Reg. 3 = 0xFF

Powerdown all output drivers Reg. 16, 17, 18, 19, 20, 21, 22, 23 =

0x80

Set interrupt masks (see register 2 description)

Write new configuration to device using the contents of the register map

generated by ClockBuilder Desktop. This step also powers up the output drivers.

(Registers 15-92 and 149-170)

Apply PLLA and PLLB soft reset

Reg. 177 = 0xAC

Enable desired outputs (see Register 3)

Figure 12. I2C Programming Procedure

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5.2. Si5351 Application Examples

The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.

5.3. Replacing Crystals and Crystal Oscillators

Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for applications that require fewer clocks. An example is shown in Figure 13.

		XA		Multi	CLK0	125 MHz	Ethernet
				Synth			PHY
	27 MHz	OSC	PLL	0
					CLK1
				Multi		48 MHz	USB
				Synth			Controller
				1
				Multi	CLK2	28.322 MHz	HDMI
				Synth
							Port
				2	CLK3
				Multi		74.25 MHz
				Synth
				3	CLK4
				Multi		74.25/1.001 MHz
				Synth
				4	CLK5		Video/Audio
				Multi		24.576 MHz	Processor
				Synth
				5
				Multi	CLK6	22.5792 MHz
				Synth
				6
				Multi	CLK7	33.3333 MHz	CPU
		Si5351A		Synth
				7

Note: Si5351A replaces crystals, XOs, and PLLs.

Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs

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5.4. Replacing Crystals, Crystal Oscillators, and VCXOs

The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video applications. An example is shown in Figure 14.

					Free-running
					Clocks
XA			Multi	CLK0	125 MHz	Ethernet
						PHY
			Synth
27 MHz	OSC	PLL	0	CLK1
			Multi
XB					48 MHz	USB
			Synth			Controller
			1
			Multi	CLK2	28.322 MHz
			Synth
						HDMI
			2
						Port
VC			Multi	CLK3	74.25 MHz
			Synth
		VCXO	3	CLK4
			Multi
					74.25/1.001 MHz	Video/Audio
			Synth			Processor
			4
				CLK5
			Multi		24.576 MHz
			Synth
	Si5351B		5		Synchronous
					Clocks
Note: FBW = 10 kHz

Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs

5.5. Replacing Crystals, Crystal Oscillators, and PLLs

The Si5350C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO. Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running clocks. An example is shown in Figure 15.

					Free-running
					Clocks
XA			Multi	CLK0	125 MHz	Ethernet
						PHY
			Synth
25 MHz	OSC	PLL	0	CLK1
			Multi
XB					48 MHz	USB
			Synth			Controller
			1
			Multi	CLK2	28.322 MHz
			Synth
						HDMI
			2
						Port
			Multi	CLK3	74.25 MHz
CLKIN			Synth
54 MHz		PLL	3	CLK4
			Multi		74.25/1.001 MHz	Video/Audio
			Synth			Processor
			4
				CLK5
			Multi		24.576 MHz
			Synth
	Si5351C		5
					Synchronous
					Clocks

Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs

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5.6. Replacing a Crystal with a Clock

The Si5351 can be driven with a clock signal through the XA input pin.

VIN = 1 VPP
25/27 MHz	XA
	0.1 µF	OSC
	XB

Note: Float the XB input while driving the XA input with a clock

PLLA	Multi
	Synth
	0
	Multi
	Synth
	1
PLLB
	Multi
	Synth
	N

Figure 16. Si5351 Driven by a Clock Signal

5.7. HCSL Compatible Outputs

The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).

The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair must also be inverted to generate a differential pair. See register setting CLKx_INV.

PLLA

OSC

PLLB

Multi

Synth

0

Multi

Synth

1

Multi

Synth

N

ZO = 70	R1
0	511
	240	R2
ZO = 70	R1
0	511
	240	R2

Note: The complementary -180 degree out of phase output clock is generated using the INV function

HCSL CLKIN

Figure 17. Si5350C Output is HCSL Compatible

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6. Design Considerations

The Si5351 is a self-contained clock generator that requires very few external components. The following general guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for additional layout recommendations.

6.1. Power Supply Decoupling/Filtering

The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and VDDOx pins as possible without using vias.

6.2. Power Supply Sequencing

The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow flexibility in output signal levels. If a minimum output-to-output skew is important, then all VDDOx must be applied before VDD. Unused VDDOx pins should be tied to VDD.

6.3. External Crystal

The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more details.

6.4. External Crystal Load Capacitors

The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load capacitors are used, they should be placed as close to the XA/XB pads as possible. See AN554 for more details.

6.5. Unused Pins

Unused voltage control pin should be tied to GND. Unused CLKIN pin should be tied to GND.

Unused XA/XB pins should be left floating. Refer to "5.6. Replacing a Crystal with a Clock" on page 20 when using XA as a clock input pin.

Unused output pins (CLK0–CLK7) should be left floating. Unused VDDOx pins should be tied to VDD.

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6.6. Trace Characteristics

The Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default). It is recommended to configure the trace characteristics as shown in Figure 18 when an output drive setting of 8 mA is used.

ZO = 85 ohms

R = 0 ohms

CLK

(Optional resistor for EMI management)

Length = No Restrictions

Figure 18. Recommended Trace Characteristics with 8 mA Drive Strength Setting

Note: Jitter is only specified at 6 and 8 mA drive strength.

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