Siemens TDA4916GG Datasheet

SMPS-IC with MOSFET Driver Output TDA 4916 GG

Features

• High clock frequency

• Low current drain

• High reference accuracy

• All monitoring functions

P-DSO-24-1

Type Ordering Code Package

TDA 4916 GG Q67000-A9230 P-DSO-24-1

Functional Description and Application

The general-purpose single-ended switch-mode power supply device for the direct control of SIPMOS power transistors incorporates both digital and analog functions. These are required for the construction of high-quality flyback, forward and choke converters. The device can be likewise used for transformer-less voltage multipliers and variable-speed motors.

Faults occurring during operation of the switch-mode power supply are detected by comparators integrated in the device which initiate protective functions.

In addition, pairs of power supplies can be synchronized in antiphase. In-phase or antiphase synchronization is possible when more than two power supplies are involved.

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Pin Configuration

(top view)

TDA 4916 GG

P-DSO-24-1

Figure 1

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Pin Definitions and Functions Pin No. Symbol Function

1 0V GND GND

TDA 4916 GG

Supply voltage 3 0V QSIP Ground QSIP 4 Q SIP SIPMOS driver 5

QSIP Supply voltage driver

6 SF Series feed 7 – I K5/– I K6 Current sensor negative input 8 + I K5 Current sensor K5 9 + I K6 Current turn-OFF K6 10 Q K6 Output K6 11 PO Pulse omission 12

Soft start 13 I SYN Input synchronization 14 Q SYN Output synchronization 15 16

R C

Frequency generator

Frequency generator 17

Ramp generator 18 I K4 Input undervoltage 19 I K3 Input overvoltage 20 I K1 Input K1 21 Q OP Output operational amplifier 22 – I OP Input operational amplifier 23 + I OP Input operational amplifier 24

REF

Reference voltage

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TDA 4916 GG

Figure 2 Block Diagram

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TDA 4916 GG

Circuit Description

The individual functional sections of the device and their interactions are described below.

Power Supply at

The device does not enable the output until the turn-ON threshold ofVS is exceeded. The duty factor (active time/period) can then rise from zero to the value set with K1 in the time determined by the soft start. The turn-OFF threshold lies below the turn-ON threshold. Below the turn-OFF threshold the output Q SIP is reliably low.

Frequency Generator

The frequency is mainly determined by close-tolerance external components and the calibrated reference voltage.

The switching frequency at the output can be set by suitable choice of

and Ct.

The maximum possible duty factor can be reduced by a defined amount by means of a

resistor from defined amount by means of a resistor from

to 0V GND. The maximum possible duty factor can be increased by a

to VS.

Ramp Generator

The ramp generator is controlled by the frequency generator and operates with the same

frequency. Capacitor

on the ramp generator is discharged by an internally-set current

and charged via a current set externally. The duration of the falling edge of the ramp generator output must be shorter than its rise time. Only then do the upper and lower switching levels of the ramp generator signal have their nominal values.

In “voltage mode control” operation, the rising edge of the ramp generator signal is compared with an externally set dc voltage in comparator K1 for pulse-width control at the output. The slope of the rising edge is set by the current through source connected to

can be the SMPS input voltage. This makes it possible to control

. The voltage

the duty factor for a constant volt-second product at the output. This control option (precontrol) permits equalization of known disturbances (e.g. input voltage ripple).

Superimposed load current control (current mode control) can also be implemented. For this purpose the actual current at the source of the SIPMOS transistor is sensed and compared with the specified value in comparator K5.

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TDA 4916 GG

Comparator K1 (duty factor setting for voltage mode control)

The two plus inputs of the comparator are so connected that the lower plus level is always compared with the minus input level. As soon as the voltage of the rising edge of the sawtooth (minus input) exceeds the lower of the two plus input levels, the output is inhibited via the turn-OFF Flip-Flop, that is to say the High time of the output can be continuously varied. Since the frequency remains constant, this corresponds to a duty factor change.

Comparator K2

The comparator has a switching threshold at 1.5 V. Its output sets the fault Flip-Flop when the voltage on capacitor the setting pulse only if no reset pulse (fault) is applied. This prevents resetting of the output as long as a fault signal is present.

lies below 1.5 V. However, the fault Flip-Flop accepts

Comparators K3 (overvoltage), K4 (undervoltage), VS Undervoltage, V

REF

Overcurrent

These are fault detectors which cause the output to be inhibited immediately by the fault Flip-Flop when faults occur. When faults are no longer present, the duty factor is reestablished via the soft start

. In the event of undervoltage, a current is injected at

the input of K4 with the aid of which an adjustable hysteresis or latching is made possible. The value of the hysteresis is determined by the internal resistance of the external drive source and the current injected internally at the input of K4. In the event of undervoltage at K4, the injected current flows into the device.

Comparator K5 (duty factor setting for current mode control)

K5 is used to sense the source current at the switching transistor. The plus input of the comparator is fed out. Enabling of output Q SIP after cessation of the fault is effected with an H signal at the turn-OFF Flip-Flop output.

Comparator K6 (overcurrent turn-OFF)

The turn-OFF Flip-Flop is reset when overcurrent is detected by K6. In combination with the pulse-omission facility, individual pulses can then be omitted. This then results in a limited rise in the output current with a rising overload at the output.

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TDA 4916 GG

Operational Amplifier OP

Opamp OP is a high-quality operational amplifier. It can be used in the control circuit to transfer the variations in the voltage to be regulated in amplified form to the free plus input of comparator K1. As a result, a voltage change is converted into a duty factor change. The output of OP is an open collector. The frequency response of OP is already corrected. The plus input is connected internally via a capacitor to ground. This gives the inverting amplifier a more favorable phase response.

Turn-OFF Flip-Flop AFF

A pulse is fed to the set input of the turn-OFF Flip-Flop with the falling edge of the frequency generator signal. However, it can only really be set if no reset signal is applied. With a set turn-OFF Flip-Flop, the output is enabled and can be active. The Flip-Flop inhibits the output in the event of a turn-OFF signal from K1, K5, K6 or K7.

Fault Flip-Flop

Fault signals fed to the reset input of the fault Flip-Flop cause the output to be immediately disabled (Low), and to be turned on again via the soft start

after

removing fault-condition.

Soft Start

The smaller of the two voltages at the plus inputs of K1 - compared with the ramp generator voltage - is a measure of the duty factor at the output. At the instant the device is turned-ON, the voltage on capacitor

equals zero. Provided no fault exists, the

capacitor is charged up to its maximum value.

is discharged in the event of a fault. However, the fault Flip-Flop inhibits the output

immediately. Below a charging voltage of approx. 1.5 V, a set signal is applied to the fault Flip-Flop and the output is enabled, provided a reset signal is not applied simultaneously. However, since the minimum ramp generator voltage is about 1.8 V, the duty factor at the output is not actually slowly and continuously increased until the voltage on

The Z-diode limits the voltage on capacitor

exceeds a value of 1.8 V.

. The voltage at the ramp generator can

reach a higher level than the Zener voltage. With a suitable ramp generator rising edge slope, the duty factor can be limited to a wanted maximum value.

Pulse Omission PO

In the event of overcurrent in the SIPMOS transistors it is frequently necessary to omit pulses even with minimum duty factor. Only this measure ensures that the SIPMOS transistors cannot be overloaded. This wanted function can be achieved with Pulse Omission PO and Overcurrent Comparator K7 by means of a suitable external circuit.

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TDA 4916 GG

Reference Voltage V

REF

The reference voltage source makes available a source with a high-stability temperature characteristic which can be used for external connection to the operational amplifier, the fault comparators, the frequency generator, or to other external units. The voltage source is short-circuit-proof to ground.

Synchronization I SYN, Q SYN

The device has an input and an output for synchronization. In the case of a synchronized device (slave), its output Q SIP is in phase opposition to the output Q SIP of the synchronizing device (master). In the case of an unconnected input I SYN, or with connection to

, or also when a series capacitor (without switching transitions) is

REF

connected, the device receives its clock from the internal frequency generator in accordance with the circuit connected to it. As soon as switching transitions appear at I SYN, switchover to external synchronization and vice versa takes place after a delay. After a switchover process, a few clock cycles must elapse in addition to the delay before the frequency and phase achieve their steady states.

Series Feed SF

The Series Feed circuit section is used to turn-OFF the external series-feed transistor when energy recovery commences. As a result there is minimum power loss in the supply to the device. With the series-feed transistor turned-OFF, its drive current flows via VS to

SIPMOS Driver Output Q SIP

The output is High active. The time during which the output is active can be continuously varied.

The duration of the rising edge of the frequency generator signal is the minimum time during which the output can be Low.

The duration of the falling edge of the frequency generator signal is the maximum time during which the output can be High.

The output driver is designed as a push-pull stage. The output current is limited internally to the specified values.

Output Q SIP is connected via diodes to the supply

QSIP and 0V QSIP.

A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low

impedance in the event of undervoltage at

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TDA 4916 GG

When the supply to the switch-mode power supply is switched on, the capacitive displacement current from the gate of the SIPMOS transistor is conducted to the smoothing capacitor at

QSIP may reach about 2.3 V in the process without the SIPMOS transistor being

turned-ON. The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V.

Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS transistor can then flow away unimpeded.

The output is active Low with supply voltages at function of the diode connected to pull-down source.

The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits connections to be made to the SIPMOS transistor in such a way that the drive currents for the gate do not flow to the source via the current-sensing resistor. The maximum permissible level differences between 0V GND and 0V SQIP are given under Functional Range. If greater level differences are anticipated, it is better to join the two terminals.

QSIP by the diode connected to VSQSIP. The voltage at

and VSQSIP from about 4 V on. The

QSIP and the resistor are then taken over by the

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