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Packing
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Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
written appr oval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2with the express
32 Kbit (4096 × 8bit)SerialCMOS
2
EEPROMs, I
Preliminary
Features
• Data EEPROM internally organized as
4096 bytes and 128 pages × 32 bytes
• Page Protection Mode for protecting the
EEPROM against unintended data changes
(SLx 24C32.../P types only)
• Low power CMOS
V
•
• Two wire serial interface bus, I
• Three chip select pins to address 8 devices
• Filtered inputs for noise suppression with
= 2.7 to 5.5 V operation
CC
Schmitt trigger
C Synchronous 2-Wire Bus
2
C-Bus compatible
SLx 24C32
P-DIP-8-4
• Clock frequency up to 400 kHz
• High programming flexibility
– Internal programming voltage
– Self timed programming cycle including erase
– Byte-write and page-write programming, between
1 and 32 bytes
– Typical programming time 5 ms for up to 32 bytes
• High reliability
6
– Endurance 10
cycles
– Data retention 40 years
1)
1)
– ESD protection 4000 V on all pins
• 8 pin DIP/DSO packages
• Available for extended temperature ranges
– Industrial:− 40 °C to + 85 °C
– Automotive:− 40 °C to + 125 °C
P-DSO-8-3
1)
Values are temperature dependent, for further information please refer to your Siemens sales office.
Semiconductor Group3Preliminary 1998-07-27
SLx 24C32
Ordering Information
TypeOrdering CodePackageTemperatureVoltage
SLA 24C32-D
SLA 24C32-D/P
SLA 24C32-S
SLA 24C32-S/P
SLA 24C32-D-3
SLA 24C32-D-3/P
SLA 24C32-S-3
SLA 24C32-S-3/P
SLE 24C32-D
SLE 24C32-D/P
SLE 24C32-S
SLE 24C32-S/P
Q67100-H3746
Q67100-H3752
Q67100-H3748
Q67100-H3753
Q67100-H3747
Q67100-H3754
Q67100-H3749
Q67100-H3769
Q67100-H3235
Q67100-H3755
Q67100-H3236
Q67100-H3756
P-DIP-8-4– 40 °C … + 85 °C 4.5 V...5.5 V
P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V
P-DIP-8-4– 40 °C … + 85 °C 2.7 V...5.5 V
P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V
P-DIP-8-4– 40°C … + 125 °C 4.5 V...5.5 V
P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V
Other types are available on request:
– Temperature range (– 55 °C … + 150 °C)
– Package (die, wafer delivery)
– 3V types with automotive temperature range (– 40 °C … + 125 °C)
1Pin Configuration
CS0
CS2
18
CS1
V
SS
IEP02125
Figure 1
Pin Configuration (top view)
P-DSO-8-3P-DIP-8-4
V
CC
72
WP
SCL63
SDA54
CS0
CS1
CS2
V
SS
1
2
3
4
IEP02124
V
8
CC
7
WP
6
SCL
SDA
5
Semiconductor Group4Preliminary 1998-07-27
Pin Definitions and Functions
Table 1
Pin No.SymbolFunction
1, 2, 3CS0, CS1, CS2Chip select inputs
SLx 24C32
4
V
SS
Ground
5SDASerial bidirectional data bus
6SCLSerial clock input
7WPWrite protection input
8
V
CC
Supply voltage
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA
V
bus requires a pull-up resistor to
CC
.
Chip Select (CS0, CS1, CS2)
The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven
V
to
or VSS. These inputs allow the selection of one of eight possible devices sharing
CC
acommonbus.
Write Protection (WP)
V
WP switched to
WP switched to
Semiconductor Group5Preliminary 1998-07-27
allows normal read/write operations.
SS
V
protects the EEPROM against changes (hardware write protection).
CC
SLx 24C32
2Description
The SLx 24C32 device is a serial electrically erasable and programmable read only
memory (EEPROM), organized as 4096 × 8 bit. The data memory is divided into
128 pages. The 32 bytes of a page can be programmed simultaneously.
2
The device conforms to the specification of the 2-wire serial I
2
pins allow the addressing of 8 devices on the I
C-Bus. Low voltage design permits
operation down to 2.7 V with low active and standby currents. All devices have a
6
minimum endurance of 10
erase/write cycles.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at
2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V
V
type (
applications and as 3 V type (
= 4.5 … 5.5 V) with two temperature ranges for industrial and automotive
CC
V
= 2.7 … 5.5 V) for industrial applications. The
CC
EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.
C-Bus. Three chip select
SCL
SDA
V
SS
V
CC
Start/
Stop
Logic
CS0CS1CS2
Chip Address
Control
Logic
Serial
Control
Logic
Address
Logic
WP
Programming
Control
H.V. Pump
X
DEC
EEPROM
Page Logic
Y DEC
Dout/ACK
IEB02525
Figure 2
Block Diagram
Semiconductor Group6Preliminary 1998-07-27
SLx 24C32
3I2C-Bus Characteristics
2
AccesstotheSLx24C32deviceisgivenviatheI
of two wires SCL and SDA for clock and data. The protocol is master/slave oriented,
where the serial EEPROM always takes the role of a slave.
Slave 1Slave 2Slave 3Slave 4
SCL
Master
SDA
C bus. This bidirectional bus consists
V
CC
Slave 8Slave 5Slave 6Slave 7
V
CC
IES02183
Figure 3
Bus Configuration
MasterDevice that initiates the transfer of data and provides the clock for transmit
and receive operations.
SlaveDevice addressed by the master, capable of receiving and transmitting
data.
TransmitterThe device using the SDA as output is defined as the transmitter. Due to
the open drain characteristic of the SDA output the device applying a low
level wins.
ReceiverThe device using the SDA as input is defined as the receiver.
Semiconductor Group7Preliminary 1998-07-27
SLx 24C32
The conventions for the serial clock line and the bidirectional data line are shown in
figure 4.
SCL
SDA
START ConditionData allowedSTOP Condition
12
to Change
8
Acknowledge
9
ACKACK
1
9
IED02128
Figure 4
2
C-Bus Timing Conventions for START Condition, STOP Condition, Data
I
Validation and Transfer of Acknowledge ACK
StandbyMode in which the bus is not busy (no serial transmission, no
programming): both clock (SCL) and data line (SDA) are in high
state. The device enters the standby mode after a STOP condition
or after a programming cycle.
START ConditionHigh to low transition of SDA when SCL is high, preceding all
commands.
STOP ConditionLow to high transition of SDA when SCL is high, terminating all
communications. A STOP condition after writing data initiates an
EEPROM programming cycle. A STOP condition after reading
data from the EEPROM initiates the standby mode.
AcknowledgeA successful reception of eight data bits is indicated by the
receiver by pulling down the SDA line during the following clock
cycle of SCL (ACK). The transmitter on the other hand has to
release the SDA line after the transmission of eight data bits.
TheEEPROM asthe receivingdeviceresponds withan
acknowledge, when addressed. The master, on the other side,
acknowledges each data byte transmitted by the EEPROM and
can at any time end a read operation by releasing the SDAline (no
ACK) followed by a STOP condition.
Data TransferData must change only during low SCL state, data remains valid
on the SDA bus during high SCL state. Nine clock pulses are
required to transfer one data byte, the most significant bit (MSB)
is transmitted first.
Semiconductor Group8Preliminary 1998-07-27
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