Siemens SAB-C501G-L24N, SAB-C501G-L24P, SAB-C501G-L40M, SAB-C501G-L40N, SAB-C501G-L40P Datasheet
...
Microcomputer Components
8-Bit CMOS Microcontroller
C501
Data Sheet 04.97
C501 Data Sheet
Revision History :
1997-04-01
Previous Releases : 11.92, 11.93, 08.94, 08.95, 10.96
Page
(previous
version)
Page
(new
version)
Subjects (changes since last revision)
general C501G-1E OTP version included
4
5
5-7
11
8, 9, 10
4
5
5-7
11
8, 9, 10
Ordering information resorted and C501G-1E types added
Table with literature hints added
Pin configuration logic symbol for pins EA
Pin description for ALE/PROG and EA/Vpp completed
Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi-
bidirectional”
13
14
15-18
17
-
41
-
13
14
15
16-18
17
25-28
31
41
43, 44
Block diagram updated for C501G-1E
New design of register (PSW) description
“Memory organization” added
Actualized design of the SFR tables
Reset value of T2CON corrected
Description for the C501-1E OTP version added
DC characteristics for C501-1E added
Timing “External Clock Drive” now behind “Data Memory Cycle”
AC characteristics for C501-1E added
/Vpp and ALE/PROG updated
Edition 1997-04-01
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
2
with the express
8-Bit CMOS Microcontroller
Preliminary
Fully compatible to standard 8051 microcontroller
•
Versions for 12/24/40 MHz operating frequency
•
Program memory : completely external (C501-L)
•
8K × 8 ROM (C501-1R)
8K × 8 OTP memory (C501-1E)
256 × 8 RAM
•
Four 8-bit ports
•
Three 16-bit timers / counters (timer 2 with up/down counter feature)
•
USART
•
Six interrupt sources, two priority levels
•
Power saving modes
•
Quick Pulse programming algorithm (C501-1E only)
•
2-Level program memory lock (C501-1E only)
•
P-DIP-40, P-LCC-44, and P-MQFP-44 package
•
Temperature ranges : SAB-C501
•
SAF-C501
: 0 ˚C to 70 ˚C
T
A
: – 40 ˚C to 85 ˚C
T
A
C501
C501
Power
Saving
Modes
T2
Figure 1
C501G Functional Units
RAM
256 x 8
T0
CPU
T1
8K x 8 ROM (C501-1R)
8K x 8 OTP (C501-1E)
USART
Port 0
Port 1
Port 2
Port 3
Ι
/O
Ι
/O
Ι
/O
Ι
/O
MCA03238
Semiconductor Group 3 1997-04-01
C501
The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/
write data memory, four ports, three 16-bit timers counters, a seven source, two priority level
interrupt structure and a serial port. The C501-L is identical, except that it lacks the program
memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip.
The term C501 refers to all versions within this specification unless otherwise noted. Further, the
term C501 refers to all versions which are available in the different temperature ranges, marked with
SAB-C501... or SAF-C501.... .
Ordering Information
Type Ordering Code Package Description
(8-Bit CMOS microcontroller)
SAB-C501G-LN
SAB-C501G-LP
SAB-C501G-LM
SAB-C501G-L24N
SAB-C501G-L24P
SAB-C501G-L24M
SAB-C501G-L40N
SAB-C501G-L40P
SAB-C501G-L40M
SAF-C501G-L24N
SAF-C501G-L24P
SAB-C501G-1RN
SAB-C501G-1RP
SAB-C501G-1RM
SAB-C501G-1R24N
SAB-C501G-1R24P
SAB-C501G-1R24M
SAB-C501G-1R40N
SAB-C501G-1R40P
SAB-C501G-1R40M
Q67120-C969
Q67120-C968
Q67127-C970
Q67120-C1001
Q67120-C999
Q67127-C1014
Q67120-C1002
Q67120-C1000
Q67127-C1009
Q67120-C1011
Q67120-C1010
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
Q67120-DXXX
Q67120-DXXX
Q67127-DXXX
P-LCC-44
P-DIP-40
P-MQFP-44
P-LCC-44
P-DIP-40
P-MQFP-44
P-LCC-44
P-DIP-40
P-MQFP-44
P-LCC-44
P-MQFP-44
P-LCC-44
P-DIP-40
P-MQFP-44
P-LCC-44
P-DIP-40
P-MQFP-44
P-LCC-44
P-DIP-40
P-MQFP-44
for external memory (12 MHz)
for external memory (24 MHz)
for external memory (40 MHz)
for external memory (24 MHz)
ext. temp. – 40 ˚C to 85 ˚C
with mask-programmable ROM (12 MHz)
with mask-programmable ROM (24 MHz)
with mask-programmable ROM (40 MHz)
SAF-C501G-1R24N
SAF-C501G-1R24P
SAB-C501G-1EN
SAB-C501G-1EP
SAF-C501G-1EN
SAF-C501G-1EP
SAB-C501G-1E24N
SAB-C501G-1E24P
SAF-C501G-1E24N
SAF-C501G-1E24P
Semiconductor Group 4 1997-04-01
Q67120-DXXX
Q67120-DXXX
Q67120-C1054
Q67120-C1056
Q67120-C2002
Q67120-C2003
Q67120-C2005
Q67120-C2006
Q67120-C2008
Q67120-C2009
P-LCC-44
P-DIP-40
P-LCC-44
P-DIP-40
P-LCC-44
P-DIP-40
P-LCC-44
P-DIP-40
P-LCC-44
P-DIP-40
with mask-programmable ROM (24 MHz)
ext. temp. – 40 ˚C to 85 ˚C
with OTP memory (12 MHz)
with OTP memory (12 MHz))
ext. temp. – 40 ˚C to 85 ˚C
with OTP memory (24 MHz)
with OTP memory (24 MHz))
ext. temp. – 40 ˚C to 85 ˚C
Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request.
The ordering number of ROM types (DXXX extensions) is defined after program release
(verification) of the customer.
Additional Literature
For further information about the C501 the following literature is available :
Title Ordering Number
C501 8-Bit CMOS Microcontroller User’s Manual B158-H6723-X-X-7600
C501
C500 Microcontroller Family
B158-H6987-X-X-7600
Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600
CC
P0.1/AD1
P1.3
P1.4
6 5 4 3 2 1 44 43 42 41 40
P1.5
P1.6
P1.7
RESET P0.7/AD7
RxD/P3.0
N.C.
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
8
9
10
11
12
13
14
15
16
17
P1.2
P1.1/T2EX
N.C
P1.0/T2
C501
P0.0/AD0
V
P0.3/AD3
P0.2/AD2
397
38
37
36
35
34
33
32
31
30
29
2827262524232221201918
P0.4/AD4
P0.5/AD5
P0.6/AD6
EA/
V
PP
N.C.
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
MCP03214
XTAL2
RD/P3.7
WR/P3.6
SS
V
XTAL1
N.C.
P2.1/A9
P2.0/A8
P2.3/A11
P2.2/A10
P2.4/A12
Figure 2
Pin Configuration P-LCC-44 Package (Top view)
Semiconductor Group 5 1997-04-01
C501
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RxD/P3.0
TxD/P3.1
INT0/P3.2
1
2
3
4
5
6
7
8
9
10
11
12
C501
40
39
38
37
36
35
34
33
32
31
30
29
V
CC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7RESET
EA/
V
PP
ALE/PROG
PSEN
INT1/P3.3
13
14
T1/P3.5
15
16
RD/P3.7
XTAL2
XTAL1
17
18
19
20
V
SS
Figure 3
Pin Configuration P-DIP-40 Package (top view)
28
27
26
25
24
23
22
21
MCP03215
P2.7/A15
P2.6/A14T0/P3.4
P2.5/A13
P2.4/A12WR/P3.6
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
Semiconductor Group 6 1997-04-01
P0.6/AD6
P0.5/AD5
P0.4/AD4
PP
V
EA/
N.C.
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
C501
P0.3/AD3
33
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
N.C.
C501
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4 WR/P3.6
44 12
P1.5
P1.6
P1.7
N.C.
RESET P0.7/AD7
RxD/P3.0
Figure 4
Pin Configuration P-MQFP-44 Package (top view)
10987654321
TxD/P3.1
INT0/P3.2
INT1/P3.3
23242526272829303132
2234
2135
2036
1937
1838
1739
1640
1541
1442
1343
11
T0/P3.4
T1/P3.5 P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
N.C.
V
SS
XTAL1
XTAL2
RD/P3.7
MCP03216
VV
CC
XTAL1
XTAL2
SS
Port 0
8-Bit Digital
Ι/O
Port 1
/OΙ8-Bit Digital
RESET
EA
/
V
PP
C501
Port 2
/OΙ8-Bit Digital
ALE/PROG
Port 3
PSEN
MCL03217
/OΙ8-Bit Digital
Figure 5
Logic Symbol
Semiconductor Group 7 1997-04-01
Table 1
Pin Definitions and Functions
Symbol Pin Number I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
P1.0 – P1.7 2–9
2
3
*) I = Input
O = Output
1–8
1
2
40–44,
1–3,
40
41
I/O Port 1
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 1 pins that
have 1s written to them are pulled high by
the internal pullup resistors, and in that
state can be used as inputs. As inputs,
port 1 pins being externally pulled low will
source current (
istics) because of the internal pull-up
resistors. Port 1 also contains the timer 2
pins as secondary function. The output
latch corresponding to a secondary
function must be pro-grammed to a one
(1) for that function to operate.
The secondary functions are assigned to
the pins of port 1, as follows:
P1.0 T2 Input to counter 2
P1.1 T2EX Capture - Reload trigger of
I
, in the DC character-
IL
timer 2 / Up-Down count
Semiconductor Group 8 1997-04-01
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
P3.0 – P3.7 11,
13–19
11
13
14
15
16
17
18
19
10–17
10
11
12
13
14
15
16
17
5, 7–13
5
7
8
9
10
11
12
13
I/O Port 3
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 3 pins that
have 1s written to them are pulled high by
the internal pull-up resistors, and in that
state they can be used as inputs. As
inputs, port 3 pins being externally pulled
low will source current (
characteristics) because of the internal
pull-up resistors. Port 3 also contains the
interrupt, timer, serial port 0 and external
memory strobe pins which are used by
various options. The output latch
corresponding to a secondary function
must be programmed to a one (1) for that
function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
P3.0 R × D receiver data input (asyn-
P3.1 T × D transmitter data output
P3.2 INT
P3.3 INT1 interrupt 1 input/timer 1
P3.4 T0 counter 0 input
P3.5 T1 counter 1 input
P3.6 WR the write control signal lat-
P3.7 RD the read control signal
I
, in the DC
IL
chronous) or data input
output (synchronous) of
serial interface 0
(asynchronous) or clock
output (synchronous) of
the serial interface 0
0 interrupt 0 input/timer 0
gate control
gate control
ches the data byte from
port 0 into the external
data memory
enables the external data
memory to port 0
*) I = Input
O = Output
Semiconductor Group 9 1997-04-01
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
XTAL2 20 18 14 –
XTAL2
Output of the inverting oscillator
amplifier.
XTAL1 21 19 15 –
XTAL1
Input to the inverting oscillator amplifier
and input to the internal clock generator
circuits.
To drive the device from an external
clock source, XTAL1 should be driven,
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, since the input
to the internal clocking circuitry is divided
down by a divide-by-two flip-flop.
Minimum and maximum high and low
times as well as rise fall times specified
in the AC characteristics must be
observed.
P2.0 – P2.7 24–31 21–28 18–25 I/O Port 2
is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high
by the internal pull-up resistors, and in
that state they can be used as inputs. As
inputs, port 2 pins being externally pulled
low will source current (
characteristics) because of the internal
pull-up resistors. Port 2 emits the highorder address byte during fetches from
external program memory and during
accesses to external data memory that
use 16-bit addresses (MOVX @DPTR).
In this application it uses strong internal
pull-up resistors when issuing 1s. During
accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port
2 issues the contents of the P2 special
function register.
, in the DC
I
IL
*) I = Input
O = Output
Semiconductor Group 10 1997-04-01
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
C501
PSEN
32 29 26 O
RESET 10 9 4 I
ALE/PROG
33 30 27 I/O The Address Latch Enable
The Program Store Enable
output is a control signal that enables the
external program memory to the bus
during external fetch operations. It is
activated every six oscillator periods
except during external data memory
accesses. Remains high during internal
program execution.
RESET
A high level on this pin for two machine
cycles while the oscillator is running
resets the device. An internal diffused
resistor to
using only an external capacitor to
permits power-on reset
V
SS
.
V
CC
output is used for latching the low-byte of
the address into external memory during
normal operation. It is activated every six
oscillator periods except during an
external data memory access.
For the C501-1E this pin is also the
program pulse input (PROG) during OTP
memory programming.
EA
/
V
PP
35 31 29 I
External Access
Enable
When held at high level, instructions are
fetched from the internal ROM (C501-1R
and C501-1E) when the PC is less than
2000H. When held at low level, the C501
fetches all instructions from external
program memory. For the C501-L this
pin must be tied low.
This pin also receives the programming
supply voltage
V
during OTP memory
PP
programming (C501-1E) only).
*) I = Input
O = Output
Semiconductor Group 11 1997-04-01
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-LCC-44 P-DIP-40 P-MQFP-44
P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0
is an 8-bit open-drain bidirectional I/O
port. Port 0 pins that have 1s written to
them float, and in that state can be used
as high-impedance inputs. Port 0 is also
the multiplexed low-order address and
data bus during accesses to external
program or data memory. In this
application it uses strong internal pull-up
resistors when issuing 1s.
Port 0 also outputs the code bytes during
program verification in the C501-1R and
C501-1E. External pull-up resistors are
required during program verification.
C501
V
SS
V
CC
22 20 16 – Circuit ground potential
44 40 38 – Supply terminal for all operating modes
N.C. 1, 12,
23, 34
*) I = Input
O = Output
– 6, 17,
28, 39
– No connection
Semiconductor Group 12 1997-04-01
C501
Functional Description
The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational
characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the
timer 2 unit.
Figure 6 shows a block diagram of the C501.
V
CC
V
SS
XTAL1
XTAL2
RESET
ALE/PROG
PSEN
EA/
V
PP
C501
OSC & Timing
Serial Channel
CPU
Timer 0
Timer 1
Timer 2
Interrupt Unit
(USART)
RAM
256 x 8
C501-1R : ROM
C501-1E : OTP
8K x 8
Port 0
Port 1
Port 2
Port 3
Port 0
8-Bit Digit.
Port 1
8-Bit Digit.
Port 2
8-Bit Digit.
Port 3
8-Bit Digit.
Ι/O
Ι/O
Ι/O
/OΙ
MCB03219
Figure 6
Block Diagram of the C501
Semiconductor Group 13 1997-04-01
C501
CPU
The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs
24 MHz: 500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0H) Reset Value : 00H
Bit No. MSB LSB
H
D7
CY AC
H
D6
H
D5
F0
H
D4
RS1 RS0 OV F1 PD0
Bit Function
CY Carry Flag
Used by arithmetic instruction.
AC Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1 RS0 Function
0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F
H
D3
H
D2
H
D1
H
D0
H
PSW
H
H
H
H
OV Overflow Flag
Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group 14 1997-04-01
Memory Organization
The C501 CPU manipulates data and operands in the following four address spaces:
– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128 byte special function register area
Figure 7 illustrates the memory address spaces of the C501.
C501
External
Internal
"Code Space"
FFFF
2000
External
(EA = 0)(EA = 1)
H
H
1FFF
0000
FFFF
H
External
Indirect
Address
FF
H
Internal
RAM
80
H
H
0000
H
"Data Space" "Internal Data Space"
H
Internal
RAM
Direct
Address
Special
Function
Register
7F
H
00
H
MCD03224
FF
80
H
H
Figure 7
C501 Memory Map
Semiconductor Group 15 1997-04-01
C501
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.
The 27 special function registers (SFRs) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits
0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Semiconductor Group 16 1997-04-01
C501
Table 2
Special Function Registers - Functional Blocks
Block Symbol Name Address Contents after
Reset
CPU ACC
B
DPH
DPL
PSW
SP
Interrupt
System
IE
IP
Ports P0
P1
P2
P3
Serial
Channel
PCON
SBUF
SCON
Timer 0 /
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 2 T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Pow. Sav.
PCON
Modes
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
Interrupt Enable Register
Interrupt Priority Register
Port 0
Port 1
Port 2
Port 3
2)
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, High Byte
Timer 2 Reload/Capture Register, Low Byt
Timer 2 High Byte
Timer 2 Low Byte
2)
Power Control Register 87
E0
F0
83
82
D0
81
A8
B8
80
90
A0
B0
87
99
98
88
8C
8D
8A
8B
89
C8
C9
CB
CA
CD
CC
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
00
H
00
H
00
H
00
H
00
H
07
H
0X000000
XX000000
FF
H
FF
H
FF
H
FF
H
0XXX0000
3)
XX
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
XXXXXXX0
00
H
00
H
00
H
00
H
0XXX0000
3)
B
3)
B
3)
B
3)
B
3)
B
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
Semiconductor Group 17 1997-04-01
Table 3
Contents of the SFRs, SFRs in numeric order of their addresses
C501
Addr Register Content
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
after
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
SMOD – – – GF1 GF0 PDE IDLE
B
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
GATE C/T M1 M0 GATE C/T M1 M0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
SM0 SM1 SM2 REN TB8 RB8 TI RI
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
EA – ET2 ES ET1 EX1 ET0 EX0
B
RD WR T1 T0 INT1 INT0 TxD RxD
– – PT2 PS PT1 PX1 PT0 PX0
B
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
–––––––DCEN
B
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CY AC F0 RS1 RS0 OV F1 P
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
Reset
2)
80
81
82
83
87
P0 FF
H
SP 07
H
DPL 00
H
DPH 00
H
PCON 0XXX-
H
0000
2)
88
89
TCON 00
H
TMOD 00
H
8AHTL0 00
8BHTL1 00
8CHTH0 00
8DHTH1 00
2)
90
98
99
A0
A8
P1 FF
H
2)
SCON 00
H
SBUF XX
H
2)
P2 FF
H
2)
IE 0X00-
H
0000
2)
B0
B8
P3 FF
H
2)
IP XX00.
H
0000
2)
C8
T2CON 00
H
C9HT2MOD XXXX-
XXX0
CAHRC2L 00
CBHRC2H 00
CCHTL2 00
CDHTH2 00
2)
D0
E0
F0
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
PSW 00
H
2)
ACC 00
H
2)
B 00
H
Semiconductor Group 18 1997-04-01
Timer / Counter 0 and 1
Timer/counter 0 and 1 can be used in four operating modes as listed in table 4.
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock
C501
0 8-bit timer/counter with a
Gate C/T
XX00
M1 M0 internal external (max)
f
OSC/12 × 32
f
OSC/24 × 32
divide-by-32 prescaler
1 16-bit timer/counter X X 1 1 f
2 8-bit timer/counter with
XX00f
OSC/12
OSC/12
f
OSC/24
f
OSC/24
8-bit autoreload
3 Timer/counter 0 used as one
XX11f
OSC/12
f
OSC/24
8-bit timer/counter and one
8-bit timer
Timer 1 stops
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f
OSC
/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f
/24. External inputs INTO and INT1 (P3.2, P3.3) can be
OSC
programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the
input clock logic.
f
OSC
P3.4/T0
P3.5/T1
max
P3.2/INT0
P3.3/INT1
f
OSC
/24
TR 0/1
TCON
Gate
TMOD
=1
Figure 8
Timer/Counter 0 and 1 Input Clock Logic
f
÷
12
C/T
TMOD
0
1
Control
&
_
<
1
MCS01768
/12
OSC
Timer 0/1
Input Clock
Semiconductor Group 19 1997-04-01
C501
Timer 2
Timer 2 is a 16-bit timer/counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Table 5
Timer/Counter 2 Operating Modes
Mode
16-bit
Autoreload
16-bit
Capture
Baud
Rate
Generator
R×CLK
or
T×CLK
0
0
0
0
0
0
1
1
T2CON T2MOD
CP/
RL2
TR2 internal
DCEN
0
0
0
0
1
1
X
X
1
1
1
1
1
1
1
1
0
0
1
1
X
X
X
X
T2CON
EXEN
0
1
X
X
0
1
0
1
P1.1/
T2EX
Remarks
X
reload upon
overflow
↓
reload trigger
(falling edge)
0
Down counting
1
Up counting
X↓16 bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
X↓no overflow
interrupt
request (TF2)
extra external
interrupt
(“Timer 2”)
Input Clock
f
/12
OSC
f
/12
OSC
f
/2
OSC
external
(P1.0/T2)
max
f
/24
OSC
max
f
/24
OSC
max
f
/24
OSC
off X X 0 X X X Timer 2 stops – –
Note: ↓ = falling edge
Semiconductor Group 20 1997-04-01
C501
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 7.
Table 6
USART Operating Modes
Mode
SCON Baudrate Description
SM0 SM1
000
f
/12 Serial data enters and exits through R×D.
OSC
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
1 0 1 Timer 1/2 overflow rate 8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
210
f
/32 or f
OSC
OSC
/64 9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
3 1 1 Timer 1/2 overflow rate 9-bit UART
Like mode 2 except the variable baud rate
Table 7
Formulas for Calculating Baudrates
Baud Rate
Interface Mode Baudrate
derived from
Oscillator 0
Timer 1 (16-bit timer)
(8-bit timer with
2
1,3
1,3
(2
(2
SMOD
SMOD
× timer 1 overflow rate) /32
× f
f
/12
OSC
SMOD
(2
OSC
× f
OSC
) / 64
) / (32 × 12 × (256-TH1))
8-bit autoreload)
f
Timer 2 1,3
/ (32 × (65536-(RC2H, RC2L))
OSC
Semiconductor Group 21 1997-04-01
C501
Interrupt System
The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of
the interrupt sources and illustrates the request and control flags.
P1.1/
T2EX
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
EXEN2
T2CON.3
USART
TCON.0
TF2
T2CON.7
EXF2
T2CON.6
RI
SCON.0
TI
SCON.1
TF0
TCON.5
TF1
TCON.7
_
<
1
_
<
1
ET0
IE.1 IP.1
ET1
IE.3
ET2
IE.5 IP.5
ES
PT0
PT1
IP.3
PT2
PS
IP.4IE.4
High Priority
Low Priority
P3.2/
INT0
IT0
TCON.0
P3.3/
INT1
IT1
TCON.2
Figure 9
Interrupt Request Sources
IE0
TCON.1
IE1
TCON.3
EX0
IE.0 IP.0
EX1
IE.2 IP.2
EA
IE.7
PX0
PX1
MCS01783
Semiconductor Group 22 1997-04-01
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags) Vector Vector Address
C501
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 9
Interrupt Priority-Within-Level
Interrupt Source Priority
External Interrupt 0,
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Serial Channel,
Timer 2 Interrupt,
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
High
↓
Low
0003
000B
0013
001B
0023
002B
H
H
H
H
H
H
Semiconductor Group 23 1997-04-01
C501
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode,
respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down
mode takes precedence. Table 10 gives a general overview of the power saving modes.
Table 10
Power Saving Modes Overview
Mode Entering
Leaving by Remarks
Instruction
Example
Idle mode ORL PCON, #01H – enabled interrupt
– Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power-Down
Mode
ORL PCON, #02H Hardware Reset Oscillator is stopped, contents
of on-chip RAM and SFR’s are
maintained (leaving Power
Down Mode means redefinition
of SFR contents).
In the Power Down mode of operation,
be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that V
V
can be reduced to minimize power consumption. It must
CC
CC
is restored to its normal operating level, before the Power Down mode is terminated. The reset
signal that terminates the Power Down mode also restarts the oscillator. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long enough
to allow the oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group 24 1997-04-01
C501
OTP Operation
The C501-1E is programmed by usng a modified Quick-Pulse Programming
from older methods in the value used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and
used by a programming system to identify the device. The signature bytes identify the manufacturer
of the device.
Table 11 shows the logic levels for reading the signature byte, and for programming the program
memory, the encryption table, and the security bits. The circuit configuration and waveforms for
quick-pulse programming are shown in figures 10 to 12.
Table 11
OTP Programming Modes
TM 1)
algorithm. It differs
Mode RESET PSEN ALE/
EA/V
P2.7 P2.6 P3.7 P3.6
PP
PROG
Read signature 1 0 1 1 0000
Program code data 1 0 0 V
PP
1011
Verify code data 1 0 1 1 0011
Progam encryption table 1 0 0 V
Program security bit 1 1 0 0 V
Program security bit 2 1 0 0 V
PP
PP
PP
1010
1111
1100
Notes :
1. “0” = valid low for that pin, “1” = valid high for that pin.
2. V
3. V
4. ALE/PROG
= 12.75 V ± 0.25V
PP
= 5 V ± 10% during programming and verification.
CC
receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for
100 µs (±
10 µs) and high for a minimum of 10 µs.
1)
Quick-Pulse ProgrammingTM is a trademark phrase of Intel Corporation
Semiconductor Group 25 1997-04-01
C501
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in figure 10. Note that the C5011E is running with a 4 to 6 MHz oscillator The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the OTP memory location to be programmed is applied to port 1 and 2 as shown in
figure 10. The code byte to be programmed into that location is applied to port 0. RESET, PSEN
and pins of port 2 and 3 specified in table 11 are held at the “Program code data“ levels. The ALE/
PROG signal is pulsed low 25 times as shown in figure 11.
For programming of the encryption table, the 25 pulse programming sequence must be repeated for
addresses 0 through 1FH, using the “Program encrytion table“ levels. After the encryption table is
programmed, verification cycles will produce only encrypted data.
For programming of the security bits, the 25 pulse programming sequence must be repeat using the
“Program security bit“ levels. After one security bit is programmed, further programming of the code
memory and encryption table is disabled. However, the other security bit can still be programmed.
Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level. for any
amount of time. Even a narrow glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches and overshoots.
Program Verification
If security bit 2 has not been programmed, the on-chip OTP program memory can be read out for
program verification. The address of the OTP program memory locations to be read is applied to
ports 1 and 2 as shown in figure 12. The other pins are held at the “Verify code data“ levels
indicated in table 11. The contents of the address location will be emitted on port 0. External pullups
are required on port 0 for this operation.
If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR
of the program byte with one of the encryption bytes. The user will have to know the encryption
table contents in order to correctly decode the verification data. The encryption table itself cannot be
read out.
Reading the SIgnature Bytes
The signature bytes are read by the same procedure as a normal verification of loctions 30H and
31H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are :
30H = E0H indicates manufacturer
31H = 71H indicates C501-1E
Semiconductor Group 26 1997-04-01
+5 V
C501
A0 - A7
Port 1
C501-1E
1
1
1
4 - 6 MHz
Figure 10
C501-1E OTP Memory Programming Configuration
RESET
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
Port 0
V
EA/
PP
ALE/PROG
PSEN
P2.7
P2.6
P2.0 - P2.4
MCS03232
Programming
Data
+12.75 V
25 x 100 s
µ
Low Pulses
0
1
0
A8 - A12
ALE/PROG
1
ALE/PROG
0
Figure 11
C501-1E ALE/PROG Waveform
25 Pulses
µµµ
10 s min.
MCT03234
Semiconductor Group 27 1997-04-01
+5 V
C501
A0 - A7
1
1
1
Port 1
RESET
P3.6
P3.7
XTAL2
4 - 6 MHz
XTAL1
V
Figure 12
C501-1E OTP Memory Verification
SS
C501-1E
V
CC
Port 0
V
EA/
PP
ALE/PROG
PSEN
P2.7
P2.6
P2.0 - P2.4
MCS03235
10 kΩ
Programming
Data
1
1
0
00Enable
A8 - A12
Semiconductor Group 28 1997-04-01
C501
Absolute Maximum Ratings
Ambient temperature under bias (TA) ......................................................... – 40 to 85 °C
Storage temperature (T
Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V
Input current on any pin during overload condition..................................... – 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on
V
CC
absolute maximum ratings.
) .......................................................................... – 65 °C to 150 °C
stg
V
>
V
CC
or
pins with respect to ground (
IN
V
) must not exceed the values defined by the
SS
V
<
V
SS
) the
IN
Semiconductor Group 29 1997-04-01
DC Characteristics for C501-L / C501-1R
V
= 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 ˚C to 70 ˚C for the SAB-C501
CC
T
= – 40 ˚C to 85 ˚C for the SAF-C501
A
Parameter Symbol Limit Values Unit Test Condition
min. max.
C501
Input low voltage (except EA,
RESET)
Input low voltage (EA
) V
Input low voltage (RESET)
Input high voltage (except
XTAL1, EA
, RESET)
Input high voltage to XTAL1
Input high voltage to EA
,
RESET
Output low voltage
(ports 1, 2, 3)
Output low voltage
(port 0, ALE, PSEN)
Output high voltage
(ports 1, 2, 3)
Output high voltage
(port 0 in external bus mode,
ALE, PSEN
)
V
IL
IL 1
V
IL 2
V
IH
V
IH 1
V
IH 2
V
OL
V
OL 1
V
OH
V
OH 1
– 0.5 0.2 VCC – 0.1 V –
– 0.5 0.2 VCC – 0.3 V –
– 0.5 0.2 VCC + 0.1 V –
0.2 VCC + 0.9 VCC + 0.5 V –
0.7 V
0.6 V
CC
CC
V
+ 0.5 V
CC
V
+ 0.5 V –
CC
– 0.45 V IOL = 1.6 mA
– 0.45 V IOL = 3.2 mA
2.4
0.9 V
2.4
0.9 V
CC
CC
–
–
–
–
V IOH = – 80 µA,
I
= – 10 µA
OH
V IOH = – 800 µA
I
= – 80 µA
OH
1)
1)
2)
,
2)
Logic 0 input current
I
(ports 1, 2, 3)
Logical 1-to-0 transition
I
current (ports 1, 2, 3)
Input leakage current
(port 0, EA
)
I
Pin capacitance C
Power supply current:
7)
Active mode, 12 MHz
Idle mode, 12 MHz
7)
Active mode, 24 MHz
Idle mode, 24 MHz
7)
Active mode, 40 MHz
Idle mode, 40 MHz
7)
Power Down Mode
I
I
7)
I
I
7)
I
I
I
Notes see page 32.
IL
TL
LI
CC
CC
CC
CC
CC
CC
PD
– 10 – 50 µA VIN = 0.45 V
– 65 – 650 µA VIN = 2 V
– ± 1 µA 0.45 < VIN < V
IO
–10pFf
–
–
–
–
–
–
–
21
4.8
36.2
8.2
56.5
12.7
50
mA
mA
mA
mA
mA
mA
µA
= 1 MHz,
C
T
= 25 ˚C
A
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 2 … 5.5 V
CC
CC
4)
5)
4)
5)
4)
5)
3)
Semiconductor Group 30 1997-04-01
DC Characteristics for C501-1E
V
= 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 ˚C to 70 ˚C for the SAB-C501
CC
T
= – 40 ˚C to 85 ˚C for the SAF-C501
A
Parameter Symbol Limit Values Unit Test Condition
min. max.
C501
Input low voltage (except
EA/VPP, RESET)
Input low voltage (EA
/VPP) V
Input low voltage (RESET)
Input high voltage (except
XTAL1, EA
/VPP, RESET)
Input high voltage to XTAL1
Input high voltage to EA
/VPP,
RESET
Output low voltage
(ports 1, 2, 3)
Output low voltage
(port 0, ALE/PROG, PSEN)
Output high voltage
(ports 1, 2, 3)
Output high voltage
(port 0 in external bus mode,
ALE/PROG
, PSEN)
V
IL
IL 1
V
IL 2
V
IH
V
IH 1
V
IH 2
V
OL
V
OL 1
V
OH
V
OH 1
– 0.5 0.2 VCC – 0.1 V –
– 0.5 0.1 VCC – 0.1 V –
– 0.5 0.2 VCC + 0.1 V –
0.2 VCC + 0.9 VCC + 0.5 V –
0.7 V
0.6 V
CC
CC
V
+ 0.5 V
CC
V
+ 0.5 V –
CC
– 0.45 V IOL = 1.6 mA
– 0.45 V IOL = 3.2 mA
2.4
0.9 V
2.4
0.9 V
CC
CC
–
–
–
–
V IOH = – 80 µA,
I
= – 10 µA
OH
V IOH = – 800 µA
I
= – 80 µA
OH
1)
1)
2)
,
2)
Logic 0 input current
I
(ports 1, 2, 3)
Logical 1-to-0 transition
I
current (ports 1, 2, 3)
Input leakage current
(port 0, EA
/VPP)
I
Pin capacitance C
Power supply current:
7)
Active mode, 12 MHz
Idle mode, 12 MHz
7)
Active mode, 24 MHz
Idle mode, 24 MHz
7)
Power Down Mode
I
I
7)
I
I
I
Notes see next page.
IL
TL
LI
CC
CC
CC
CC
PD
– 10 – 50 µA VIN = 0.45 V
– 65 – 650 µA VIN = 2 V
– ± 1 µA 0.45 < VIN < V
IO
–10pFf
–
–
–
–
–
21
18
36.2
20
50
mA
mA
mA
mA
µA
= 1 MHz,
C
T
= 25 ˚C
A
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 5 V,
CC
V
= 2 … 5.5 V
CC
CC
4)
5)
4)
5)
3)
Semiconductor Group 31 1997-04-01
Notes:
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the
V
0.9
3)
I
PD
EA
4)
I
CC
XTAL1 driven with
EA
used (appr. 1 mA).
5)
I
CC
XTAL1 driven with
RESET = EA
specification when the address lines are stabilizing.
CC
(Power Down Mode) is measured under following conditions:
= Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.
(active mode) is measured with:
t
, t
CLCH
= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
CHCL
= Port0 = RESET= VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is
(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
t
, t
CLCH
= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
CHCL
= VSS; Port0 = VCC; all other pins are disconnected;
C501
7)
I
CC max
active mode:
idle mode:
where
at other frequencies is given by:
I
= 1.27 x f
CC
I
= 0.28 x f
f
OSC
CC
is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
+ 5.73
OSC
+ 1.45 (C501-L and C501-1R only)
OSC
Semiconductor Group 32 1997-04-01
C501
AC Characteristics for C501-L / C501-1R / C501-1E
V
= 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501
CC
T
= – 40 ˚C to 85 ˚C for the SAF-C501
A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter Symbol Limit Values Unit
ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
PSEN
PSEN
pulse width t
to valid instr in t
Input instruction hold after PSEN
Input instruction float after PSEN
t
Address valid after PSEN
Address to valid instr in
Address float to PSEN
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
PXIZ
t
PXAV
t
AVIV
t
AZPL
12 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 12 MHz
CLCL
min. max. min. max.
127 – 2t
43 – t
30 – t
– 233 – 4t
58 – t
215 – 3t
– 150 – 3t
– 40 – ns
CLCL
– 40 – ns
CLCL
– 53 – ns
CLCL
– 100 ns
CLCL
– 25 – ns
CLCL
– 35 – ns
CLCL
– 100 ns
CLCL
0–0–ns
*)
–63– t
*)
75 – t
– 8 – ns
CLCL
– 302 – 5t
– 20 ns
CLCL
– 115 ns
CLCL
0–0–ns
*) Interfacing the C501 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group 33 1997-04-01
C501
AC Characteristics for C501-L / C501-1R / C501-1E (cont’d)
External Data Memory Characteristics
Parameter Symbol Limit Values Unit
RD
pulse width t
WR
pulse width t
Address hold after ALE
RD
to valid data in t
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR
Address valid to WR
WR
or RD high to ALE high t
Data valid to WR
or RD t
or RD t
transition t
Data setup before WR
Data hold after WR
Address float after RD
RLRH
WLWH
t
LLAX2
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
LLWL
AVWL
WHLH
QVWX
t
QVWH
t
WHQX
t
RLAZ
12 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 12 MHz
CLCL
min. max. min. max.
400 – 6t
400 – 6t
30 – t
– 252 – 5t
– 100 – ns
CLCL
– 100 – ns
CLCL
– 53 – ns
CLCL
– 165 ns
CLCL
0–0–ns
–97– 2t
– 517 – 8t
– 585 – 9t
200 300 3t
203 – 4t
43 123 t
33 – t
433 – 7t
33 – t
– 50 3t
CLCL
– 130 – ns
CLCL
– 40 t
CLCL
– 50 – ns
CLCL
– 150 – ns
CLCL
– 50 – ns
CLCL
– 70 ns
CLCL
– 150 ns
CLCL
– 165 ns
CLCL
+ 50 ns
CLCL
+ 40 ns
CLCL
–0–0ns
External Clock Drive Characteristics
Parameter Symbol Limit Values Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min. max.
Oscillator period
High time
Low time
Rise time
Fall time
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
83.3 285.7 ns
20 t
20 t
CLCL
CLCL
– t
– t
CLCX
CHCX
ns
ns
–20ns
–20ns
Semiconductor Group 34 1997-04-01
C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24
V
= 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501
CC
T
= – 40 ˚C to 85 ˚C for the SAF-C501
A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter Symbol Limit Values Unit
ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
PSEN
PSEN
pulse width t
to valid instr in t
Input instruction hold after PSEN
Input instruction float after PSEN
t
Address valid after PSEN
Address to valid instr in
Address float to PSEN
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
PXIZ
t
PXAV
t
AVIV
t
AZPL
24 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 24 MHz
CLCL
min. max. min. max.
43 – 2t
17 – t
17 – t
–80– 4t
22 – t
95 – 3t
–60– 3t
– 40 – ns
CLCL
– 25 – ns
CLCL
– 25 – ns
CLCL
– 87 ns
CLCL
– 20 – ns
CLCL
– 30 – ns
CLCL
– 65 ns
CLCL
0–0–ns
*)
–32– t
*)
37 – t
– 5 – ns
CLCL
– 148 – 5t
– 10 ns
CLCL
– 60 ns
CLCL
0–0–ns
*) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group 35 1997-04-01
C501
AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d)
External Data Memory Characteristics
Parameter Symbol Limit Values Unit
RD
pulse width t
WR
pulse width t
Address hold after ALE
RD
to valid data in t
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR
Address valid to WR
WR
or RD high to ALE high t
Data valid to WR
or RD t
or RD t
transition t
Data setup before WR
Data hold after WR
Address float after RD
RLRH
WLWH
t
LLAX2
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
LLWL
AVWL
WHLH
QVWX
t
QVWH
t
WHQX
t
RLAZ
24 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 24 MHz
CLCL
min. max. min. max.
180 – 6t
180 – 6t
15 – t
– 118 – 5t
– 70 – ns
CLCL
– 70 – ns
CLCL
– 27 – ns
CLCL
– 90 ns
CLCL
0–0–ns
–63– 2t
– 200 – 8t
– 220 – 9t
75 175 3t
67 – 4t
17 67 t
5–t
170 – 7t
15 – t
– 50 3t
CLCL
– 97 – ns
CLCL
– 25 t
CLCL
– 37 – ns
CLCL
– 122 – ns
CLCL
– 27 – ns
CLCL
– 20 ns
CLCL
– 133 ns
CLCL
– 155 ns
CLCL
+ 50 ns
CLCL
+ 25 ns
CLCL
–0–0ns
External Clock Drive Characteristics
Parameter Symbol Limit Values Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min. max.
Oscillator period
High time
Low time
Rise time
Fall time
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
41.7 285.7 ns
12 t
12 t
CLCL
CLCL
– t
– t
CLCX
CHCX
ns
ns
–12ns
–12ns
Semiconductor Group 36 1997-04-01
C501
AC Characteristics for C501-L40 / C501-1R40
V
= 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501
CC
T
= – 40 ˚C to 85 ˚C for the SAF-C501
A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter Symbol Limit Values Unit
ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
PSEN
PSEN
pulse width t
to valid instr in t
Input instruction hold after PSEN
Input instruction float after PSEN
t
Address valid after PSEN
Address to valid instr in
Address float to PSEN
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
PXIZ
t
PXAV
t
AVIV
AZPL
40 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 40 MHz
CLCL
min. max. min. max.
35 – 2 t
10 – t
10 – t
–55– 4 t
10 – t
60 – 3 t
–25– 3 t
– 15 – ns
CLCL
– 15 – ns
CLCL
– 15 – ns
CLCL
– 45 ns
CLCL
– 15 – ns
CLCL
– 15 – ns
CLCL
– 50 ns
CLCL
0–0 – ns
*)
–20– t
*)
20 – t
– 5 – ns
CLCL
–65– 5 t
– 5 ns
CLCL
– 60 ns
CLCL
– 5 – – 5 – ns
*) Interfacing the C501 to devices with float times up to 25ns is permissible. This limited bus contention will not
cause any damage to port 0 Drivers.
Semiconductor Group 37 1997-04-01
C501
AC Characteristics for C501-L40 / C501-1R40 (cont’d)
External Data Memory Characteristics
Parameter Symbol Limit Values Unit
RD
pulse width t
WR
pulse width t
Address hold after ALE
RD
to valid data in t
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR
Address valid to WR
WR
or RD high to ALE high t
Data valid to WR
or RD t
or RD t
transition t
Data setup before WR
Data hold after WR
Address float after RD
RLRH
WLWH
t
LLAX2
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
LLWL
AVWL
WHLH
QVWX
t
QVWH
t
WHQX
t
RLAZ
40 MHz
Clock
1/
Variable Clock
t
= 3.5 MHz to 40 MHz
CLCL
min. max. min. max.
120 – 6 t
120 – 6 t
10 – t
–75– 5 t
– 30 – ns
CLCL
– 30 – ns
CLCL
– 15 – ns
CLCL
– 50 ns
CLCL
0–0–ns
–38– 2 t
– 150 – 8 t
– 150 – 9 t
60 90 3 t
70 – 4 t
10 40 t
5–t
125 – 7 t
5–t
– 15 3 t
CLCL
– 30 – ns
CLCL
– 15 t
CLCL
– 20 – ns
CLCL
– 50 – ns
CLCL
– 20 – ns
CLCL
– 12 ns
CLCL
– 50 ns
CLCL
– 75 ns
CLCL
+ 15 ns
CLCL
+ 15 ns
CLCL
–0–0ns
External Clock Drive Characteristics
Parameter Symbol Limit Values Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min. max.
Oscillator period
High time
Low time
Rise time
Fall time
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
25 285.7 ns
10 t
10 t
CLCL
CLCL
– t
– t
CLCX
CHCX
ns
ns
–10ns
–10ns
Semiconductor Group 38 1997-04-01
ALE
t
C501
LHLL
PSEN
Port 0
Port 2
t
AVLL PLPH
t
LLIV
t
t
PLIV
t
AZPL
t
LLAX
t
LLPL
t
t
PXAV
t
PXIZ
PXIX
A0 - A7 Instr.IN A0 - A7
t
AVIV
A8 - A15 A8 - A15
MCT00096
Figure 13
Program Memory Read Cycle
Semiconductor Group 39 1997-04-01
ALE
PSEN
RD
t
LLWL
t
LLDV
t
RLDV
t
RLRH
t
WHLH
C501
t
AVLL
Port 0
A0 - A7 from
Ri or DPL from PCL
Port 2
Figure 14
Data Memory Read Cycle
t
AVWL
t
LLAX2
t
AVDV
t
RLAZ
Data IN
t
RHDZ
t
RHDX
A0 - A7 Instr.
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
IN
MCT00097
Semiconductor Group 40 1997-04-01
ALE
PSEN
t
WHLH
C501
t
LLWL
WR
t
Port 0
AVLL
A0 - A7 from
t
LLAX2
Ri or DPL from PCL
t
AVWL
Port 2
Figure 15
Data Memory Write Cycle
t
QVWX
t
WLWH
t
QVWH
Data OUT
t
WHQX
A0 - A7
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
Instr.IN
MCT00098
t
CLCL
V
- 0.5V
CC
0.45V
0.2
0.7
V
CC
V
CC
- 0.1
t
CHCL
t
CLCX
t
CLCH
t
CHCX
MCT00033
Figure 16
External Clock Drive at XTAL2
Semiconductor Group 41 1997-04-01
C501
ROM Verification Characteristics for C501-1R
ROM Verification Mode 1
Parameter Symbol Limit Values Unit
min. max.
Address to valid data t
ENABLE to valid data
Data float after ENABLE
t
t
Oscillator frequency 1/
P1.0 - P1.7
P2.0 - P2.4
Port 0
P2.7
ENABLE
AVQV
ELQV
EHQZ
t
CLCL
t
ELQV
–48t
–48t
048t
CLCL
CLCL
CLCL
ns
ns
ns
4 6 MHz
Address
t
AVQV
Data OUT
t
EHQZ
MCT00049
Address: P1.0 - P1.7 = A0 - A7
P2.0 - P2.4 = A8 - A12
Data:
Inputs: P2.5 - P2.6, PSEN =
ALE, EA =
RESET =P0.0 - P0.7 = D0 - D7
V
SS
V
IH
V
SS
Figure 17
ROM Verification Mode 1
Semiconductor Group 42 1997-04-01
OTP Programming and Verification Characteristics
V
= 5 V ± 10%, VSS = 0 V, TA = 21 ˚C to + 27 ˚C
CC
Parameter Symbol Limit Values Unit
min. max.
C501
Programming supply voltage V
Programming supply current I
PP
Oscillator frequency 1 /
Address setup to ALE/PROG
Address hold after ALE/PROG
Data setup to ALE/PROG
Data hold after ALE/PROG
P2.7 (ENABLE
V
setup to ALE/PROG low t
PP
hold after ALE/PROG low t
V
PP
ALE/PROG
) high to V
width t
Address to data valid
ENABLE
low to data valid t
Data float after ENABLE
ALE/PROG
high to ALE/PROG low t
low t
low t
PP
AVGL
t
GHAX
DVGL
t
GHDX
t
EHSH
SHGL
GHSL
GLGH
t
AVQV
ELQV
t
EHQZ
GHGL
PP
t
CLCL
12.5 13.0 V
–50mA
4 6 MHz
48 t
48 t
48 t
48 t
48 t
CLCL
CLCL
CLCL
CLCL
CLCL
–ns
–ns
–ns
–ns
–ns
10 – µs
10 – µs
90 110 µs
– 48 t
– 48 t
0 48 t
CLCL
CLCL
CLCL
ns
ns
ns
10 – µs
Semiconductor Group 43 1997-04-01
C501
P1.0 - P1.7
P2.0 - P2.4
Port 0
ALE/PROG
V
EA/
PP
P2.7
ENABLE
t
AVGL
t
EHSH
t
DVGL
t
GLGH
t
SHGL
Programming
Address
t
AVQV
Data Data
t
GHDX
t
GHAX
t
GHGL
t
GHSL
Logic 0
t
ELQV
Verification
Address
Logic 1
t
EHQZ
MCT03237
Figure 18
C501-1E OTP Memory Program/Read Cycle
Semiconductor Group 44 1997-04-01
C501
g
V
-0.5 V
CC
0.45 V
AC Inputs during testing are driven at VCC – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing
measurements are made at V
for a logic ‘1’ and V
IHmin
Figure 19
AC Testing: Input, Output Waveforms
V
+0.90.2
CC
V
0.2 -0.1
CC
Test Points
for a logic ‘0’.
ILmax
MCT00039
-0.1 V
V
OH
V
+0.1 V
OL
MCT00038
V
Load
V
V
Load
Load
+0.1 V
Timing Reference
Points
-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH / VOL level occurs.
I
/ IOH ≥ ± 20 mA.
OL
Figure 20
AC Testing: Float Waveforms
Crystal Oscillator Mode Driving from External Source
C
N.C.
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
3.5 - 40 MHz
XTAL2 XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
External Oscillator
Signal
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
MCS02452
20 pF
C
= pF10
C
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
(incl. stray capacitance)
Note: During programming and verification of the C501-1E OTP memory
a clock si
nal of 4-6 MHz must be applied to the device.
Figure 21
Recommended Oscillator Circuits
Semiconductor Group 45 1997-04-01
Package Outlines
Plastic Package, P-DIP-40 for C501G-L / C501G-1R
(Plastic Dual in-Line Package)
C501
Figure 22
P-DIP-40 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
Semiconductor Group 46 1997-04-01
GPD05883
Plastic Package, P-LCC-44 – SMD for C501G-L / C501G-1R / C501G-1E
(Plastic Leaded Chip-Carrier)
C501
Figure 23
P-LCC-44 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group 47 1997-04-01
GPL05882
Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-1R
(Plastic Metric Quad Flat Package)
C501
Figure 24
P-MQFP-44 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
GPM05957
Dimensions in mm
Semiconductor Group 48 1997-04-01
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