Sharp ZQ-5000, ZQ-5200 Service Manual
SHARP
SERVICE MANUAL
CODE:OOZZQ5200SM/E
ZQ-5000
MODEL
z&5200
STANDARD FUNCTION
10 digits
1M
D
ELEMENT: FEM LCD
!:
NUMERAL:
1
PARTS NAME:
F7615G
16
dinits (8 lines)
96 x 64 dot matrix liquid crystal
display 16 columns x 8 lines
s:
d
IE!!P
(with 5 x 7 dot characters)
c
12 columns 4 lines
0.45 0.04 (with 8 x 16 dot characters)
(mm)
KEY SYSTEM: Rubber key
CPU: SC6201 5B02
Electronic notebook
Display:
LH5073A
and LH5074F
section
Tebphanediiory
mode
SdwdUb rm.%
1
i
Mask ROM:
UPD23C2001
GW302
Regulator:
SC1771
1 YDA
SRAM: M5256FP15L
Low battery ditecter: MN1 280P
RTC:
SEK6115B
POWERSUPPLY 1 AC: X
1
DC: 0
Main power supply:
6 Vdc lithium batteries (CR2032 x 2)
Memory backup power:
3 Vdc lithium battery (CR2032 x 1)
AC ADAPTOR
RECHARGEABLE
BATTERY
POWER
CONSUMPTION
0.08
W
AUTO POWER
OFF TIME
Approx. 6 minutes
Secret fundJon. user
diibnaw,
data tmnste,
MEMORY
PROTECT
Yes
DIMENSIONS(mm)
Open: 145(W) x 160(D) x 8.9(H) mm.
Clock
Closed: 145(W) x
80(D)
x 17.8(H) mm.
I
Weight
Approx.
1759
(including batteries)
CALCULATIONS
1
addition, subtraction, multiplication, division;
constant, square root, percent, memory
calculation, estimation
Accessories
Lithium batteries (CR2032 x 3)
Operation manual
Operating time
SHARP CORPORATION
l%is document has been published to be used for after
service only.
The contents are subject to change without notice.
ZQ-5000
ZQ-5200
1.
CPU (SC6201
5802)
terminal descriptions
Terminal No. Signal name
Input/Output
Descriptions
1
Xl
output
Ceramic oscillation output
2
x2
Input
Ceramic oscillation
output
3
x3
output
4
x4
Input
5
VDD
output
6
vcc Power
CR oscillation output
CR oscillation input
Display power
Power
(+)
7
1
RESET
/
Input
1
Reset input terminal. Reset at
L
8
GND
Power
j
Power (-)
9
TEST
Input
10
Cl
Input
/
Test input
11
I
co
I
Outout
1
Buzzer drive outout fKev click sound)
I
12
I
ON
t
Input
/
ON KEY input terminal
I
13
I
WR
/
Outout1 Write clock
I
14
I
MRO 1 -
1 Nat used
I
15
I
KIO
1
lnout
1
KEY inout terminal
I
I
I
2 I 2 I1
I
22
I
K17 /
lnout
1
KEY inout terminal
I
23
DIO 0
Input/Output
Data
bus
1 ? ?
I
30
DIO 7
Input/Output
Data
bus
31
A0 OutDut
Address bus
1
2 2
L
49
Al8
Outout
1
Address bus
50
VDISP
-
Not used.
51
VA
-
Not used.
52
@D
-
Not used.
53
K015
output 15 pin ER signal (Data terminal ready)
54
K014
output
1.5
pin RR signal (Receive enable)
55
K013 output
ON KEY strobe signal
56
K012
output KEY strobe signal
57
K011
output KEY strobe signal
58
KOlO
output
KEY strobe signal
59
IRQ
Input
Interrupt input terminal (Active low)
60
@OUT
-
Not used.
61
CE7
output
LCD driver slave side chip enable signal.
62
CE6
output
LCD driver master side chip enable signal.
63
CE5
-
Not used.
64
CE4
output
Internal ROM chip enable signal COOOOH-FFFFFH
65
CE3
-
Not used.
66
CE2
-
Not used.
67
CEl
output
Internal RAM chip enable signal 1
OOOOH-1
FFFFH
68
CEO
-
Not used.
69
OA
output
Address latch signal
70
DIS
output
LCD driver control signal
71
HA
-
Not used.
72
RD
-
Not used.
73
K09
output
KEY strobe signal
1 1
t
1
82
KOO
output
KEY strobe signal
83
R/D
Input
15pin RD
signal (receive data)
84
T/D
output
1
Spin
SD signal (receive data)
85
El5
Input/Output
4pin SO signal (send data)
86
El4
Input/Output
4pin SI signal (receive data)
87 El3
output
15pin RS
signal (Send request)
86
El2
Input
15pin
CS signal (Send enable)
-l-
ZQ-5000
ZQ-5200
Terminal No. Signal name
Input/Output
Descriptions
89
El1
Input
15pin
DR signal (Data set ready)
90
El0
Input
15pin
CD signal (carrier detection)
output
Low battery control signal
92 E8
output
93 E7
Input/Output
Multi-language select signal
(ZQ-500015200:
Open;
ZQ-51 OOM/5300M:
Short between 93 pin and 95 pin)
94
E6
-
Not used.
95
E5
output
96
E4
Inout
Multi-language select signal
(ZQ-5000/5200: Open, ZQ-5100M/5300M: Short between 93 pin and 95 pin)
RTC serial clock sianal
97
E3
Input
98 E2
OUtRUt
RTC serial IN signal
RTC timer reset siqnal
99 El output
/
RTC serial OUT signal
100
EO
1
Output 1 RTC control signal
2. LCD drivers
LH5073A
and
LH5074F
LCD drivers LH5073A and
LH5074F,
as display common drivers,
respectively include 32 drive circuits. The display duty is
1132.
As
display segment drivers, they include 98 drive circuits and store 8bit
parallel display data sent from a microcomputer into their internal
display RAM to generate liquid crystal drive signal. One bit data of the
disply RAM corresponds to one dot ON/OFF of the liquid crystal
panel.
(1)
Features
@I
Common driver section
0
Common output impedance:
5.OK
ohm (Max.)
0
Built-in common liquid crystal display drive circuit: 32circuits
@
Segment driver section
0
Segment output impedance: 25K ohm (max.)
0
Direct display of RAM data by built-in display RAM: Data
“H”:
ON, Data
I”:
OFF
0
Display RAM capacity: 392byte
(3,136bit)
0
Arithmetic RAM capacity:
12Obyte
(960bit)
0
Bbit
parallel interface (Data bus, address bus)
0
Built-in segment liquid crystal display drive circuit:
98circuits
Display duty:
l/32
0
Instruction function
Display data read/write, display ON/OFF, address set
@
C-MOS process
@
Power source
GND=OV, VCC=4 - 6V
VFF= lo-
14V
@
PKG
163 pin film
@
Difference between LH5073A and LH5074F
LH5073 is equipped with an internal oscillation circuit and aninter-
nal
booster circuit.
LH5074 has no internal oscillation circuit (Synchronization signal
is inputted from
LH5073A),
and no booster circuit (Voltageis
sup-
plid
from
LH5073A).
* The control signal array of LH5073A is contrary to that of
LH5074F.
-2-
ZQ-5000
ZQ-5200
(2)
Terminal arrangement
LHXl74A
(163pin
film)
HHHH
-H
s
-
S
16 15 14
13
1
96
1
LH5074F
(163pin
film)
S S H
H S
S
97 98 32
-
17
1
-
96
H-
H H H H
1
13 14 15 16
q
+
Signal
name
(Note) NC : Not used terminal
-3-
ZQ-5000
ZQ-5200
(3)
Terminal
name
(LH5073A),
(LH5074F)
ZQ-5000
7-Q-5200
132
578
Segment output
159
133
s79 Segment output
160
134
sao
Segment output
161
135
Sal
Segment output
162
136
sa2
Segment output
163
137
sa3
Segment output
(Note *) Mark
‘*”
means LH5073A signal name, and LH5074F terminal is not used.
4onnectiorb
H9
Common output
HlO
Common output
HI1
Common output
H12
Common output
H13
Common output
LH5073A rear(terminal
side)
LCD driver (Master) M
Ci,C2=0.22~F:Booster
capacitor
C3,C4,C5,:Liquid
crystal power smoothing capacitor
-5-
(4)
(LH5073)
Block
Diagram
VEE
VCC
GND
CF
RIW
*AL
0’
-
+
---
VOOVDD DIS HA
,&&,
fj”sy
CRT
803802 801
UN) PJT)
IN OUT IN OUT
(LH5074) Block
Diagram
ZQ-5000
ZQ-5200
Supplied from
LH5073Al
VFF
VDP
VA
VM
\
VB
Vl
v2
HI
H32
Sl
_________....__._.....___._.___.__
VEE
Segment driver
VCC
6- r-i n
I
” ”
XGCRT
803 802
BOI
IN OUT IN OUl
(5)
Operational description
LH5073F is an LCD driver for LH5073A display expansion, and is
used in pairs with
LH5073A.
The display section power VFF, liquid
crystal drive power
VDP,VA,
VM, and synchronization signal HA of
VM and display divider are supplied from the output terminals of the
same names of
LH5073A.
Display data are in 8 bit unit, and asynchronous read/write from/to the
built-in display RAM is enabled. One bit data of the display RAM
corresponds to one dot on/off of the liquid crystal panel. Display
output is provided in
l/32
duty by
g&segment
dirver.
Display control signal VDD input and
DIS
input should be the same
as those of
LH5073A.
Every time when
DIS
input is turned from L to
H,
the internal display divider is reset.The operation modes and
timing chart of the display circuit are shown below:
Control input
Input signal from LH5073
VDD
DIS
HA
VFF, VDP, VA, VM, VB
Operation mode
H
l
Stop (H or L) Stop (GND level) Standby
L
H
Operation Operation
Display mode
L
L
Operation Operation
Display OFF (Segment OFF waveform)
The internal ROM operation mode is shown below:
1 ~o,r-rt;~~;~~
1
Data;;U/;tput 1
Operation mode
I
H H H
HZ
Standbylpre-charge
H H L
Address input Address write
L L H
Data input Data write
L H H
Data output Data read
(NOTE) When reading/writing data, turn E input to
“H”
to bring
about pre-charge state for every cycle.
-6-
DIS
input
LHsO73
HA
HA output - input
(Display
divider reset
LSI internal signal)
HA32 cycles
HA32 cycles
1OV VAH
-
6.5.V VMH
-
7.OV VBH
~
3.OV VAL
-
1.5V
VML
-
1OV
VAH
l-l
, _ _. . . . . . . ,
(Note)
Valuessf
VA, VM, and
V!3
are TYP values when VDP is set to
1OV.
3. RTC
(SEKGI 15B)
(1) RTC
(SEK6115B) terminal arrangement
K2)i 0
16(Kl
I/O
1
)2
15(VSl
l/O 2)3
14(VS2
I/03)4
13(VST
ALARM
)5
lP(VDD
SR )6
11
(c2
osc2
)7
lO(C1
OSCl )a
9
(vs3
r
-7-
ZQ-5000
ZQ-5200
(2) RTC
(SEK6115B) Terminal
signal
description
Terminal No.
Signal name
InpuffOlJtput
12 VDD
-
[Power terminal] (OV)
15
VSI
-
[Power terminal, Booster/voltage falling power terminal
VSl
(-1
.S/), VS2
(-3.0V)]
14
vs2
-
Across VDD -
VS2:
-3V power, Across
VDD -
VS3: Failing capacitor
9
vs3
-
[Booster power terminal
(4.5V)]
Capacitor is inserted between
VDD
and
VS3.
13
VST
[Constant voltage output terminal] Output terminal of IC internal power.
Capacitor is inserted between
VDD
and VST for stabilization of constant voltage output.
10
Cl
-
11
c2
[Booster capacitor connection terminal] Capacitor is inserted between Cl and C2.
6
SR
8
OSCl
7
osc2
16
Ki
1
K2
2
l/O1
4
1103
5
ALARM
Input
Input
output
Input
output
output
[System reset input] After oscillation frequency is stabilized,
the system can be reset by high level input (6.25 msec or above).
[Oscillation terminal] Oscillation input/output terminal
[Data input terminal] Normally pulled down to LOW.
[Data output terminal] Output amplitude is between
VDD
and
VS2.
[Alarm output] Alarm buzzer drive output terminal
Output frequency is 4,096KHz, output amplitude is between
VDD
and VS2.
4. Regulator
(SC1771
1 Y DA)
5. Low battery detection circuits
This is used to produce power for RTC (SMC6115F). (6V + 3V)
1
VIN
2
GND
I
3
VOUT
(1)
Outline
The ZQ-5000/5200 is equipped with the following two circuits for low
battery detection:
@
Main battery voltage detection circuit
Q
Memory protection battery voltage detection circuit
The main battery voltage detection circuit @ detects the battery voltage during operation of the unit. When the voltage falls to the caution
level (about 4.4 to 4.8V), the LCD battery lamp lights up. When the
voltage falls to the fatal level (about 3.9 to 4.2V), the power is compul-
sority turned off. This operation is common with the OZ/IQ-7000.
All detection circuit
a>, Q
detect the battery voltage when the power
is turned on, and provide the message of low battery if required.
The detection procedures in that case are as follows:
@
The fatal level of the battery for operating the unit is checked. (If
The
SC1771
1YDA is a voltage regulator developed with C-MOS
SI
gate process, and is composed of a high accuracy and low power
consumption reference voltage supplier, a differential amplifier control
transistor, and a voltage setting resistor. The output votage is inter-
nally fixed. It is a negative output voltage regulator.
The package is mini power mold plastic package.
VIN (
r2
VREF
,GND
RL
the battery level is below the fatal level, the power cannot be
turned on.)
Q
The level of the unit memory protection battery is checked. In case
of low battery, the display will be as Fig.
1.
Q
The unit memory header is checked.
@
The caution level of the unit operation battery is checked. In case
of low battery, the display will be as Fig. 2.
Fig. 1
Fig. 2
ia-
d.
1
Display remains for about 5
set,
Display remains for about 2
set,
and the power is turned off. and the normal operation mode
is restored. (The battery lamp
lights up.)
ZQ-5000
ZQ-5200
(2)
Circuit description
a. Main
battery
voltage detection
When input voltage
VIN
exceeds the detection voltage VD, the output
of the voltage detection IC
[LBIC (MN1280)]
is driven from Low to
High. When
VIN
falls under VD, the output is driven from High to Low.
The
LBIC (MN1
280)
detects
both the CAU level and the STOP level
by dividing the voltage applied to the input terminal (2 pin) with Rl
and R2 and by turning on/off R2 with CAU signal of
G-A.
When the power voltage falls under the CAU level, as shown in Fig.
3, the
BAl7
symbol lights up. When the power voltage falls further
under the STOP level, the symbol goes off.
For CAU level detection, the CPU E9 terminal it turned on (low level)
and the CPU
IRQ
terminal state is observed. (If the
IRQ
is at Low
level, the symbol lights up.)
When the CAU level is detected, the CPU E9 terminal is turned off
(high impedance). (When the CPU E9 terminal is turned off, resistor
division is not performed and the voltage at
LBIC
2 pin increases,
driving the output from Low to High.) The CPU
IRQ
terminal state is
checked again to detect the STOP level.
After the STOP level is detected, the ON key and the RESET key
become ineffective.
4
CPU E9
(N-ch
open)
b.
Memory protection
battery
“CC
1
After
Smsec
of
E8’s
becoming high,
DIS
becomes low. After I oopsec,
the back-up battery low voltage is detected. When
LBIC
is high, it is
normal. When
LBIC
is
low, KIO
becomes high to turn off the display
of <ATTENTION> after 5 sec.
6. Memory map
CEI
loooot
1 aooot
2oooot
CE2
3oooot
CE5
4oooot
CEO
‘30000t
CE3
coooot
CE4
EOOOOI
00000t
04ooot
FFFFFI
DRIVER
32KS
SOP IC
-Internal
RAM
.-.
32K8 COB
EX RAM1
54KE
EX RAM2
64 KS
EX CED
256 KS
PM)
EX CED
25s KB
(34
SYSTEM ROM
1
MB
(Internal)
04000H
qxi+$
07FFFH
E8
Backup
-9-
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