Sharp LH540245U-35, LH540245U-25, LH540245U-20, LH540245M-35, LH540245M-20 Datasheet
...
LH540235/45
FEATURES
•
Fast Cycle Times: 20/25/35 ns
•
Pin-Compatible Drop-In Replacements for
IDT72235B/45B FIFOs
•
Choice of IDT-Compatible or
Mode; Selected by an Input Control Signal
•
Device Comes Up into One of Two Known Default
States at Reset Depending on the State of the
EMODE
Control Input: Programming is Allowed, but
is not Required
•
Internal Memory Array Architecture Based on CMOS
Dual-Port SRAM Technology, 2048 × 18 or 4096 × 18
•
‘Synchronous’ Enable-Plus-Clock Control at Both
Input Port and Output Port
•
Independently-Synchronized Operation of Input Port
and Output Port
•
Control Inputs Sampled on Rising Clock Edge
•
Most Control Signals Assertive-LOW for
Noise Immunity
Enhanced
Operating
2048 × 18 / 4096 × 18 Synchronous FIFOs
•
May be Cascaded for Increased Depth, or
Paralleled for Increased Width
•
16 mA-IOL High-Drive Three-State Outputs
•
Five Status Flags: Full, Almo st- Full, Half- Full,
Almost-Empty, and Empty; ‘Almost ’ Flags are
Programmable
•
In Enhanced Operating Mode, Almost-Full,
Half-Full, and Almost-Empty Flags can b e Made
Completely Synchronous
•
In Enhanced Operating Mode, Duplicate Enables
for Interlocked Paralleled FIFO Operation, for
36-Bit Data Width, when Selected and
Appropriately Connected
•
In Enhanced Operating Mode, Disabling
Three-State Outputs May be Made to Suppress
Reading
•
Data Retransmit Function
•
TTL/CMOS-Compatible I/O
•
Space-Saving 68-Pin PLCC Package; Even-Smaller
64-Pin TQFP Package
RS
FL/
RT
WXI/
WEN
2
WXO/HF
RXI/
REN
2
RXO/
EF
2
WCK
WEN
WXI/
WEN
2
FF
PAF
WXO/HF
D0 - D
17
LD
BOLD ITALIC = Enhanced Operating Mode.
RESET
LOGIC
EXPANSION
LOGIC
INPUT
PORT
CONTROL
LOGIC
INPUT
PORT
EMODE
FIFO
MEMORY ARRAY
2048 x 18/4096 x 18
WRITE
POINTER
DEDICATED AND
PROGRAMMABLE
STATUS FLAGS
PROGRAMMABLE
REGISTERS
READ
POINTER
OUTPUT
PORT
CONTROL
LOGIC
OUTPUT
PORT
RCK
REN
RXI/
EF
PAE
RXO
OE
Q
0
- Q
REN
/EF
17
2
2
540235-1
BOLD ITALIC = Enhanced Operating Mode
Figure 1. LH540235/45 Block Diagram
1
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
FUNCTIONAL DESCRIPTION
NOTE: Throughout this data sheet, a
font is used for all references to
features which do not function in IDT-Compatible
Mode
Operating Mode; and also for all references to the
transmit
feature), even though it may be used – s ubject to some
restrictions – in either of these two operating modes.
Thus, readers interested only in using the LH540235/45
FIFOs in IDT-Compatible Operating Mode may skip over
BOLD ITALIC
memory devices, based on fully-static CMOS dual-port
SRAM technology , capable of co ntaining up to 2048 or 4096
18-bit words respectively. They can replace two or more
byte-wide FIFOs in many a pplication s, for micropro cessorto-microprocessor or microprocessor-to-bus communication. Their archite cture supports synchronous operatio n, tied
to two independent free-running clocks at the input and
output ports respectively. However, these ‘clocks’ also may
be aperiodi c, asynchronous ‘d emand’ sig nals. Almost all
control-input signals and status-output signals are synchronized to these clocks, to simplify system design .
pendently of each other, unless the FIFO becomes either
totally full or else totally empty. Data flow is initiated at a
port by the rising edge of its corresponding clock, and is
gated by the appropriate edge-sampled enable signals.
which the internal memory has been filled: Ful l, AlmostFull, Half-Full, Almost-Empty, and Empty . The Almost-Full
and Almost-Empty flag offsets are programmable over the
entire FIFO depth; but, during a reset operation, each of
these is initialized to a default offset value of 12710
FIFO-memory words, from the respective FIFO boundary .
If this default offset value is satisfac tory, no further programming is required.
input was not asserted (was HIGH), these FIFOs operate
in the IDT-Compatible Operating Mode. In this mode,
each part is pin-compatible and functionally-compatible
with the IDT72235B/45B part of similar depth and speed
grade; and the
or visible to the external-system logic which is controlling
the FIFO, although it still performs the same control
functions.
facility (which is not an IDT72235B/45B FIFO
sections, if they wish.
The LH540235/45 parts are FIFO (First-In, First-Out)
The input and output ports operate altogether inde-
The following FIFO status flags monitor the extent to
After a reset opera tion during which the
Control Register
BOLD IT ALIC
Enhanced Operating
EMODE
is not even accessible
However, assertion of the EMODE control input
during a reset operation leaves Control Reg ister bits
00-05 set, and causes the FIFO to operate in the
Enhanced Operating Mode. In essence, asserting
EMODE chooses a different default state for the Con-
type
re-
control
trol Register. The system optionally then may program the Control Register in any desired manner to
activate or deactivate any or all of the Enhanced-Operating-Mode features which it can control, in cluding
selectable-clock-edge flag synchronization, and read
inhibition when the data outputs are disabled.
Whenever
EMODE is being asserted, interlockedoperation paralleling also is available, by appropriate
interconnection of the FIFO’ s expansion inp uts.
The retransmit facility is available during standalone
operation, in either IDT-Compatible Operating Mode or
Enhanced Operating Mode (see Tables 1 and 2). It is
inoperative if the
an IDT72235B/45B feature.
FL/RT input signal is grounded. It is not
The Retransmit control
signal causes the internal FIFO read-address pointer
to be set back to zero, without affecting the internal
FIFO write-address pointer. Thus, the Retransmit
control signal also provides a mechanism whereby a
block of data delimited by the zero physical address
and the current write-address-pointer address may
be read out repeatedly, an arbitrary number of times.
The only restrictions are that neither the read-address pointer nor the write-address pointer may
‘wrap around’ during this entire process, and that the
retransmit facility is not available during depth-cascaded operation, either in IDT -Compat ible Operating
Mode or in Enhanced Operating Mode (see Tables 1
and 2). Also, the flags behave differently for a short
time after a retransmit operation. Otherwise, the retransmit facility is available during standalone o peration, in either IDT-Compatible Operating Mode or
Enhanced Operating Mode.
Note that, when
FL/RT is being used as RT, RT is
an assertive-HIGH signal, rather than assertive-LOW
as it is in most other FIFOs having a retransmit
facility.
Programming the programmable-flag offsets,
the timing synchronization of the various status flags, the
optional read-suppression functionality of
OE, and
the behavior of the pointers which access the offsetvalue registers and the Control Register
vidually controlled by asserting the signal
reset operation. When
is being enabled by asserting
input bus word D
WCLK to program one or more of the programmable
registers on successive write clocks. Likewise, the values
programmed into these programmable registers may be
read out for verification by asserting
the outputs Q
grammable registers should not be initiated while they are
being written into. Table 3 defines the possible modes of
operation for loading and reading out the contents of
programmable registers.
– Q17 enabled. Reading out these pro-
0
LD is being asserted, and writing
WEN, some portion of the
– D17 is used at the next rising edge of
0
may be indi-
LD, without any
LD and REN, with
BOLD ITA LIC = Enhanced Operating Mode
2
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
In the Enhanced Operating Mode, coordinat ed operation of two 18-bit FIFOs as one 36-bit FIFO may be
ensured by ‘interlocked’ crosscoupling of the statusflag outputs from each FIFO to the expan sion inp uts
of the other one; that is,
FF to WXI/WEN2, and EF to
RXI/REN2, in both directions between two paralleled
FIFOs. This ‘interlocked’ operation takes effect
17
SS
D15D16D
D
10
14
11
D
13
D
12
12
D
13
11
D
14
10
D
15
9
16
V
CC
17
D
8
V
18
SS
D
19
7
D
20
6
D
21
5
D
22
4
D
23
3
24
D
2
D
25
1
D
26
0
RT
PAE
FL/
WCLK
BOLD ITALIC = Enhanced Operating Mode.
V
WEN
RCLK
2
WEN
WXI/
REN
33 34 35 36 37 38 39 40 41 42 4327 28 29 30 31 32
CC
V
LD
3 2 1 6867666564636261987654
PAF
automatically, if two paralleled FIFOs are crossconnected in this manner , with the
EMODE control input
being asserted (LOW) (see Tables 1 and 2, also Figures 28 and 31). IDT-compatible depth cascading no
longer is available when operating in this ‘interlocked-paralleled’ mode; however, pipelined depth
cascading remains available.
17
OE
2
REN
RXI/
RS
FF
CC
SS
V
V
2
EF
WXO/HF
RXO/
Q
EF
0
Q
SS
V
16
Q
Q2Q
CC
V
1
Q
15
SS
V
Q
60
V
CC
59
Q
14
Q
58
13
57
V
SS
56
Q
12
55
Q
11
54
V
CC
53
Q
10
52
Q
9
51
V
SS
Q
50
8
Q
49
7
EMODE
48
Q
47
6
Q
46
5
V
45
SS
Q
44
4
3
CC
V
TOP VIEW
540235-2
Figure 2. Pin Connections for PLCC Package
BOLD ITALIC = Enhanced Operating Mode
3
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
64-PIN TQFP
TOP VIEW
17
16
D16D
17
SS
V
RCLK
REN
LD
OE
RS
CC
SS
Q
V
V
EF
Q
15
SS
V
CC
Q
V
58 57 56 55 54 53 52 51 50 4964 63 62 61 60 59
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
40
39
38
37
36
35
34
33
41
Q
14
Q
13
V
SS
Q
12
Q
11
V
CC
Q
10
Q
9
V
SS
Q
8
Q
7
Q
6
Q
5
V
SS
Q
4
EMODE
23 24 25 26 27 28 29 30 31 3217 18 19 20 21 22
RT
PAE
FL/
NOTE:
BOLD ITALIC
= Enhanced operating mode.
Figure 3. Pin Connections for Thin Quad Flat Package
SUMMARY OF SIGNALS/PINS
PIN NAME
D0 – D
17
RS Reset
EMODE Enhanced Operating Mode
WCLK Write Clo ck
WEN Write Enable
RCLK Read Clock
REN Read Enable
OE Output Enable
LD Load
FL
/RT
RXI
/REN
Data Inputs
First Load/
Read Expansio n In pu t/
2
Retransmit
2
WCLK
WEN
WEN
V
WXI/
Read Enable 2
CC
PAF
2
REN
RXI/
1
2
FF
2
EF
WXO/HF
RXO/
0
Q
Q
V
3
SS
Q
Q
PIN NAME
WXI
/WEN
Write Expansion Input/
2
Write Enable 2
FF Full Flag
P AF Programmable Almost-Full Flag
WXO/HF Write Expansion Output/Half-Full Flag
P AE Programmable Almost-Empty Flag
EF Empty Flag
RXO/
Q0 – Q
V
CC
V
SS
EF
2
17
Read Expansion Out put
Data Outputs
Power
Ground
/Empty Flag 2
540235-34
BOLD ITA LIC = Enhanced Operating Mode
4
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
PIN LIST
SIGNAL NAME PLCC PIN NO. TQFP PIN NO.
RS
OE
LD
REN
RCLK
D
17
D
16
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
PAE
FT/
RT
WCLK
WEN
WXI/
WEN
2
PAF
RXI/
REN
2
FF
WXO/HF
RXO/
EF
2
Q
0
157
258
359
460
561
763
864
91
10 2
11 3
12 4
13 5
14 6
15 7
17 8
19 9
20 10
21 11
22 12
23 13
24 14
25 15
26 16
27 17
28 18
29 19
30 20
31 21
33 23
34 24
35 25
36 26
37 27
38 28
SIGNAL NAME PLCC PIN NO. TQFP PIN NO.
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
EMODE
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
Q
16
Q
17
EF
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
39 29
41 31
42 32
44 34
46 36
47 37
48 33
49 38
50 39
52 41
53 42
55 44
56 45
58 47
59 48
61 50
63 52
64 53
66 54
662
16 NC
18 NC
32 22
40 30
43 NC
45 35
51 40
54 43
57 46
60 49
62 51
65 NC
67 55
68 56
BOLD ITALIC = Enhanced Operating Mode
5
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
PIN DESCRIPTIONS
PIN NAME
D0 – D
17
Data Inputs
PIN
TYPE
RS Reset
Enhanced
EMODE
Operating
Mode
WCLK Write Clo ck
WEN Write Enable
RCLK Read Clock
REN Read Enable I
OE Output Enable
1
Data inputs fr om an 18-bit bus.
I
When
RS is taken LO W, the FIF O ’s internal read an d w ri te p oi nters are set to
DESCRIPTION
address the first physical location of the RAM array; FF, PAF, an d HF go HIGH;
and
I
P AE and EF go LOW. The programmable-flag-offset registers
Control Register
EMODE
, below.) A reset operation is required before an initial read or write
are set to their default values. (But see the description of
operation after power-up.
When EMODE is tied LOW, the de fa ul t setting for Control Re gi ster bits 0005 after a reset operation changes to HIGH rather than LOW, thus enabling
all Control-Re gi st er- co nt r ol la bl e Enh an ce d O pe rat in g Mode features, and
allowing access to t he Co nt rol Re gi st er for reprogramming or readbac k
(see Tables 1, 2, and 5). If this behavior is desired,
EMODE may be
grounded; however, Con tro l Register bits 00-06 still may be ind iv id ua ll y
programmed to selectively enable or disable certain of the Enhanced Mode
I
features, ev en though those feat ur e s associated with i nt er l oc ke d-paralleled
operation al w ay s ar e e nabled whenever
Table 2). Alternatively, EMODE may be ti ed t o V
EMODE is being as se rte d (s ee
so that the FIFO is
CC,
functionall y IDT-compat ib le , an d the Control Register i s no t accessible or
visible, and al l of its bits rem ain LOW.
Controlling EMODE dynamically
during system operation is not recommended.
Data is written i nt o th e FIFO on a LOW-t o-HIGH transition of WCL K, whe ne ve r
WEN (Write En able) is being asserted (L O W) , and LD is HIGH. If LD is LOW, a
programmable register rather than the internal FIFO memory is written into.
I
the Enhanced O p era ti ng M o de , w he ne ver Co nt rol Re gi ster bit 06 is HIGH,
WEN
is ANDed with WEN to produce an effective internal write-enable
2
2
signal.
When
WEN is LOW an d LD is HIGH, an 18-bit data wo rd i s wri tten into the FIFO
on every LOW- to -HIG H tra nsit ion of WCLK. Whe n WEN is HI G H, th e FIFO
internal memory continues to hold the previous data (see Table 3). Data will not
I
be written into the FIFO if
whenever Contro l Register bit 06 is HI GH, WEN
produce an e ffective interna l w r it e-enable signal.
FF is LOW.
In the Enhanc ed O p era ti ng Mode,
is ANDed with WEN to
2
2
Data is read from the FIFO on a LO W -to -HIG H trans itio n of RCLK when ever
REN (Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW , a
programma ble re gist er rat her than the int erna l FIFO memo ry is re ad fro m.
I
Enhanced Opera ti ng M o de , whenever Control Regist er bit 06 is HIGH, REN
is ANDed with REN (and whenev er Control Register bit 05 is HI G H, al so
with
OE) to pro du ce an effective internal read-ena bl e signal.
When
REN is LOW and LD is HIGH, an 18-bit data word is rea d from the FI FO
on every LOW- to -HIG H tra nsit ion of RCLK. When
REN is HIGH, and/or also
2
when EF is LOW, the FIFO’s output registe r continues to hold th e previous data
word, whether or not Q
– Q17 (the data outputs) are enabled (see T able 3).
0
the Enhanced O p era ting Mode, whenever Control Register bit 06 i s HIG H,
REN
is ANDed with REN (and whenever Control Register bi t 05 is HIGH,
2
also with OE) to produce an effective internal read-enable signal.
When
OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FI FO ’s outputs are in hi gh-Z (high-impedanc e)
state.
I
In the Enhanc ed O p era ti ng Mode, OE not only continues to con trol
the outputs in this same manner, but also c an function as an additional
ANDing input to th e co mbin ed e ffective read-enable signa l, a lo ng with
and REN2, whenever Control Register b it 05 is HIGH (see Table 5).
and the
2
2
In
In the
2
In
REN
BOLD ITA LIC = Enhanced Operating Mode
6
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
PIN DESCRIPTIONS (cont’d)
PIN NAME
LD Load
WEN
REN
2
2
Write Enable 2
Read Enable 2
FF Full Flag
PAF
Programmable
Almost-Full Fl ag
HF Half-Full Flag
Programmable
PAE
Almost-Empty
Flag
EF Empty Flag
EF
2
Q0 – Q
17
V
CC
V
SS
NOTES:
1 I = Input, O = Output, Z = H igh-Impedance, V = Power V olta ge Le ve l
2 The ostensible differences in signal assertiveness are reconciled before ANDing.
Empty Flag 2
Data Outputs O/Z Data outputs to drive an 18-bit bus.
Power V +3.3 V power-supply pins.
Ground V 0 V ground pins.
PIN
TYPE
I
I
I
O
O
O
O
O
O
1
DESCRIPTION
When LD is LOW , the data word on D0 – D17 (the data in puts) is written into a
programmable-flag-offset register,
Enhanced Opera ting Mode),
or into the Co nt rol Re gi ster (when in the
on the LOW-to -HIG H tra nsitio n of WC LK, when ever
WEN is LOW (see Table 3). Also, when LD is LOW, a word is r ead to Q0 – Q17 (the
data outputs) from the offset registers
Enhanced Opera t i ng M o de )
on the LO W-to-HIGH transi ti on o f R CLK, whenever
and/or the Control Register (when in the
REN is LOW (s ee again Table 3, and p ar t i cu la rl y th e N ot es fo llowing this table) .
When LD is HIGH, normal FIFO write and read operations are enabled.
Tie L O W in St andard Mode, cascad in g is n ot supported.
Operating Mode, whenever Control Register Bit06 is HIGH,
functions as a second write-enable signal,
WEN
In the Enhand ed
WXI/WEN
, which is ANDed with WEN
2
to produce a n effective internal w r it e-enable signal.
Tie L OW in Standard Mode.
Control Register Bit06 is HIGH,
signal,
which is ANDed with REN to produce an effect ive int ernal read-
REN2,
In the Enhanc ed O p era ti ng M o de, whenever
RXI/
functions as a second read-enable
REN
2
enable signal.
When
FF is LOW, the FIFO i s fu ll ; further advanceme nt o f its internal writ e- address
pointer, and further data writes through its Data Inputs into its internal memory
array, are inhibited. When
FF is HIGH, th e FI FO is n ot f ul l. FF is synchronized to
WCLK.
P AF is LOW, the FIFO is ‘a lmo st ful l,’ based on the almost -f ull- of f set va lue
When
programme d int o t he FI FO’ s Almo st-F ul l Of f set Re gi ster. The def ault valu e of th is
offset a t re set is 127
Operating M ode, PAF is asynchronous.
, measured from ‘full’ (see Table 4). In the IDT-Compatible
10
In the Enhanced Operating Mode, PAF is
synchronized to WCLK after a reset operation, according to the state of
Control Re gi ster bit 04 (see Table 5).
In the standalo ne or para llel ed con fi gura tion , whe neve r
more than half full. In IDT-Compatible Oper at ing Mod e,
HF is LOW the device is
HF is asynch ronous;
Enhanced Opera t i ng M o de , HF may be synchroniz ed e ither to WCLK or to
RCLK after a reset operation, according to the state of Control Register bits
02 and 03 ( see Table 5) .
When
P AE is LOW, th e FIFO is ‘almost emp ty,’ based on the alm o st-empty-offset
value progra mmed into the F IF O’ s Alm ost- Empt y Of f set Re gist er. The defa ult valu e
of this offset at reset is 127
Compatible Operating Mode, PAE is asynchronous.
Mode,
P A E is s yn ch r on iz ed t o RCLK after a reset op er a ti on , according to the
, measured from ‘empty’ (see Table 4). In IDT-
10
In the Enhanced Operating
state of Control Register bit 01. (See Table 5.)
When
EF is LOW, the FIFO is empty; further advancement of its internal readaddress pointer, and further readout of data words from its internal memory array to
its Data Outputs, are inhibited. When
EF is HIGH, the FIFO is not empty. EF i s
synchronized to RCLK.
In the Enhanced Operating Mode, Control Register bit 06 is HIGH, EF
behaves as an exact duplicate of EF, but delayed by one full cycle of RCLK
with respect to
EF.
2
in the
2
BOLD ITALIC = Enhanced Operating Mode
7
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
ABSOLUTE MAXIMUM RATINGS
1.1 k Ω
680 Ω
+5 V
30 pF
*
540235-3
PARAMETER RATING
Supply V olta ge to VSS Potential –0.5 V to 7 V
Signal Pin Voltage to VSS Potential –0.5 V to VCC + 0.5 V
DC Output Current
Temperature Range with Power
Applied
2
Storage T emperature Range
Power Dissipation (PLCC Pack-
age Limit)
NOTES:
1. Only one output may be shorte d at a time, for a period not
exceeding 30 seconds.
2. Measured with clocks idle.
1
75 mA
±
–55°C to 125°C
–65°C to 150°C
2 W
DEVICE
UNDER
TEST
*
INCLUDES JIG AND SCOPE CAPACITANCES
Figure 4. Output Lo ad Cir cu it
OPERATING RANGE
SYMBOL PARAMETER MIN. MAX. UNIT
T
A
V
CC
V
SS
V
IL
V
IH
T emperature, Ambient
Supply Voltage
Supply Voltage
Logic LOW Input Voltage
Logic HIGH Input Voltage
070C
4.5 5.5 V
00V
–0.5 0.8 V
2.0 V
+ 0.5 V
CC
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC2
I
CC3
I
CC4
NOTES:
1. Output load is disconnecte d.
2. I
CC
outputs open; and, for ICC and I
AC TEST CONDITIONS
Input Pulse Leve ls VSS to 3 V
Input Rise and Fal l T i mes (10% to 90 %) 3 ns
Input Timing Reference Levels 1.5 V
Output T i ming R efe renc e Level s 1.5 V
Output Load,
Timing Tests
(Figure 5)
Input Leakage VCC = 5.5 V , VIN = 0 V to V
I/O Leakage
OE ≥ VIH, 0 V ≤ V
OUT
≤ V
CC
CC
–10 10
–10 10
Output HIGH Voltage IOH = –8.0 mA 2.4 V
Output LOW Voltage IOL = 16.0 mA 0.4 V
Average O pe ra ting Supply Current
Average Sta nd by Su pply Current
Power-Down Supply Current
Power-Down Supply Current
, I
CC2
, and I
are dependent up on actual output loading, and ICC and I
CC3
CC4
, operating at mini mum cycle times.
1,2
Measured at fCC = 50 MHz 245 mA
2
All inputs = V
2
2
All inputs = VCC – 0.2 V (clocks idle) 1 mA
All inputs = VCC – 0.2 V (clocks at 50 MHz) 1 mA
(clocks idle) 25 mA
IHMIN
are also dependent on cycle rates. Specified values are with
CC4
CAPACITANCE
PARAMETER RATING
(Top Resistor)
R
1
(Bottom Resistor)
R
2
(Load Capacitance) 30 pF
C
L
1.1k
680
Ω
Ω
CIN (Input Capacitance) VIN = 0 V 9 pF
C
(Output Ca pa ci tance) V
OUT
PARAMETER RATING
= 0 V
OUT
9 pF
A
µ
A
µ
BOLD ITA LIC = Enhanced Operating Mode
8
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
f
CC
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
Clock Cycle Frequency
Data Access T ime 2 12 3 15 3 20
Clock Cycle Time
Clock HIGH Time 8 10 14
Clock LOW Time
Data Setup Time 5 6 7
Data Hold Time 2 2 2
Enable Setup Time
Enable Hold Time 2 2 2
Reset Pulse Width
Reset Setup Time
Reset Recove ry T i m e
1
2
2
Reset to Flag and Output Time 30 35 40
Output Enab le t o O ut pu t in Low-Z
2
Output Enable t o Outpu t Valid
Output Enable t o Outpu t in Hi gh-Z
2
Write Clo ck to Full Flag
Read Clock to Em pty Flag 12 15 20
Clock to Progra mm able Almo st-F ull Flag (ID T-Compatible
Operating M ode)
–20 –25 -35
MIN. MAX. MIN. MAX. MIN. MAX.
50 40 28.6
20 25 35
81014
567
20 25 35
12 15 20
12 15 20
000
91215
19112115
12 15 20
14 17 23
t
PAE
t
HF
t
PAFS
t
PAES
t
HFS
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2
NOTES:
1. Pulse widths less than the s t ate d mi nimum values may cause incorrect operation.
2. Values are guaranteed by design; not currently tested.
3. These times also apply to the Programmable-Almost-Full and Half-Full flags when they are synchronized to WCLK.
4. These times also apply to the Half-Full and Programmable-Almost-Empty flags when they are synchronized to RCLK.
Clock to Progr amm abl e Almo st -Emp ty Fla g (I DT-Compatibl e
Operating M ode)
Clock to Half-Full Flag (IDT-Compatible O p er ating Mode)
Clock to Progra mmab le Alm ost- Fu ll Fl ag (En hanc ed
Operating Mode)
Clock to Progra mmab le Alm ost- Emp ty Fl ag (En hanc ed
Operating Mode)
Clock to Half -F ull Flag (Enhanced Operating Mode)
14 17 23
14 17 23
14 17 23
14 17 23
14 17 23
Clock to Expa ns io n- O ut 12 15 20
Expansion-In Pu ls e Wi dt h
8913
Expansion-In Setup Time 8 9 14
Skew Tim e Betwee n Rea d Clock and Wr it e Clock for Fu ll Fl ag
Skew Tim e Betwee n W ri te Cloc k and Rea d Clo ck for Em pty F lag
3
91116
4
91116
BOLD ITALIC = Enhanced Operating Mode
Rev. B, 8/8/96
9
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES
EMODE
1
H
1
H
H
H
Table 1. Grouping-Mode Determination
WXI/
WEN
RXI/
2
REN
FL/
2
RT
HHH
HHL
HLX
LHX
During a Reset Operation
MODE
Cascaded
2
Slave
Cascaded
Master
2
(Reserved)
(Reserved)
WXO/HF
USAGE
WXO WXI RXI FL RXO
WXO WXI RXI FL RXO
–––––
–––––
5
WXI/
USAGE
WEN
RXI/
2
REN
USAGE
2
FL/
RT
USAGE
RXO
/EF
USAGE
(Not
H
LL H
3
During
HF) (none) (none)
(
(RT)
(none)
Allowed
Reset)
3
H
LL L
Standalone HF (none) (none)
RT
(none)
(Not
LX X
H
3
During
HF) (WEN2)(REN2)(RT) (EF2)
(
Allowed
Reset)
Interlocked
LX X
NOTES:
1. In IDT-compatib l e c ascading, a reset operation fo rces
HIGH for the (n + 1)st FIFO.
2. The terms ‘master’ and ‘slave’ r efe r to IDT-compatible cascad ing. In pipelined cascading
3. Once grouping mode has been determined during a reset operation, FL/RT then may go HIGH to activate a retransmit operation.
EMODE must be asserted for access to the Control Register to be enabled. Also, FIFOs being used in a pipelined-cascading
4.
configuration should be in Interlocked Paralleled mode.
5. Setup-time and recovery-time specifications apply during a reset operation.
3
L
Paralleled
WXO/HF and RXO/
HF WEN
4
EF2
2
HIGH for the nth FIFO, thus for cing WXI/
4
, there is no such distinction.
REN
2
RT EF
WEN2
2
and RXI/
2
REN
2
I/O PIN
I WXI /
O
I RXI/
O
I FL/
NOTE:
1.
FL/RT may be grounded if
BOLD ITA LIC = Enhanced Operating Mode
WEN
2
WXO/HF To WXI ((n+1 )s t FI FO ) To WXI ( (n+1)st FIFO) Becomes HF
REN
2
RXO
/EF
2
RT
DEPTH-CASCADED
MASTER
From WXO (( n-1)st FIFO) From WXO (( n-1)st FIFO) Grounded
From RXO ((n-1)st FIFO) From RXO ((n-1)st FIFO) Grounded
To RXI ((n+1)st F IFO) T o R XI ((n+1)st FIFO) Unused
Grounded (Logic LOW) Logic HIGH
the Retransmit fa cility
Table 2. Expansion-Pin Usage According to
Grouping Mode
IDT-COMPATIBLE OPERATING MODE
DEPTH-CASCADED
SLAVE
is not being us ed .
STANDALONE
Becomes RT1Becomes RT
ENHANCED
OPERATING MODE
INTERLOCKED
PARALLELED
From FF (other FIFO)
Becomes HF
From EF (other FIFO)
Becomes EF
2
1
10
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
Table 3. Selection of Read and Write Operations
LD WEN
3,4
L X X – – No operation.
LL L
LL H
LH H
LH L X
LH H X
HL X
HX L X
HL X – X
HH X X X
H X L X – No read oper atio n.
HX H X X
HL L – –
H H H X X No operation.
KEY:
H = Logic ‘HIGH’; L = Logic ‘LOW’; X = ‘Don’t-care’ (logic ‘HIGH,’ logic ‘LOW,’ or any transition);
∧
= A ‘LOW’-to-‘HIGH’ tra ns ition; – = Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.
NOTES:
1. The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the selection for writi n g; the other state machine cont ro l s the selection for reading. Th ese two state machines op erate independently of each other.
Both state machines are reset to point to Word 0 by a r es et o pe ra t ion .
both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of
LD), followed by a valid memory a r r ay w r ite cy cle for t h e w riting-control state machine and/or by a valid memory a rr ay r ead cy c le
for the reading-control state machine.
2. The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is
always:
Word 0: Almost-Empty Offset Register
Word 1: Almost-Ful l O ffse t Regi st er
Word 0: Almost-Empty Offset Register
...
(repeats indefini te l y)
...
The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state
machine, is always:
Word 0: Almost-Empty Offset Register
Word 1: Almo st-Fu ll Of fse t Reg ister
Word 2: Control Register
Word 0: Almost-Empty Of fset Register
(repeats indefinitely)
Note that, in IDT-Compatible Operating Mode, W or d 2 is n ot a cc es se d; Word 0 and Word 1 alternate.
3. After normal FIFO operatio n h as begun, writing new contents into either of the offset regi sters should only be done w he n the FIFO is empty.
4. WEN2, REN2, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control
input and of Control Register bit 05.
……
……
REN
3,4
WCLK RCLK ACTION
∧∧
∧
∧
∧
Illegal combin atio n, wh ich wil l caus e erro rs.
Write to a programmable re gi st er.
X
X Hold present value of programmable-register write counter, and do not write.
Read from a programmable regi st er.
∧
Hold present value of programmable-register read counter, and do not read.
∧
Normal FIFO write operation.
X
Normal FIFO read operation.
∧
No write operation.
No write operation.
No read op er ation.
No operation.
In the Enhanced Operating Mode, if Control Register bit 00 is set,
1
2
1
2
BOLD ITALIC = Enhanced Operating Mode
11
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
Table 4. Status Flags
NUMBER OF UNREAD DATA WORDS PRESENT WITHIN FIFO
2048 × 18 FIFO 4096 × 18 FIFO
1, 2
FULL
FLAG
FF PAF HF PAE EF
MIDDLE FLAGS
EMPTY
FLAG
0 0 HHHLL
1 to q 1 to q H H H L H
(q + 1) to 1024 (q + 1) to 2048 HHHHH
1025 to (2048 – (p + 1)) 2049 to (4096 – (p + 1)) H H L H H
(2048 – p) to 2047 (4096 – p) to 4095 H L L H H
2048 4096 L L L H H
NOTES:
1. q = Programmable-Almos t-Em p ty Offset value. (Default va l ue : q = 1 27.)
2. p = Programmable-Almos t-F u l l O ffset value. (Default value: p = 127.)
3. Only 11 (2048 × 18), or all 12 (409 6 × 18), of the 12 of fse t-value-register bits shou l d b e p rogrammed. The unneeded m o st-significant-end
2048 × 18 bit should be LOW (zero).
4. The flag output is delayed b y o ne full clock cycle in Enh an ce d O perating Mode, when synchronous operation is speci fi e d for intermediate flags.
BOLD ITA LIC = Enhanced Operating Mode
12
2048 x 18/4096 x 18 Synchronous FIFOs LH540235/45
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d)
Table 5. Control-Reg ister Format
COMMAND
REGISTER
BITS
CODE
VALUE AFTER RESET FLAG
EMODE = H EMODE = L
AFFECTED,
IF ANY
DESCRIPTION NOTES
Deasserti on of LD does not
L
reset the progra mmab leregister writ e po inter and
IDT - co mpatible addressing
of programmable registers.
read pointer.
Deasserti on of
LD resets
the programmable-register
write pointer and read
00
H
LH–
pointer to address Word 0,
the Programm ab le -Al mo stEmpty-Flag-O f fse t Regis ter.
The change takes effect
Non-ambiguous
addressing of
programmable r e gi sters.
after a valid writ e opera tion
or a valid read operation,
respectively, to the mem ory
array.
↑
01
03, 02
04
L
H
LL
LH
HL,
HH
L
H
LH
PAE
LL HH HF
L
H
PAF
Set by
↑
Set and reset b y
Set by
↑
Set and reset b y
Set and reset b y
Set by
↑
Set and reset b y
RCLK, reset by
WCLK.
↑
WCLK, reset by
RCLK.
↑
WCLK, reset by
RCLK.
↑
RCLK.
↑
RCLK.
↑
WCLK.
↑
WCLK.
OE has no e ffect on an
L
internal read operation,
apart from disablin g the
outputs.
05
LH–
H
Deasserti on of OE inhibits
a read ope ration; whenever
the data outputs Q
– Q
0
17
are in the h igh-Z state, the
read pointer does n ot
advance.
L
06
11, 10,
09, 08, 07
NOTES:
When
1.
IDT72235B/45B FIFO of similar depth and speed grade. Under these conditions, the
ternal system which inclu des th e FIFO .
If
2.
EMODE
LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits
06-11 are unaffected by EMODE.
H
LLLLL LLLLL LLLLL
is HIGH, and
EMODE
is not asserted (is HIGH),
LL
Control Register bits 00-05 are LOW,
Control Register bits 00-05 remain LOW
–
–
Reserved.
Reserved. Reserved.
the FIFO behaves in a manner functionally equivalent to the
Control Register
after a reset operation.
Asynchronous flag
clocking.
Synchronous flag clocking.
Asynchronous flag
clocking.
Synchronous flag clocking
at output port.
Synchronous flag clocking
at input port.
Asynchronous flag
clocking.
Synchronous flag clocking.
Allows the read-address
pointer to ad va nce even
when Q
– Q17 are not
0
driving the output bus.
Inhibits the re ad -a dd res s
pointer from a dv anci ng
when Q
– Q17 are not
0
driving the output bus;
thus, guards agai nst da ta
loss.
Future use to c on tro l de pt h
cascading and in ter lock ed
paralleling.
is not visible or accessible to the ex-
However, if EMODE is asserted (is
BOLD ITALIC = Enhanced Operating Mode
13
LH540235/45 2048 x 18/4096 x 18 Synchronous FIFOs
Data Inputs
DATA IN (D0 – D17)
Data, programmable-flag-offset values, and
Register
D
0
trol-Register
codes are input to the FIFO as 18-bit words on
– D17. Unused bit positions in offset-value
words should be zero-filled.
Control-
and Con-
Control Inputs
RESET (RS)
The FIFO is reset whenever the asynchronous Reset
RS) input is taken to a LOW state. A reset operation is
(
required after power-up, before the first write operation
may occur. The state of the FIFO is fully defined after a
reset operation. If the default values which are entered
into the Programmable-Flag-Offset-Value Registers
the Control Register
able, then no device programming is required. A reset
operation initializes the FIFO’s internal read-address and
write-address pointers to the FIFO’s first physical memory
location. The five status flags,
are updated to indicate that the FIFO is completely empty;
thus, the first three of these are reset to HIGH, and the
last two are reset to LOW . The flag-of fset values for
PAE each are initialized to 12710. If
and
being asserted (i.e., if
Register
to operate in the IDT72235B/45B-Compatible Operating
Mode. Until a write operation occurs, the data outputs
D
0
bits are initialized to LOW, to configure the FIFO
– D17 all are LOW whenever OE is LOW.
by a reset operation are accept-
FF, PAF, HF, P AE, and EF,
EMODE
EMODE
is HIGH), all
ENHANCED OPERATING MODE (EMODE)
Whenever
EMODE is asserted during a reset operation, Control Register bits 00-05 remain HIGH
rather than LOW after the completion of the reset
operation. Thus,
EMODE has the effect of activating
all of the Enhanced-Operating-Mode features during
a reset operation. Subsequently, they may be individually disabled or re-enabled by changing the setting of Control-Register bits. The behavior of these
Enhanced-Operating-Mode features is described in
Table 5. For permanent Enhanced-Operating-Mode
operation,
trol of
EMODE must be grounded; dynamic con-
EMODE during system operation is not recom-
mended.
Asserting
causes
EMODE during a reset operation also
WXI/WEN2 to be configured as WEN2, and
RXI/REN2 to be configured as REN2, to support in terlocked-paralleled operation of two FIFOs ‘side by
side’ (see Figu re 28). Additionally ,
ured as
EF2, which duplicates the EF signal with one
RXO/EF2 is config-
extra RCK cycle delay, in order to provide proper
timing for ‘pipelined’ cascaded op eration.
and
PAF
is not
Control
WRITE CLOCK (WCLK)
A rising edge (LOW-to-HIGH transition) of WCLK initiates a FIFO write cycle if
ble-register write cycle if
and all input-side synchronous control inputs, must meet
setup and hold times with respect to the rising edge of
WCLK. The input-side status flags are meaningful after
specified time intervals, following a rising edge of WCLK.
Conceptually , the WCLK input receives a free-running,
periodic ‘clock’ waveform, which is used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that the WCLK waveform
must
be periodic. An ‘asynchronous’ mode of operation
is in fact possible, if
is, is continuously held LOW), and WCLK receiv es aperiodic ‘clock’ pulses of suitable duration. There likewise is
no requirement that WCLK must have any particular
synchronization relation to the read cloc k RCLK. These
two clock inputs may in fact receive the same ‘clock’
signal; or they may receive totally-different signals, which
are not synchronized to each other in any way.
WRITE ENABLE (
Whenever
HIGH, and the FIFO is not full, an 18-bit data word is
loaded into the effective input register for the memory
array at every WCLK risi ng edge (LOW-to-HIGH transition). Data words are stored into the two-port memory
array sequentially, regardless of any ongoing read operation. Whenever
input register retains whatever data word it contained
previously, and no new data word gets loaded into the
memory array.
To prevent overrunning the internal FIFO boundaries,
further write operations are inhibited whenever the Full
FF) is being asserted (is LOW). If a valid read
Flag (
operation then occurs, upon the completion of that read
FF again goes HIGH after a time t
cycle
write operation is allowed to begin whenever WCLK
makes another LOW-to-HIGH transition. Effectively,
WEN is overridden by FF; thus, during normal FIFO
operation,
WEN is being asserted (is LOW) and LD is
WEN is not being asserted (is HIGH), the
WEN has no effect when the FIFO is full.
LD is HIGH, or a programma-
LD is LOW. The 18 data inputs,
WEN is continuously asserted (that
WEN)
, and another
WFF
In the Enhanced Operating Mode, WXI/WEN2 functions as WEN
, an additional duplicate (albeit asser-
2
tive-HIGH) write-enable input, in order to provide
an‘interlocking’ mechanism for reliable synchronization of two parallel ed FIFOs. To control w riting,
is ANDed with WEN; this logic-AND function
WEN
2
WEN •• WEN2) then behaves like WEN in the forego-
(
ing description.
BOLD ITA LIC = Enhanced Operating Mode
14
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