Sharp LH531024D, LH531024U, LH531024N Datasheet
LH531024
CMOS 1M (64K × 16 ) MROM
FEATURES
•• 65,536 words × 16 b it organ izatio n
•• Access time: 100 ns (MAX.)
•• Power consu mption :
Operating : 412.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• JEDEC stan dard EPROM pinout (DIP)
•• Packages:
40-pi n , 600 -mil DIP
40-pi n , 525 -mil S OP
44-pi n , 650 -mil Q FJ (PLC C)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536 × 16 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
531024-1
TOP VIEW
1
2
3
4
7
8
D
11
D
14
38
37
36
35
34
33
30
27
CE
D
15
5
6
D
12
D
13
32
31
NC
NC
A
15
A
13
A
11
A
9
GND
A
6
9
10
11
40
39
NC
D
10
12
29
A
8
28
A
7
D
7
D
9
A
14
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
A
4
A
3
A
2
A
1
D
2
D
1
D
3
GND
D
5
D
4
D
6
D
0
OE
A
0
V
CC
A
12
A
10
A
5
D
8
Figure 1. Pin Connections for DI P and
SOP Packages
531024-2
TOP VIEW
40
7
8
11
12
D
8
D
11
37
36
35
34
33
32
29
D
12
9
10
D
9
D
10
31
30
A
11
A
10
GND
A
8
13
14
15
39
38
A
12
GND
16
D
5
NC
D
7
A
9
44-PIN PLCC
17
D
6
D
4
A
13
NC
A
7
41424344123456
D13D14D15CENCNC
VCCNCNCA15A
14
2827262524232221201918
D3D
2
D
1
OE
NC
A
0
A3A
4
A
6
A
5
A
2
A
1
D
0
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
531024-3
40
MEMORY
MATRIX
(65,536 x 16)
SENSE AMPLIFIER
30
GND
20
OE
ADDRESS BUFFER
CE
ADDRESS DECODER
CE
BUFFER
2
TIMING
GENERATOR
A
5
A
4
A
3
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
6
A
7
A
15
A
2
A
1
A
0
33
29
26
25
31
27
32
28
24
23
22
21
36
35
34
37
11
V
CC
OE
BUFFER
COLUMN SELECTOR
D5D4D
3
D14D13D12D11D10D9D
8
D6D
7
D
15
D2D1D
0
OUTPUT BUFFER
543 6789101213141516171819
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH531024 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME
A0 – A
15
Addres s i npu t
D
0
– D
15
Data o utp ut
CE Chip E nab le inp ut
SIGNA L PIN NAME
OE Output ena ble in put
V
CC
Pow er supp ly (+5 V )
GND Grou nd
LH531024 CMOS 1M MROM
2
531024-4
44
MEMORY
MATRIX
(65,536 x 16)
SENSE AMPLIFIER
34
GND
22
OE
ADDRESS BUFFER
CE
ADDRESS DECODER
CE
BUFFER
3
TIMING
GENERATOR
A
5
A
4
A
3
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
6
A
7
A
15
A
2
A
1
A
0
37
32
29
28
35
30
36
31
27
26
25
24
40
39
38
41
12
V
CC
OE
BUFFER
D5D4D
3
D14D13D12D11D10D9D
8
D6D
7
D
15
D2D1D
0
OUTPUT BUFFER
654 78910111415161718192021
COLUMN SELECTOR
NOTE: Pin numbers apply to the 44-pin QFJ.
Figure 4. LH531024 Block Diagram
CMOS 1M MROM LH531024
3
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