Sharp LH531000BN-S Datasheet
LH531000B-S
FEATURES
•• 131,072 words × 8 b it organ izatio n
•• Access time: 500 ns (MAX.)
•• Power consu mption :
Operating : 64 .8 mW (MAX.)
Standb y: 108 µW (MAX.)
•• Mask-programmable c ontrol pin:
Pin 20 =
CE/OE/OE
•• Static operation
•• Three-state outputs
•• Low pow er supp ly: 2.6 V to 3.6 V
•• Packa ge: 28-pi n, 450 -mil SOP
DESCRIPTION
The LH531000B-S is a mask-programmable ROM
organized as 131,072 × 8 b its. It is fabricated usi ng
silicon-gate CMOS process technology.
PIN CONNECTIONS
531000BS-1
TOP VIEW28-PIN SOP
1
2
3
4
7
8
A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
15
A
12
GND
A
13
A
8
A
11
A
10
D
7
D
6
D
3
9
10
11
28
27
A
14
A
1
V
CC
12
17
D
5
16
D
4
D
1
D
2
A
0
D
0
A
9
CE/OE/OE
13
14
A
16
Figure 1. Pin Connections for DIP Package
CMOS 1M (128K × 8) 3 V-Drive MROM
1
NOTE:
1. Active level of CE/OE/OE is mask-programmable.
531000BS-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
28
2
23
21
24
4
7
8
9
A
7
A
6
V
CC
A
4
16
17
18
11
19
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
14
3
GND
D
1D2D3D4D5D6D7
15
12
13
6
25
A
5
5
A
13
26
ADDRESS BUFFER
A
0
10
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
27
A
15
1
20
TIMING
GENERATOR
A
16
22
CE/OE/OE
OE
BUFFER
Figure 2. LH531000B-S Block Diagram
PIN DESCRIPTI ON
SIGNAL PIN NAME NOTE
A0 – A
16
Addres s i npu t
D
0
– D
7
Data o utp ut
CE/OE/OE
Chip Enab le input or
Output En abl e i npu t
1
SIGNAL PIN NAME NOTE
V
CC
Power s up ply
(2.6 V to 3.6 V)
GND Ground
LH531000B -S CMOS 1M MROM
2
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