Sharp LH531000BN, LH531000BD Datasheet
LH531000B
CMOS 1M (128K × 8) MROM
FEATURES
•• 131,072 words × 8 bi t organ izatio n
•• Access time: 150 ns (MAX.)
•• Low powe r consumption :
Operating : 192.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Programmable
CE/OE/ OE
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
28-pi n , 600 -mil DIP
28-pi n , 450 -mil S OP
•• Mask ROM specifi c pin out
DESCRIPTION
The LH531000B is a mask-programmable ROM
organized as 131,072 × 8 bits. I t is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
531000B-1
TOP VIEW
28-PIN DIP
28-PIN SOP
1
2
3
4
7
8
A
2
A
5
26
25
24
23
22
21
18
15
A
7
A
6
5
6
A
3
A
4
20
19
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
9
10
11
28
27
A
14
A
1
V
CC
12
17
D
5
16
D
4
D
1
D
2
A
0
D
0
A
9
/OE/OE
13
14
A
16
Figure 1. Pin Connections for DIP and
SOP Packages
1
NOTE:
1. Active level of CE/OE/OE is mask-programmable.
TRUTH TABLE
PIN 20 CE OE/OE MODE D0 - D
7
SUPPLY CURRENT
CE type
L – Selected D
OUT
Operating (ICC)
H – Non selected High-Z Standby (I
SB
)
OE type
– H/L Selected D
OUT
Operating (ICC)
– L/H Non selected High-Z
531000B-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
28
2
23
21
24
4
7
8
9
A
7
A
6
V
CC
A
4
16
17
1811
19
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
14
3
GND
D
1D2D3D4D5D6D7
15
12
13
6
25
A
5
5
A
13
26
ADDRESS BUFFER
A
0
10
ADDRESS DECODER
COLUMN SELECTOR
CE/OE
BUFFER
A
14
27
A
15
1
20
TIMING
GENERATOR
A
16
22
CE/OE/OE
Figure 2. LH531000B Block Diagram
PIN DESCRIPTI ON
SIGNAL PIN NAME NOTE
A0 - A
16
Add ress in put
D
0
- D
7
Data ou tpu t
CE/OE/OE
Chip En abl e i npu t o r
Outp ut Ena ble in put
1
SIGNAL PIN NAME NO TE
V
CC
Power s upp ly (+5 V )
GND Groun d
LH531000B CMOS 1M MROM
2
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