Sharp LH530800AD-Y, LH530800AN-Y Datasheet
LH530800A-Y
FEATURES
•• 131,072 words × 8 b it organ izatio n
•• Access times:
500 ns (MAX.) at 2.6 V ≤ V
CC
< 4.5 V
150 ns (MAX.) at 4.5 V ≤ V
CC
≤ 5.5 V
•• Low-pow er con sumptio n:
Operating : 19 3 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• Three-state o utputs
•• Mask-programmable control pin:
Pin 24 = OE/
OE
•• Wide ra nge powe r supp ly :
2.6 V to 5.5 V
•• Packages:
32-pi n , 600 -mil DIP
32-pi n , 525 -mil S OP
DESCRIPTION
The LH530800A-Y is a 1M-bit mask-programmable
ROM organi zed as 131,072 × 8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
CMOS 1M (128K × 8) 3 V-Drive MROM
530800A-Y-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
Vcc
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
NC
A
14
A
1
NC
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE/OE
NC
32-PIN DIP
32-PIN SOP
Figure 1. Pin Connections for DIP and
SOP Packages
1
NOTE:
1. Active levels of OE/OE are mask-programmable.
TRUTH TABLE
CE OE/OE D0 - D
7
SUPPLY CURRENT NOTE
H X High-Z Standby (ISB)1
L L/H High-Z Operating (ICC)
L H/L D
OUT
Operating (ICC)
NOTE:
1. X = H or L
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
-0.3 to +7.0 V
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 - A
16
Addr ess in put
D
0
- D
7
Data Out put
CE C hip en abl e in pu t
OE/
OE Outp ut e nab le inp ut 1
SIGNAL PIN NAME NOTE
V
CC
Power su ppl y
GND
Groun d
NC No n c onn ect ion
530800A-Y-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
3
24
22
25
6
9
10
A
7
A
6
V
CC
A
4
17
18
191220
D
0
MEMORY
MATRIX
(131,072 x 8)
SENSE AMPLIFIER
5
GND
D
1D2D3D4D5D6D7
23
16
13
14
8
26
A
5
7
A
13
27
OE/OE
ADDRESS BUFFER
CE
A
0
11
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
28
A
15
2
21
TIMING
GENERATOR
A
16
1
OUTPUT BUFFER
4
311530
Figure 2. LH530800A-Y Block Diagram
LH530800A -Y CMOS 1M Mask-Programmable ROM
2
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