Sharp LH5268AN-10LL, LH5268AD-10LL, LH5268A-10LL Datasheet

LH5268A

CMOS 6 4K (8 K × 8) S tatic RA M

FEATURES

•• 8,192 × 8 bit orga niza ti on

•• Access time: 100 ns (MAX.)

•• Power consu mption :

Operating :

220 mW (MAX.)
55 mW (MAX.) (t

RC

, tWC = 1 µs)

Standb y:

220 µ W (MAX.)

Data reten tion:

3.0 µW (V

CC

= 3 V, TA = 25°C)

•• Fully-static operatio n

•• Three-state outputs

•• Singl e +5 V p owe r su ppl y

•• TTL compatible I/O

•• Packa ges:

28-pi n , 600 -mil DIP
28-pi n , 300 -mil SK-DIP
28-pi n , 450 -mil S OP

DESCRIPTION

The LH5268A is a static RAM organized as 8, 192 × 8
bits. It is fabricated using silicon-gate CMOS process
technology.

PIN CONNECTIONS

1
2
3
4

7
8

A

2

A

5

26
25
24
23
22
21

18

15

A

7

A

6

5
6

A

3

A

4

20
19

A

12

GND

A

8

A

11

A

10

CE

1

9

10

11

28
27

WE

A

1

V

CC

12

17
16

A

0

I/O

1

A

9

13
14

NC

OE

I/O

2

I/O

3

I/O

7

I/O

6

I/O

5

I/O

4

I/O

8

CE

2

5268A-1

TOP VIEW28-PIN DIP
28-PIN SK-DIP
28-PIN SOP

Figure 1. Pin Connections for DIP, SK-DIP,

and SOP Packages

1

I/O

8

A

4

A

3

6
7

11

15

18

5268A-2

MEMORY

ARRAY

(128 x 512)

13

17

12

16

A

5

5

ROW ADDRESS

BUFFER

WE

A

6

4

A

7

3

27

A

8

25

ROW DECODERS

I/O

CIRCUITS

COLUMN DECODER

V

CC

GND

OE

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

22

19

COLUMN ADDRESS

BUFFER

23

A

11A9A10A2

8

24

21

28
14

A

12

2

CE

1

20

26

CE

2

DATA CONTROL

A

0

10

A

1

9

Figure 2. LH5268A Block Diagram

PIN DESCRIPTION

SIGNA L PIN N AME

A0 - A

12

Addre ss inputs

CE1 - CE

2

Chip Ena ble in put
WE Write E na ble inp ut
OE Outpu t E nab le inp ut

SIGNAL PIN NAME

I/O1 - I/O

8

Data i npu ts and ou tpu ts

V

CC

Power sup ply

GND Ground

NC No connec tion

LH5268A CMOS 64K (8 K × 8) Static RAM

2

TRUTH TABLE

CE

1

CE

2

WE OE MODE I/O1 - I/O

8

SUPPLY CURRENT NOTE

H X X X Deselect High-Z Standby (ISB)1
X L X X Deselect High-Z Standby (I

SB

)1

L H L X Write D

IN

Operating (ICC)1

L H H L Read D

OUT

Operating (ICC)

L H H H Output disable High-Z Operating (I

CC

)

NOTE:

1. X = H or L

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTE

Suppl y v olt age V

CC

-0.3 to +7.0 V 1

Input vol tage V

IN

-0.3 to VCC + 0.3 V 1,2

Operat ing te mpe ratu re

Topr 0 to +70 °C

Storag e t emp era ture

Tstg -65 to +150 °C

NOTES:

1. The maximum applicable voltage on any pin w ith respect to GND.

2.

VIN (MIN.) = -3.0 V f or pulse width ≤50 ns.

RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Suppl y v olt age V

CC

4.5 5.0 5.5 V

Input vol tage

V

IH

2.2 VCC + 0.3 V

V

IL

-0.3 0.8 V 1

NOTE:

1.

V

IN

(MIN.) = -3.0 V f or pulse width ≤50 ns.

DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5 V ±10%)

PARAMETER SYMBOL CONDITI ONS MIN. MAX. UNIT NOTE

Input lea kage
curren t

I

LI

VIN = 0 to V

CC

-1 1 µA

Output le aka ge
curren t

I

LO

CE1 = VIH or CE2 = V

IL

or OE = VIH or WE = V

IL

V

I/O

= 0 V to V

CC

-1 1

µA

Operat ing cu rre nt I

CC

CE1 = VIL, VIN = VIL or V

IH

CE2 = VIH, I

I/O

= 0 mA

t

CYCLE

=

100 ns

40

mA

CE1 = 0.2 V, VIN = 0.2 V or

V

CC

- 0.2 V

CE

2

= VCC - 0.2 V, I

I/O

= 0 mA

t

CYCLE

=

1.0 µs

10

Standb y c urr ent

I

SB1

CE1 = V

IH or CE2

= V

IL

3mA

I

SB

CE2 ≤ 0.2 V or

CE1 ≥ VCC - 0.2 V

40

µA

1

Output vo lta ge

V

OL

IOL = 2.1 mA 0.4 V

V

OH

IOH = -1.0 mA

2.4 V

NOTE:

1.

CE

2

should be ≥ VCC - 0.2 V or ≤ 0.2 V when CE1 ≥ VCC - 0.2 V.

CMOS 64K (8K × 8) Static RAM LH5268A

3