Sharp LH52256CT-70LL, LH52256CN-70LL, LH52256CH-70LL, LH52256CD-70LL, LH52256CHT-70LL Datasheet
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LH52256C/CH
CMOS 256K (32K × 8) Sta tic RA M
FEATURES
•• 32,768 × 8 bi t organ ization
•• Access time: 70 ns (MAX.)
•• Supply curre nt :
Operating : 45 mA (MAX.)
10 mA (MAX.) (t
RC
, tWC = 1 µs)
Standb y: 40 µA (MAX.)
•• Data retention current: 1.0 µA (MAX.)
(V
CCDR
= 3 V, TA = 25°C)
•• Wide o pera tin g vol ta ge ran g e:
4.5 V ± 5.5 V
•• Operatin g temperatu re:
Commeri cal tempe rature 0°C t o +70°C
Industrial temperature -40° to +85°C
•• Fully-static operatio n
•• Three-state outputs
•• Not design ed or rated as rad iation
hardene d
•• Packa ge:
28-pi n , 600 -mil DIP
28-pi n , 450 -mil S OP
28-pi n , 300 -mil SK-DIP
28-pi n , 8 × 3 mm
2
TSOP (Type I)
•• N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768 × 8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
52256C-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
9
A
11
OE
A
10
I/O
6
I/O
5
GND
I/O
8
I/O
7
CE
A
13
A
8
I/O
1
I/O
2
I/O
3
I/O
4
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
TOP VIEW
Figure 1. Pin Connections
2
3
4
5
6
9
10
7
8
A
11
11
1
28
27
26
25
22
21
24
23
20
19
A
10
28-PIN TSOP (Type I)
12
13
14
17
16
18
15
OE
A
8
A
9
A
13
WE
A
12
A
14
I/O
3
I/O
2
A
1
I/O
8
CE
I/O
6
I/O
7
GND
I/O
5
I/O
4
I/O
1
A
0
52256C-8
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
NOTE: Reverse bend available on request.
Figu re 2. TSOP (Type I) Pin Connections
1
A
4
A
3
52256C-2
MEMORY
ARRAY
(512 x 512)
A
5
ROW
DECORDER
WE
A
6
A
7
27
A
12
V
CC
GND
OE
22
28
14
A
13
CE
20
COLUMN I/O
CIRCUIT
COLUMN
DECODER
OUTPUT
BUFFERS
I/O
1
11
12
13
15
16
17
18
19
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
10 9
8
212423
INPUT
DATA
CONTROL
26
2
3
4
5
6
7
A
0A1A2A10A9A11
A
14
A
8
25
1
8
8
Figure 3. LH52256C Block Diagram
PIN DESCRIPTI ON
SIGNA L PIN N AME
A0 - A
14
Addre ss inputs
CE
Chip ena ble
WE
Write e nab le
OE Outpu t e nab le
SIGNAL PIN NAM E
I/O1 - I/O
8
Data i npu ts and ou tpu ts
V
CC
Power sup ply
GND
Ground
LH52256C /CH CMOS 256K (32K × 8) Static RAM
2
TRUTH TABLE
CE WE OE MODE I/O1 - I/O
8
SUPPLY CURRENT NOTE
H X X Standby High impedance Standby (ISB)1
L H L Read Data output Active (I
CC
)1
L H H Output disable High impedance Active (I
CC
)1
L L X Write Data input Active (I
CC
)1
NOTE:
1. X = Don’t care, L = Low, H = High
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Suppl y v olt age V
CC
–0.5 to +7.0 V 1
Input vol tage V
IN
–0.5 to VCC + 0.5 V 1, 2
Operat ing te mpe ratu re T
OPR
0 to +70
°C
Storag e t emp era ture T
STG
–65 to +150
°C
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. Undershoot of -3.0 V is al lowed width of pulse below 50 ns.
RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C)
PARAM ETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Suppl y v olt age V
CC
4.5 5.0 5.5 V
Input vol tage
V
IH
2.2
VCC + 0.5 V
V
IL
–0.5
0.8 V 1
NOTE:
1. Undershoot of -3.0 V is al lowed width of pulse below 50 ns.
CMOS 256K (32K × 8) Static RAM LH 52256C/CH
3
DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER SYMBOL CONDITIONS MIN. TYP . MAX. UNIT
Input lea kage
curren t
I
LI
VIN = 0 V to V
CC
–1.0
1.0 µA
Output le aka ge
curren t
I
LO
CE = VIH or OE = V
IH
V
I/O
= 0 V to V
CC
–1.0
1.0
µA
Operat ing su ppl y
curren t
I
CC
Minimum cycle, VIN = VIL or V
IH
I
I/O
= 0 mA, CE = V
IL
25 45.0
mA
I
CC1
tRC, tWC = 1 µs, VIN = VIL or VIH,
I
I/O
= 0 mA, CE = V
IL
10.0
Standb y c urr ent
I
SB
CE ≥ VCC – 0.2 V
0.6 40.0
µA
I
SB1
CE = V
IH
3.0 mA
Output vo lta ge
V
OL
IOL = 2.1 mA
0.4
V
V
OH
IOH = -1.0 mA 2.4
NOTE:
Typical values at V
CC
= 5.0 V, TA = 2 5 °C
AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETE R MODE NOTE
Input pul se level
0.6 V to 2.4 V
Input ris e a nd f all ti me
10 ns
Input and ou tpu t ti min g R ef. le vel 1.5 V
Output lo ad
1 TTL + C
L
(100 pF) 1
NOTE:
1. In cluding scope and jig capacitance.
READ CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read c yc le t ime t
RC
70
ns
Addres s a cc ess ti me t
AA
70 ns
CE acc es s t ime t
ACE
70 ns
Output en abl e t o ou tpu t v ali d
t
OE
35 ns
Output ho ld from ad dre ss cha nge t
OH
10
ns
CE Low to ou tpu t a cti ve t
LZ
10
ns 1
OE Low to ou tpu t ac tiv e t
OLZ
5
ns 1
CE Hig h t o o utp ut i n H igh im ped anc e t
HZ
030ns1
OE Hig h t o o utp ut i n H igh im ped anc e t
OHZ
030ns1
NOTES:
1.
Active output to high-impedance and high-impedance t o output active tests specified for a ±200 mV
transition from steady state levels int o the test load.
LH52256C /CH CMOS 256K (32K × 8) Static RAM
4
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