Sharp LH28F800BGN-TL85, LH28F800BGN-TL12, LH28F800BGN-BL85, LH28F800BGN-BL12 Datasheet

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F800BG-L
(FOR SOP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memory

LH28F800BG-L (FOR SOP)

DESCRIPTION

The LH28F800BG-L flash memory with Smart
Voltage technology is a high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. The LH28F800BG-L can
operate at V

CC = 2.7 V and VPP = 2.7 V. Its low

voltage operation capability realizes longer battery
life and suits for cellular phone application. Its boot,
parameter and main-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for portable
terminals and personal computers. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F800BG-L offers
two levels of protection : absolute protection with
V

PP at GND, selective hardware boot block locking.

These alternatives give designers ultimate control of
their code security needs.

FEATURES

• SmartVoltage technology
– 2.7 V, 3.3 V or 5 V V

CC

– 2.7 V, 3.3 V, 5 V or 12 V VPP

• High performance read access time
LH28F800BG-L85
– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F800BG-L12
– 120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/

150 ns (2.7 to 3.6 V)

• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read

• Enhanced data protection features
– Absolute protection with V

PP = GND

– Block erase/word write lockout during power

transitions

– Boot blocks protection except RP# = V

HH

• SRAM-compatible write interface

• Optimized array blocking architecture
– Two 4 k-word boot blocks
– Six 4 k-word parameter blocks
– Fifteen 32 k-word main blocks
– Top or bottom boot location

• Enhanced cycling capability
– 100 000 block erase cycles

• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I

CC

in static mode

• Automated word write and block erase
– Command user interface
– Status register

• ETOX

TM

∗

V nonvolatile flash technology

• Package
– 44-pin SOP (SOP044-P-0600)

∗ ETOX is a trademark of Intel Corporation.

LH28F800BG-L (FOR SOP)

- 2 -

PIN CONNECTIONS

44-PIN SOP

(SOP044-P-0600)

VPP

A18
A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

GND

OE#

DQ

0

DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RP#
WE#
A

8

A9
A10
A11
A12
A13
A14
A15
A16
NC
GND
DQ

15

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC

COMPARISON TABLE

∗1 Refer to the datasheet of LH28F800BG-L/BGH-L (FOR TSOP, CSP).

TOP VIEW

VERSIONS

OPERATING

PACKAGE

DC CHARACTERISTICS

WRITE PROTECT FUNCTION

TEMPERATURE

VCCdeep power-down current (MAX.)

FOR BOOT BLOCKS

LH28F800BG-L

0 to +70°C 44-pin SOP 10 µA Controlled by RP# pin

(FOR SOP)
LH28F800BG-L

∗

1

0 to +70°C

48-pin TSOP (I)

10 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP WP# and

RP# pins

LH28F800BGH-L

∗

1

– 40 to +85°C

48-pin TSOP (I)

20 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP

WP# and RP# pins

LH28F800BG-L (FOR SOP)

BLOCK ORGANIZATION

This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in

Fig. 1.

Boot Blocks : The two boot blocks are intended to

replace a dedicated boot PROM in a micro­processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the V

PP and RP#

pins.

Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.

Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 8 M-bit
device contains fifteen 32 k words (32 768 words)
blocks.

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INPUT

BUFFERBUFFER

OUTPUT

MULTIPLEXER

VCC

CE#

RP#

OE#

IDENTIFIER

REGISTER

COMMAND

USER

INTERFACE

WRITE
STATE

MACHINE

PROGRAM/ERASE
VOLTAGE SWITCH

I/O

LOGIC

STATUS

REGISTER

DATA

REGISTER

DATA

COMPARATOR

15

32 k-WORD

MAIN BLOCKS

X

DECODER

Y

DECODER

Y GATING

RY/BY#
V

PP

V

CC

GND

DQ0-DQ15

A0-A18

INPUT

BUFFER

ADDRESS

LATCH

ADDRESS
COUNTER

WE#

OUTPUT

BOOT BLOCK 0

BOOT BLOCK 1

PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 0

MAIN BLOCK 1

MAIN BLOCK 13

MAIN BLOCK 14

BLOCK DIAGRAM

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LH28F800BG-L (FOR SOP)

SYMBOL TYPE NAME AND FUNCTION

A

0-A18 INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.

CE# INPUT

CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode. With RP# = V

HH, block erase or word

write can operate to all blocks. Block erase or word write with V

IH < RP# < VHH produce

spurious results and should not be attempted.

OE# INPUT OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE# INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase or word write). RY/BY#-high indicates that
the WSM is ready for new commands, block erase is suspended, and word write is
inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#
is always active and does not float when the chip is deselected or data outputs are
disabled.

V

PP SUPPLY

BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or
writing words. With V

PP ≤ VPPLK, memory contents cannot be altered. Block erase and

word write with an invalid V

PP (see Section 6.2.3 "DC CHARACTERISTICS" ) produce

spurious results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V

CC down to GND and then

ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid V

CC voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.

GND SUPPLY GROUND : Do not float any ground pins.

NC NO CONNECT : Lead is not inter nal connected; recommend to be floated.

PIN DESCRIPTION

DQ0-DQ15

INPUT/

OUTPUT

RP# INPUT

RY/BY# OUTPUT

V

CC SUPPLY

LH28F800BG-L (FOR SOP)

1 INTRODUCTION

This datasheet contains LH28F800BG-L speci­fications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F800BG-L
flash memory documentation also includes ordering
information which is referenced in Section 7.

1.1 New Features

Key enhancements of LH28F800BG-L SmartVoltage
flash memory are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• Boot Block Architecture

Note following important differences :

•V

PPLK has been lowered to 1.5 V to support

2.7 V, 3.3 V and 5 V block erase and word
write operations. Designs that switch V

PP off

during read operations should make sure that
the V

PP voltage transitions to GND.

• To take advantage of SmartVoltage technology,
allow V

PP connection to 2.7 V, 3.3 V or 5 V.

1.2 Product Overview

The LH28F800BG-L is a high-performance 8 M-bit
SmartVoltage flash memory organized as 512 k­word of 16 bits. The 512 k-word of data is arranged
in two 4 k-word boot blocks, six 4 k-word parameter
blocks and fifteen 32 k-word main blocks which are
individually erasable in-system. The memory map is
shown in Fig. 1.

SmartVoltage technology provides a choice of V

CC

and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.

2.7 V V

CC consumes approximately one-fifth the

power of 5 V V

CC and 3.3 V VCC consumes

approximately one-fourth the power of 5 V V

CC.

But, 5 V V

CC provides the highest read

performance. V

PP at 2.7 V, 3.3 V and 5 V

eliminates the need for a separate 12 V converter,
while V

PP = 12 V maximizes block erase and word

write performance. In addition to flexible erase and
program voltages, the dedicated V

PP pin gives

complete data protection when V

PP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by SmartVoltage Technology

Internal VCC and VPP detection circuitry auto­matically configures the device for optimized read
and write operations.

A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase and word write
operations.

A block erase operation erases one of the device’s
32 k-word blocks typically within 0.39 second (5 V
V

CC, 12 V VPP), 4 k-word blocks typically within

0.25 second (5 V V

CC, 12 V VPP) independent of

other blocks. Each block can be independently
erased 100 000 times. Block erase suspend mode
allows system software to suspend block erase to
read data from, or write data to any other block.

Writing memory data is performed in word increments
of the device’s 32 k-word blocks typically within 8.4 µs
(5 V V

CC, 12 V VPP), 4 k-word blocks typically within

17 µs (5 V V

CC, 12 V VPP). Word write suspend

mode enables the system to read data from, or write
data to any other flash memory array location.

VCC VOLTAGE VPP VOLTAGE

2.7 V 2.7 V, 3.3 V, 5 V, 12 V

3.3 V 3.3 V, 5 V, 12 V
5 V 5 V, 12 V

- 5 -

- 6 -

LH28F800BG-L (FOR SOP)

The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by RP# (see Section 4.9 for details).
Block erase or word write for boot block must not
be carried out by RP# to V

IH.

The status register indicates when the WSM’s block
erase or word write operation is finished.

The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.

The access time is 85 ns (t

AVQV) at the VCC supply

voltage range of 4.75 to 5.25 V over the
temperature range (0 to +70°C). At 4.5 to 5.5 V
V

CC, the access time is 90 ns or 120 ns. At lower

V

CC voltage, the access time is 100 ns or 130 ns

(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I

CCR current is 1 mA at

5 V V

CC and 3 mA at 2.7 V and 3.3 V VCC.

When CE# and RP# pins are at V

CC, the ICC

CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t

PHQV) is

required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t

PHEL)

from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.

LH28F800BG-L (FOR SOP)

- 7 -

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

7FFFF
78000

77FFF

6FFFF

70000

68000
67FFF

60000
5FFFF

58000
57FFF

50000
4FFFF

48000
47FFF

40000
3FFFF

38000
37FFF

30000
2FFFF

28000
27FFF

20000
1FFFF

18000
17FFF

10000
0FFFF

08000
07FFF

07000
06FFF

06000
05FFF

05000
04FFF

04000
03FFF

03000
02FFF

02000
01FFF

01000
00FFF

00000

14

13

12

11
10

9

8
7

6
5

4

3
2

1

0

4 k-Word Parameter Block

5

4 k-Word Parameter Block

4

4 k-Word Parameter Block

3

4 k-Word Parameter Block

2

4 k-Word Parameter Block

1

4 k-Word Parameter Block

0

4 k-Word Boot Block

1

4 k-Word Boot Block

0

Bottom Boot

4 k-Word Boot Block

4 k-Word Boot Block
4 k-Word Parameter Block

4 k-Word Parameter Block

4 k-Word Parameter Block
4 k-Word Parameter Block

4 k-Word Parameter Block

4 k-Word Parameter Block

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

32 k-Word Main Block
32 k-Word Main Block

32 k-Word Main Block

7FFFF
7F000

7EFFF

7DFFF

7E000

7D000
7CFFF

7C000
7BFFF

7B000
7AFFF

7A000
79FFF

79000
78FFF

78000
77FFF

70000
6FFFF

68000
67FFF

60000
5FFFF

58000
57FFF

50000
4FFFF

48000
47FFF

40000
3FFFF

38000
37FFF

30000
2FFFF

28000
27FFF

20000
1FFFF

18000
17FFF

10000
0FFFF

08000
07FFF

00000

0

1

0

1
2

3

4
5

0
1

2

3
4

5

6

32 k-Word Main Block

7

32 k-Word Main Block

8

32 k-Word Main Block

9

32 k-Word Main Block

10

32 k-Word Main Block

11

32 k-Word Main Block

12

32 k-Word Main Block

13

32 k-Word Main Block

14

Top Boot

Fig. 1 Memory Map

BLOCK CONFIGURATION VERSIONS

Top Boot LH28F800BG-TL
Bottom Boot LH28F800BG-BL

NOTES :

LH28F800BG-L (FOR SOP)

2 PRINCIPLES OF OPERATION

The LH28F800BG-L SmartVoltage flash memory
includes an on-chip WSM to manage block erase
and word write functions. It allows for : 100% TTL­level control inputs, fixed power supplies during
block erasure and word write, and minimal
processor overhead with RAM-like interface timings.

After initial device power-up or return from deep
power-down mode (see Table 2 "Bus Operations"),
the device defaults to read array mode.
Manipulation of external memory control pins allow
array read, standby and output disable operations.

Status register and identifier codes can be
accessed through the CUI independent of the V

PP

voltage. High voltage on VPP enables successful
block erasure and word writing. All functions
associated with altering memory contents—block
erase, word write, status and identifier codes—are
accessed via the CUI and verified through the
status register.

Commands are written using standard micro­processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase
and word write. The internal algorithms are
regulated by the WSM, including pulse repetition,
internal verification and margining of data.
Addresses and data are internally latched during
write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or
outputs status register data.

Interface software that initiates and polls progress
of block erase and word write can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read/write data from/to blocks other than that which
is suspended. Word write suspend allows system

software to suspend a word write to read data from
any other flash memory array location.

2.1 Data Protection

Depending on the application, the system designer
may choose to make the V

PP power supply

switchable (available only when memory block
erases or word writes are required) or hardwired to
V

PPH1/2/3. The device accommodates either design

practice and encourages optimization of the
processor-memory interface.

When V

PP ≤ VPPLK, memory contents cannot be

altered. The CUI, with two-step block erase or word
write command sequences, provides protection
from unwanted operations even when high voltage
is applied to V

PP. All write functions are disabled

when V

CC is below the write lockout voltage VLKO

or when RP# is at VIL. The device’s boot blocks
locking capability for RP# provides additional
protection from inadvertent code or data alteration
by block erase and word write operations. Refer to

Table 5 for write protection alternatives.

3 BUS OPERATION

The local CPU reads and writes flash memory in­system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier
codes or status register independent of the V

PP

voltage. RP# can be at either VIH or VHH.

The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power­down mode, the device automatically resets to read
array mode. Four control pins dictate the data flow
in and out of the component : CE#, OE#, WE# and
RP#. CE# and OE# must be driven active to obtain

- 8 -

- 9 -

LH28F800BG-L (FOR SOP)

data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data output (DQ

0-DQ15)

control and when active drives the selected
memory data onto the I/O bus. WE# must be at V

IH

and RP# must be at VIH or VHH. Fig. 11 illustrates
read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins (DQ

0-DQ15) are

placed in a high-impedance state.

3.3 Standby

CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ

0-DQ15 outputs are placed

in a high-impedance state independent of OE#. If
deselected during block erase or word write, the
device continues functioning, and consuming active
power until the operation completes.

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t

PHQV is required

after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.

During block erase or word write modes, RP#-low
will abort the operation. RY/BY# remains low until
the reset operation is complete. Memory contents
being altered are no longer valid; the data may be
partially erased or written. Time t

PHWL is required

after RP# goes to logic-high (V

IH) before another

command can be written.

As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase or
word write modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may
not occur because the flash memory may be
providing status information instead of array data.
SHARP’s flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the
manufacture code and device code (see Fig. 2).
Using the manufacture and device codes, the
system CPU can automatically match the device
with its proper algorithms.

Fig. 2 Device Identifier Code Memory Map

3.6 Write

Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V

CC = VCC1/2/3/4 and VPP = VPPH1/2/3, the CUI

additionally controls block erasure and word write.

The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word Write command requires the

7FFFF

00002
00001
00000

Reserved for

Future Implementation

Device Code

Manufacture Code

- 10 -

LH28F800BG-L (FOR SOP)

command and address of the location to be written.

The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used. Fig. 12 and
Fig. 13 illustrate WE# and CE# controlled write
operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing V

PPH1/2/3 on VPP enables

successful block erase and word write operations.

Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.

Table 2 Bus Operations

MODE NOTE RP# CE# OE# WE#

ADDRESS

V

PP

DQ

0-15

RY/BY#

Read 1, 2, 3, 8

VIHor V

HH

V

IL

V

IL

V

IH

XXD

OUT

X

Output Disable 3

VIHor V

HH

V

IL

V

IH

V

IH

X X High Z X

Standby 3

VIHor V

HH

V

IH

XXXXHigh Z X

Deep Power-Down 4 VIL XXXXXHigh Z V

OH

Read Identifier Codes 8

VIHor V

HH

V

IL

V

IL

V

IH

See Fig. 2

X(

NOTE 5)

V

OH

Write 3, 6, 7, 8

VIHor V

HH

V

IL

V

IH

V

IL

XXDINX

NOTES :

1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When V

PP ≤ VPPLK, memory contents can be read, but

not altered.

2. X can be V

IL or VIH for control pins and addresses, and

V

PPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC

CHARACTERISTICS" for V

PPLK and VPPH1/2/3 voltages.

3. RY/BY# is V

OL when the WSM is executing internal

block erase or word write algorithms. It is V

OH during

when the WSM is not busy, in block erase suspend
mode (with word write inactive), word write suspend
mode or deep power-down mode.

4. RP# at GND±0.2 V ensures the lowest deep power­down current.

5. See Section 4.2 for read identifier code data.

6. Command writes involving block erase or word write are
reliably executed when V

PP = VPPH1/2/3 and VCC =

V

CC1/2/3/4. Block erase or word write with VIH < RP# <

V

HH produce spurious results and should not be

attempted.

7. Refer to Table 3 for valid D

IN during a write operation.

8. Don’t use the timing both OE# and WE# are V

IL.

LH28F800BG-L (FOR SOP)

- 11 -

COMMAND

BUS CYCLES

NOTE

FIRST BUS CYCLE SECOND BUS CYCLE

REQ’D.

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Oper

(NOTE 1)

Addr

(NOTE 2)

Data

(NOTE 3)

Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 4 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 5 Write BA 20H Write BA D0H
Word Write 2 5, 6 Write WA

40H or 10H

Write WA WD

Block Erase and

1 5 Write X B0H

Word Write Suspend
Block Erase and

1 5 Write X D0H

Word Write Resume

Table 3 Command Definitions

(NOTE 7)

NOTES :

1. Bus operations are defined in Table 2.

2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.

3. SRD = Data read from status register. See Table 6 for a

description of the status register bits.

WD = Data to be written at location WA. Data is latched

on the rising edge of WE# or CE# (whichever
goes high first).

ID = Data read from identifier codes.

4. Following the Read Identifier Codes command, read
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.

5. If the block is boot block, RP# must be at V

HH to enable

block erase or word write operations. Attempts to issue a
block erase or word write to a boot block while RP# is
V

IH.

6. Either 40H or 10H is recognized by the WSM as the
word write setup.

7. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.

- 12 -

LH28F800BG-L (FOR SOP)

4.1 Read Array Command

Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the V

PP voltage and

RP# can be V

IH or VHH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the V

PP voltage and RP# can be

V

IH or VHH. Following the Read Identifier Codes

command, the following information can be read :

Table 4 Identifier Codes

4.3 Read Status Register Command

The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on

the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to V

IH before further reads

to update the status register latch. The Read Status
Register command functions independently of the
V

PP voltage. RP# can be VIH or VHH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.

To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V

PP voltage. RP# can

be V

IH or VHH. This command is not functional

during block erase or word write suspend modes.

4.5 Block Erase Command

Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.

CODE ADDRESS DATA

Manufacture Code 00000H 00B0H
Device Code (Top Boot) 00001H 0060H
Device Code (Bottom Boot) 00001H 0062H