Sharp LCM3700 Schematic

LC-M3700

LC-M3710

LC-M3700

1st Edition

LC-M3710

SERVICE MANUAL

WIDE LCD MONIT OR

LC-M3700

MODELS

LC-M3710

In the interests of user-safety (Required by safety regulations in some countries) the set should be restored
to its original condition and only parts identical to those specified should be used.

CONTENTS

Page

» IMPORTANT SERVICE SAFETY PRECAUTION.........................................................................................2

» SPECIFICATIONS ........................................................................................................................................6

» OPERATION MANUAL .................................................................................................................................7

» DIMENSIONS .............................................................................................................................................12

» REMOVING OF MAJOR PARTS ................................................................................................................13

» ADJUSTING PROCEDURE OF EACH SECTION .....................................................................................17

» HOW TO UPGRADE THE INTERNAL PROGRAM....................................................................................30

» DESCRIPTION OF FUNCTION OF MAJOR ICs .......................................................................................34

» CHASSIS LAYOUT .....................................................................................................................................58

» BLOCK DIAGRAM......................................................................................................................................60

» OVERALL WIRING DIAGRAM ...................................................................................................................68

» DESCRIPTION OF SCHEMATIC DIAGRAM .............................................................................................72

» SCHEMATIC DIAGRAM .............................................................................................................................73

» PRINTED WIRING BOARD ASSEMBLIES..............................................................................................132

» REPLACEMENT PARTS LIST..................................................................................................................173

» PACKING OF THE SET ............................................................................................................................212

SHARP CORPORATION

This document has been published to be used for
after sales service only.
The contents are subject to change without notice.

LC-M3700

3

2

2

LC-M3710

IMPORTANT SERVICE SAFETY PRECA UTION

Ë

Service work should be performed only by qualified service technicians who are thor­oughly familiar with all safety checks and the servicing guidelines which follow:

WARNING

1. For continued safety, no modification of any circuit
should be attempted.

2. Disconnect AC power before servicing.

» Use an AC voltmeter ha ving with 5000 ohm per v olt,

or higher, sensitivity or measure the A C v oltage drop
across the resistor.

» Connect the resistor connection to all exposed metal

CAUTION: FOR CONTINUED PROTECTION
AGAINST A RISK OF FIRE REPLACE ONLY WITH
SAME TYPE FUSE.
F7501, F7502, F7503, F7504, F7551, F7552, F7553,
F7611, F7612, F7613, F7614, F7641, F7642, F7643
(T315mAL, 250V), F2701, F2702 (T4AH, 250V)

parts having a return to the chassis (antenna, metal
cabinet, screw heads, knobs and control shafts,
escutcheon, etc.) and measure the AC voltage drop
across the resistor.
All checks must be repeated with the AC cord plug
connection reversed. (If necessar y, a nonpolarized
adaptor plug must be used only for the purpose of
completing these checks.)
Any reading of 0.75 Vrms (this corresponds to 0.5

BEFORE RETURNING THE RECEIVER
(Fire & Shock Hazard)

mA. rms AC.) or more is excessive and indicates a
potential shock hazard which must be corrected
before returning the monitor to the owner.

Before returning the receiver to the user, perform
the following safety checks:

1. Inspect all lead dress to make certain that leads are
not pinched, and check that hardware is not lodged
between the chassis and other metal parts in the
receiver.

2. Inspect all protective devices such as non-metallic
control knobs, insulation materials, cabinet backs,
adjustment and compartment covers or shields,
isolation resistor-capacitor networks, mechanical

DVM

AC SCALE

1.5k ohm
10W

insulators, etc.

3. To be sure that no shock hazard exists, check for
leakage current in the following manner.

» Plug the AC cord directly into a 110~240 volt A C outlet.
» Using two clip leads, connect a 1.5k ohm, 10 watt

0.15 µF

TEST PROBE

resistor paralleled by a 0.15µF capacitor in series
with all exposed metal cabinet parts and a known
earth ground, such as electrical conduit or electrical
ground connected to an earth ground.

2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212

TO EXPOSED
METAL PARTS

CONNECT TO
KNOWN EARTH
GROUND

SAFETY NOTICE

Many electrical and mechanical parts in WIDE LCD
MONITOR have special safety-related characteristics.
These characteristics are often not evident from visual
inspection, nor can protection afforded by them be
necessarily increased by using replacement components
rated for higher voltage , w attage , etc.
Replacement parts which have these special safety
characteristics are identified in this manual; electrical

and shaded areas in the

Schematic Diagrams.

For continued protection, replacement parts must be
identical to those used in the original circuit.
The use of a substitute replacement parts which do not
have the same safety characteristics as the factory
recommended replacement parts shown in this service
manual, may create shock, fire or other hazards.

components having such features are identified by “ å”

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

2

Replacement Parts List

and

LC-M3700

2

2

LC-M3710

PRECAUTIONS A PRENDRE LORS DE LA REPARATION

Ë

Ne peut effectuer la réparation qu' un technicien spécialisé qui s'est parfaitement
accoutumé à toute vérification de sécurité et aux conseils suivants.

AVERTISSEMENT

de 0,15µF en série avec toutes les pièces métalliques
exposées du coffret et une terre connue comme une

1. N'entreprendre aucune modification de tout circuit.
C'est dangereux.

2. Débrancher le récepteur avant toute réparation.

PRECAUTION: POUR LA
PROTECTION CONTINUE CONTRE
LES RISQUES D'INCENDIE,
REMPLACER LE FUSIBLE
F7501, F7502, F7503, F7504, F7551,

A V

F7552, F7553, F7611, F7612, F7613,
F7614, F7641, F7642, F7643
(T315mAL, 250V), F2701, F2702
(T4AH, 250V)

conduite électrique ou une prise de terre branchée à
la terre.

• Utiliser un voltmètre CA d'une sensibilité d'au moins
5000Ω/V pour mesurer la chute de tension en travers
de la résistance.

• Toucher avec la sonde d'essai les pièces métalliques
exposées qui présentent une voie de retour au châssis
(antenne, coffret métallique, tête des vis, arbres de
commande et des boutons, écusson, etc.) et mesurer
la chute de tension CA en-travers de la résistance.
Toutes les vérifications doivent être refaites après avoir
inversé la fiche du cordon d'alimentation. (Si
nécessaire, une prise d'adpatation non polarisée peut
être utilisée dans le but de terminer ces vérifications.)
Tous les courants mesurés ne doivent pas dépasser

VERIFICATIONS CONTRE L'INCEN-DIE ET
LE CHOC ELECTRIQUE

Avant de rendre le récepteur à l'utilisateur, effectuer

0,5 mA.
Dans le cas contraire, il y a une possibilité de choc
électrique qui doit être supprimée avant de rendre le
récepteur au client.

les vérifications suivantes.

1. Inspecter tous les faisceaux de câbles pour s'assurer
que les fils ne soient pas pincés ou qu'un outil ne soit
pas placé entre le châssis et les autres pièces
métalliques du récepteur.

2. Inspecter tous les dispositifs de protection comme les
boutons de commande non-métalliques, les isolants,
le dos du coffret, les couvercles ou blindages de réglage

DVM

ECHELLE CA

1.5k ohm
10W

et de compartiment, les réseaux de résistance­capacité, les isolateurs mécaniques, etc.

3. S'assurer qu'il n'y ait pas de danger d'électrocution en
vérifiant la fuite de courant, de la facon suiv ante:

• Brancher le cordon d'alimentation directem-ent à une

0.15 µF

SONDE D'ESSAI

prise de courant de 110-240V. (Ne pas utiliser de
transformateur d'isolation pour cet essai).

• A l'aide de deux fils à pinces, brancher une résistance
de 1.5 kΩ 10 watts en parallèle a v ec un condensateur

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

AUX PIECES
METALLIQUES
EXPOSEES

BRANCHER A UNE
TERRE CONNUE

AVIS POUR LA SECURITE

De nombreuses pièces, électriques et mécaniques,
dans les téléviseurs présentent des caractéristiques
spéciales relatives à la sécurité, qui ne sont souvent
pas évidentes à vue. Le degré de protection ne peut
pas être nécessairement augmentée en utilisant des
pièces de remplacement étalonnées pour haute tension,
puissance, etc.
Les pièces de remplacement qui présentent ces
caractéristiques sont identifiées dans ce manuel; les
pièces électriques qui présentent ces particularités sont

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

identifiées par la marque " å " et hachurées dans la
liste des pièces de remplacement et les diagrammes
schématiques.
Pour assurer la protection, ces pièces doivent être
identiques à celles utilisées dans le circuit d'or igine.
L'utilisation de pièces qui n'ont pas les mêmes
caractéristiques que les pièces recommandées par
l'usine, indiquées dans ce manuel, peut provoquer des
électrocutions, incendies, radiations X ou autres
accidents.

3

LC-M3700

2
2

LC-M3710

IMPORTANT SERVICE SAFETY PRECA UTION

Ë

Service work should be performed only by qualified service technicians who are thor­oughly familiar with all safety checks and the servicing guidelines which follow:

WARNING

1. For continued safety, no modification of any circuit
should be attempted.

2. Disconnect AC power before servicing.

CAUTION: FOR CONTINUED PROTECTION
AGAINST A RISK OF FIRE REPLACE ONLY WITH
SAME TYPE FUSE.
F7501, F7502, F7503, F7504, F7551, F7552, F7553,
F7611, F7612, F7613, F7614, F7641, F7642, F7643
(T315mAL, 250V), F2701, F2702 (T4AH, 250V)

BEFORE RETURNING THE RECEIVER
(Fire & Shock Hazard)

Before returning the receiver to the user, perform
the following safety checks:

1. Inspect all lead dress to make certain that leads are
not pinched, and check that hardware is not lodged
between the chassis and other metal parts in the
receiver.

2. Inspect all protective devices such as non-metallic
control knobs, insulation materials, cabinet backs,
adjustment and compartment covers or shields,
isolation resistor-capacitor networks, mechanical
insulators, etc.

3. To be sure that no shock hazard exists, check for
leakage current in the following manner.

» Plug the AC cord directly into a 220~240 volt A C outlet.
» Using two clip leads, connect a 50k ohm, 10 watt

resistor paralleled by a 0.15µF capacitor in series
with all exposed metal cabinet parts and a known
earth ground, such as electrical conduit or electrical
ground connected to an earth ground.

» Use an AC voltmeter ha ving with 5000 ohm per v olt,

or higher, sensitivity or measure the A C v oltage drop
across the resistor.

» Connect the resistor connection to all exposed metal

parts having a return to the chassis (antenna, metal
cabinet, screw heads, knobs and control shafts,
escutcheon, etc.) and measure the AC voltage drop
across the resistor.
All checks must be repeated with the AC cord plug
connection reversed. (If necessar y, a nonpolarized
adaptor plug must be used only for the purpose of
completing these checks.)
Any reading of 35V peak (this corresponds to 0.7
mA. peak AC.) or more is excessive and indicates a
potential shock hazard which must be corrected
before returning the monitor to the owner.

DVM

AC SCALE

50k ohm

10W

0.15 µF

TEST PROBE

TO EXPOSED
METAL PARTS

CONNECT TO
KNOWN EARTH
GROUND

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

SAFETY NOTICE

Many electrical and mechanical parts in WIDE LCD
MONITOR have special safety-related characteristics.
These characteristics are often not evident from visual
inspection, nor can protection afforded by them be
necessarily increased by using replacement components
rated for higher voltage , w attage , etc.
Replacement parts which have these special safety
characteristics are identified in this manual; electrical

and shaded areas in the

Schematic Diagrams.

For continued protection, replacement parts must be
identical to those used in the original circuit.
The use of a substitute replacement parts which do not
have the same safety characteristics as the factory
recommended replacement parts shown in this service
manual, may create shock, fire or other hazards.

components having such features are identified by “ å”

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121

Replacement Parts List

and

4

LC-M3700
LC-M3710

Precautions for using lead-free solder

1 Employing lead-free solder

"PWBs" of this model employs lead-free solder. The LF symbol indicates lead-free solder, and is attached on the
PWBs and service manuals. The alphabetical character following LF shows the type of lead-free solder.
Example:

L Fa

Indicates lead-free solder of tin, silver and copper.

2 Using lead-free wire solder

When fixing the PWB soldered with the lead-free solder, apply lead-free wire solder. Repairing with conventional
lead wire solder may cause damage or accident due to cracks.
As the melting point of lead-free solder (Sn-Ag-Cu) is higher than the lead wire solder by 40°C, we recommend
you to use a dedicated soldering bit, if you are not familiar with how to obtain lead-free wire solder or soldering bit,
contact our service station or service branch in your area.

3 Soldering

As the melting point of lead-free solder (Sn-Ag-Cu) is about 220°C which is higher than the conventional lead
solder by 40°C, and as it has poor solder wettability, you may be apt to keep the soldering bit in contact with the
PWB for extended period of time. However, Since the land may be peeled off or the maximum heat-resistance
temperature of parts may be exceeded, remov e the bit from the PWB as soon as you confirm the steady soldering
condition.
Lead-free solder contains more tin, and the end of the soldering bit may be easily corroded. Mak e sure to turn on
and off the power of the bit as required.
If a different type of solder stays on the tip of the soldering bit, it is allo y ed with lead-free solder. Clean the bit after
every use of it.
When the tip of the soldering bit is blackened during use, file it with steel wool or fine sandpaper.

Be careful when replacing parts with polarity indication on the PWB silk.

Lead-free wire solder for servicing

Part No, ★ Description Code
ZHNDAi123250E J φ0.3mm 250g(1roll) BL
ZHNDAi126500E J φ0.6mm 500g(1roll) BK
ZHNDAi12801KE J φ1.0mm 1kg(1roll) BM

5

LC-M3700
LC-M3710

SPECIFICATIONS

Product
Model

Screen size

LCD Panel Drive

Number of dots
Colour system
Speaker
Audio amplifier
Terminals

Power requirement
Power consumption
Standby power consumption
Dimensions
Weight
Operating temperature 0°C – +40°C
Operating humidity 20% – +80%

Wide LCD Monitor
LC-M3700/LC-M3710
37” (819.6 mm (width) x 460.8 mm (height), 940.3 mm (diagonal))
TFT (thin film transistor) Active Matrix
3,147,264 dots (768 (height) x 1,366 (width) x 3)
NTSC (3.58/4.43MHz), PAL/PAL-60, SECAM

ø

5 cm, 1 piece
External speakers: 20 W (10 W + 10 W) Built-in monitor speaker: 0.8 W
INPUT1 VIDEO in (BNC), S-video in, AUDIO (L/R) in
INPUT2(INPUT/OUTPUT
VIDEO OUTPUT VIDEO out (BNC)
INPUT3 (Y/G, Cr/Pr/R, COMPONENT video in/PC (ANALOG) in (BNC),
Cb/Pb/B, HD, VD) AUDIO in (stereo jack, ø 3.5mm)
INPUT3/PC(ANALOG)
OUTPUT
PC(ANALOG)INPUT PC (ANALOG) INPUT in (Mini D-Sub 15 pin),

PC(DIGITAL)INPUT PC (DIGITAL) INPUT in (DVI-D)
RS-232C INPUT terminal (9 pins), RS-232C OUTPUT terminal (9 pins),
SPEAKER terminal (L/R), AC input terminal
AC110 - 240V, 50/60Hz
182 W

1.2 W
949 mm x 99.5 mm x 572 mm
19 kg (without stand)

VIDEO in/out (RCA), AUDIO (L/R) in/out

INPUT3/PC (ANALOG) OUTPUT (Mini D-Sub 15 pin)

AUDIO in (stereo jack, ø 3.5 mm)

Ë

As a part of policy of continuous improvement, SHARP reserves the right to make design and specification
changes for product improvement without prior notice. The performance specification figures indicated are
nominal values of production units. There may be some deviations from these values in individual units.

6

Part Names – Display

MENU

ENTER

UP

RIGHT

LEFT

DOWN

INPUT

VOL

Liquid Crystal Display panel

Side control panel

(See below.)

Front view

Side control panel

Remote

control sensor

*

When using the

remote control, point

it towards here.

STANDBY/ON

button

STANDBY/ON

indicator

Panel side

MENU

ENTER

VOL +/–

UP

LEFT

RIGHT

DOWN

INPUT

Menu operation

buttons

Cursor

control

LC-3700 LC-3710

About LC-M3710:

»

The SHARP logo for the LC-M3710 model is

on the vertical base.

Removing the terminal cover

1. Hold down the two claws at the top of the terminal

cover, and pull the cover toward you so it opens a

little.

2. Slowly lift the cover so the three claws at the bottom

come loose from the claw holes in the console.

2

1

3

Rear view

Built-in monitor

speaker

SPEAKER (R)

External speaker terminal

(right)

POWER

Main power on/off

switch

SPEAKER (L)

External speaker terminal

(left)

AC Input

terminal

INPUT2 (INPUT/

OUTPUT)

VIDEO OUTPUT

RS-232C INPUT

RS-232C OUTPUT

INPUT1

PC (DIGITAL) INPUT

INPUT3/PC (ANALOG)

OUTPUT

INPUT3

PC (ANALOG)

INPUT

Removing the terminal cover

Lower claw

Upper claw

OPERATION MANUAL

LC-M3700
LC-M3710

7

LC-M3700

Part Names – Remote Control Unit

INPUT

RETURN

MENU

STANDBY/ON

ENLARGE

WIDE

LCD MONITOR

ENTER

VOL

Signal transmitter

Remote control unit

STANDBY/ON

MENU

VOL +/–

ENLARGE

INPUT

RETURN

WIDE

Cursor control ('/"/\/|)

ENTER

INPUT1

INPUT1: Terminals are provided for two types of video input signal. Input Select

No matter which video signal is selected, the system uses the signal input to the audio terminals for

audio.

Related topic:

Input Select

*1 “Auto” (automatic colour system detection) is factory preset value. Color System

INPUT 1

AUDIO

VIDEOS-VIDEO

R - - L

1

S-video

INPUT1

audio

Video

Connecting Peripheral Equipment

Terminal type

BNC

S terminal

Compatible signals

NTSC (3.58/4.43), PAL, SECAM (*1)

NTSC (3.58/4.43), PAL, SECAM (*1)

Video

S-video

LC-M3710

8

Connecting Peripheral Equipment (Continued)

INPUT2

INPUT 2 (INPUT/OUTPUT)

VIDEO

AUDIOR - - L

2

INPUT2

audio

Video

Terminal type

RCA

Compatible signals

NTSC (3.58/4.43), PAL, SECAM (*2)Video

INPUT2: Input or output can be selected for INPUT2. (*1) INPUT2 Select

This setting cannot be switched when INPUT2 is currently being displayed.

When this is set to

“Output”, video signals input fr

om the INPUT1 video input terminal are output. (*3)

An audio signal is output with this setting (i.e. the audio signal corresponding to the video currently

being displayed). (*4)

Related topic:

*1 “Input” is factory preset value.

*2 “Auto” (automatic colour system detection) is factory preset value. Color System

*3 Outputs video from INPUT1, regardless of the currently displayed signal.

*4 If the “INPUT2 Select” is set to “Output”, audio output is as follows

.

Example 1

Input Selection : INPUT1

“Input Select” : AV

Example 2

Input Selection : INPUT3

“Input Select” : RGB

INPUT2 video output: Video from INPUT1

INPUT2 audio output: Audio from INPUT1

INPUT2 video output: Video from INPUT1

INPUT2 audio output: Audio from INPUT3

INPUT3

INPUT 3

AUDIOPr/Cr/RPb/Cb/B VDHDY/G

3

Input Select: RGB

INPUT3 audio

Input Select:

COMPONENT

Horizontal

sync signal (H sync)

Vertical

sync signal (V sync)

The signal is input with the Y/Pb/Pr (Y/Cb/Cr) terminals. The HD and VD terminals are

not used. Video adjustment options on the menu are the AV type.

Compatible input range: 480i/576i, 480p/576p, 1080i (50Hz (*4) /60Hz), 720p (60Hz). (*1)

The monitor operates using Video (RGB) and Sync (HD/VD) signals, just like a PC

(analog). Supported sync signals are ordinary separate sync (HD/VD) and Sync On

Green. (*2) (*3)

Video adjustment options on the menu are the PC type.

Compatible input range: Conforms to PC (analog). Appendix 1

COMPONENT

RGB

Ë INPUT3: Either COMPONENT or RGB can be selected for the input video signal. Input Select

Related topic:

Input Select

*1 Auto-detects video signal frequency.

*2 Automatic sync signal type detection

*3 Sync signal presence is detected in the order: Separate Sync Sync On Green. If for some reason

Separate Sync is not input, the system will operate assuming that the signal is a Sync On Green

signal (i.e. that the sync signal is contained in the G signal of RGB), and this may result in an

unstable image, depending on the video signal.

*4 1080i (50Hz) corresponds to a SMPTE274M signal. (Horizontal frequency is 28.125kHz)

LC-M3700
LC-M3710

9

LC-M3700

PC

Terminal type

D-Sub15-pin

DVI-D

Compatible signals

VGA, SVGA, XGA, SXGA and others Appendix 1

In addition to ordinary Separate Sync (HD/VD) signals, the system is also

compatible with Composite Sync (Csync) and Sync On Green. (*1) (*2)

VGA, SVGA, XGA, SXGA and others Appendix 1

Analog

Digital

Connecting Peripheral Equipment (Continued)

PC: Terminals for two kinds of PC video input signal are available. Input Select

No matter which video signal is selected, the system uses the signal input to the audio terminals for

audio.

Related topic:

*1 Auto-detects Sync signal type.

*2 Sync signal presence is detected in the order: Separate Sync Composite Sync Sync On

Green. If for some reason neither Separate Sync nor Composite Sync is input, the system will

operate assuming that the signal is a Sync On Green signal (i.e. that the sync signal is contained in

the G signal of RGB), and this may result in an unstable image, depending on the video signal.

PC(DIGITAL)INPUT

PC (digital) video

PC(ANALOG)INPUT

AUDIO

PC (analog) video

PC audio

VIDEO OUTPUT

Ë When INPUT2 is displayed, video from INPUT2 is output. Otherwise video from INPUT1 is output.

INPUT3/PC (ANALOG) OUTPUT

Ë When INPUT3 is displayed, video from INPUT3 is output. Otherwise PC (analog) video is output.

RS-232C INPUT/RS-232C OUTPUT

Ë The RS-232C INPUT and RS-232C OUTPUT are used to control this monitor with a PC.

To connect a single monitor to a PC, connect to the RS-232C INPUT terminal.

To connect multiple monitors in a daisy chain for control by PC, use the RS-232C OUTPUT terminal.

RS-232C INPUT

RS-232C OUTPUT

INPUT 3 / PC (ANALOG) OUTPUT

VIDEO

OUTPUT

Video

LC-M3710

10

Appendix 3: Menu Option Reference Chart

Contrast

Black Level

Red

Green

Blue

Advanced

Reset

0 - 40

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–10 - 0 - +10

Yes, No

Picture

Lock Item

PIN

PIN Clear

Control Lock

Input Select

Input Signal *

1

Auto Sync.

Fine Sync.

Picture Flip

Language

INPUT2 Select

ID No. Setting

Enlarge

Panel Protection Cover

Wide Mode

DNR

Quick Shoot

Monitor Speaker Output

H-Pos.

V-Pos .

Clock

Phase

Reset

0 - 180

0 - 99

0 - 180

0 - 40

Yes, No

Yes, No

Yes, No

Off

22

33

Select the position from 1 to 4

Select the position from 1 to 9

Menu Display

Remote

Buttons

Power

RS-232C

Lock, Unlock

Lock, Unlock

Lock, Unlock

Lock, Unlock

Lock, Unlock

Setup

–15 - 0 - +15

–15 - 0 - +15

L 30 - 0 - R 30

Yes, No

–8 - 0 - +8

Off, Mode1, Mode2

Audio

Brightness

Power Management

Input 4 digit numbers

Yes, No

Power

control

Normal, Full, Cinema, Dot by Dot *

3

Off, High, Low

On, Off

On, Off

Option

Treble

Bass

Balance

Reset

Analog, Digital *

1

640 480, 720 400, 640 480, 848 480, 852 480,

1024 768, 1280 768, 1366 768, 640 480p *

2

Start Now

When Connected

Normal, Mirror, Upside Down, Rotate

Japanese, English, Deutsch, Français, Español

Input, Output

Input numbers from 000 to 255

C.M.S. (H)

C.M.S. (S)

C.M.S. (V)

C.M.S.

R

Y

G

C

B

M

Reset

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

Yes, No

Attached, Detached

Menu option reference chart: PC input mode

*1 May not be displayed for certain signal types.

*2 Items displayed may vary according to input signal types.

*3 Items displayed may vary according to input signal types.

» Depending on the conditions, certain menu items may be displayed in grey. These items cannot be selected.

NOTE:

×

×

××××

××××

×

C.M.S. (H)

C.M.S. (S)

C.M.S. (V)

Color Temp

Black

3D-Y/C

Monochrome

Film Mode

I/P Setting

Contrast

Black Level

Color

Tint

Sharpness

Advanced

Reset

High, Mid-High, Mid, Mid-Low, Low

Off, High, Low

Standard, Fast, Slow

On, Off

On, Off

Interlace, Progressive

C.M.S.

R

Y

G

C

B

M

Reset

0 - 40

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–10 - 0 - +10

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

–30 - 0 - +30

Yes, No

Yes, No

Picture

Lock Item

PIN

PIN Clear

Wide Mode

Color System

DNR

Quick Shoot

Monitor Speaker Output

H-Pos.

V-Pos .

Reset

–10 - 0 - +10

–20 - 0 - +20

Yes, No

Off

22

33

Select the position from 1 to 4

Select the position from 1 to 9

Menu Display

Remote

Buttons

Power

RS-232C

Lock, Unlock

Lock, Unlock

Lock, Unlock

Lock, Unlock

Lock, Unlock

Setup

–15 - 0 - +15

–15 - 0 - +15

L 30 - 0 - R 30

Yes, No

Audio

Brightness

Power Management

Input 4 digit numbers

Yes, No

Power

control

Normal, Full 14:9, Zoom 14:9, Panorama, Cinema 14:9, Cinema 16:9, Full, Underscan

Auto, PAL, SECAM, NTSC3.58, NTSC4.43

Off, High, Low

On, Off

On, Off

Option

Treble

Bass

Balance

Reset

AV , Y/C

COMPONENT, RGB *

2

Normal, Mirror, Upside Down, Rotate

Japanese, English, Deutsch, Français, Español

Input, Output

Input numbers from 000 to 255

–8 - 0 - +8

Off, Mode1, Mode2

Attached, Detached

Control Lock

Input Select *

1

Position

Picture Flip

Language

INPUT2 Select *

3

ID No. Setting

Enlarge

Panel Protection Cover

Menu option reference chart: AV input mode

*1 This item cannot be chosen if input other than

“INPUT1” or “INPUT3” is selected.

*2 Available only for

“INPUT3”

*3 Not available when

“INPUT2” is selected.

» Depending on the conditions, certain menu items may be displayed in grey. These items cannot be selected.

NOTE:

×

×

LC-M3700
LC-M3710

11

LC-M3700
LC-M3710

DIMENSIONS

Unit: mm

909
810

99.5

66.1

462.8

949

821.6

200

200

36

13

13

12.3

37

65

105265370

6.5

572

12

66.1

24

18.5

223

200

115

142

72.5

188.3

155

38.5

335.8

12

REMOVING OF MAJOR PARTS

SC4101

SC4102

8

10

11

6

7

5

5

9

FPC holder (left)

PC I/F PWB shield

Wire Holder

Monitor PWB shield

FPC holder (right)

Terminal cover B

Terminal cover A

Cabinet B (bottom)

1. Remove the terminal cover.

2. Remove the four lock screws that fix the temporary stand and remove the simple stand.

3. Remove the two lock screws that fix the handle and remove the handle.

4. Remove the 29 lock screws that fix the cabinet B and remove the cabinet B.

5. Remove the seven lock screws that fix the cabinet B (bottom) and remove the cabinet B (bottom).

6. Remove the two lock screws that fix the terminal cover B and remove the terminal cover B.

7. Remove the two lock screws that fix the terminal cover A and remove the terminal cover A.

8. Remove the four lock screws that fix the PC I/F PWB shield and remove the PC I/F PWB shield.

9. Remove the four lock screws that fix the monitor PWB shield and remove the monitor PWB shield.

10. Remove the four lock screws that fix the FPC holder (left) and remove the FPC holder (left).

11. Remove the four lock screws that fix the FPC holder (right) and remove the FPC holder (right).

3

Handle

LC-M3700
LC-M3710

4

2

1

Temporary stand

Terminal cover

4

3

Handle

13

LC-M3700
LC-M3710

12. Disconnect the connectors from each PWB.

13. Remove the two lock screws that fix the key PWB and remove the key PWB.

14. Remove the two lock screws that fix the R/C LED PWB and remove the R/C LED PWB.

15. Remove the two lock screws that fix the speaker-L PWB and remove the speaker-L PWB.

16. Remove the two lock screws that fix the AC inlet PWB and remove the AC inlet PWB.

17. Remove the two lock screws that fix the terminal-1 PWB and remove the terminal-1 PWB.

18. Remove the two lock screws that fix the terminal-2 PWB and remove the terminal-2 PWB.

19. Remove the two lock screws that fix the speaker-R PWB and remove the speaker-R PWB.

20. Remove four lock screws that fix the speaker angle and remove the speaker angle.

SC4601

CN1703

CN1704

CN1701

CN1705

CN3702

CN2702

P7803

P7501

P7506

P7502

P7505

P7503

P7507

P151

12

P7504

P7551

12

P7552

P7554

P7553

P202

P7557

P101

12

CN1702

P7704

CN1706

P2003

CN1707

CN3701

CN4701

12

CN2701

P7802

P7707

P2004

CN9

CN8

P1101

12

SC4602 SC4604

12

12

CN11

CN1

SC1103

CN2001

P7705

P2005

SC4603

P1501

P1504

SC2405

P7611

P7616

P7615

P7612

P2508

P2302

P7649

P2301

P7618

P7644

P7647

P7613

12

P7614

P7641

12

P7642

P7643

P202

P1801

12

P1507

SC1506

P1505

SC2406

20

Speaker angle

13

Key PWB

R/C LED PWB

14

Speaker-LPWB

AC inlet PWB

15

16

17

Terminal-1 PWB

14

Terminal-2 PWB

18

Speaker-R PWB

19

LC-M3700
LC-M3710

21. Remove the inverter-3 PWB.

22. Remove the three lock screws that fix the inverter-4 PWB and remove the inverter-4 PWB.

23. Remove the four lock screws that fix the main PWB and remove the main PWB.

24. Remove the four lock screws that fix the monitor PWB and remove the monitor PWB and monitor PWB angle.

25. Remove the two lock screws that fix the PC I/F PWB and remove the PC I/F PWB.

26. Remove the four lock screws that fix the DC/DC PWB and remove the DC/DC PWB.

27. Remove the one lock screw that fixes the holder B assembly and remove the holder B assembly.

28. Remove the one lock screw that fixes the holder A assembly and remove the holder A assembly.

29. Remove the inverter-1 PWB.

30. Remove the one lock screw that fixes the inverter 2 PWB and remove the inverter-2 PWB.

Holder A assembly

28

29

Inverter-1 PWB

Holder B assembly

27

DC/DC PWB

26

PC I/F PWB

25

PC I/F PWB
angle

Monitor PWB

21

Inverter-3 PWB

24

Monitor PWB angle

30

Inverter-2 PWB

22

Inverter-4 PWB

Main PWB

Power PWB

23

31

15

LC-M3700
LC-M3710

» Cautions in handling the liquid crystal panel

1. Handle the liquid crystal panel in a clean room (Humidity: 50% or more).

2. The operator should wear an earth band without fail.

3. Take care not to give an impact (dropping, vibrating, etc.) to the liquid crystal panel

4. Use an ionizer (within 30 cm).

32. Remove the five lock screws that fix the liquid crystal panel and remove the liquid crystal panel unit.

33. Remove the three lock screws that fix each sheet-fixing angle and remove each sheet-fixing angle.

34. Remove the reflection/shade sheet, prism sheet, diffusion sheet and diffusion plate.

35. Remove the three lock screws that fix each lamp holder (upper, lower) and remove each lamp holder (upper,
lower).

36. Remove the lamp assembly from the lamp clip.

Lamp holder (upper)

Sheet-fixing angle

33

32

35

34

33

Sheet-fixing angle

Lamp holder (lower)

Lamp unit

36

Diffusion plate

Diffusion plate

Prism sheet

Reflection/shade sheet

Back shield

35

Lamp holder (lower)

Lamp holder (upper)

16

LC-M3700
LC-M3710

ADJUSTING PROCEDURE OF EACH SECTION

[How to enter the process adjustment mode]

Caution:Take great care not to allow the customer to know the method of entering the process

adjustment mode described below. If the setting in the process adjustment mode is changed
indiscriminately, an unrecoverable error may be caused.

<Main process>

1) Using the remote control or main body switch, put the unit in a standby state. (The power LED is "Red".)

2) Press the "MAIN POWER" button to turn off the power.

3) Press the "POWER" button on the display section to turn off the power.

4) While pressing the "INPUT" and "MENU" keys on the main body side together, press the "MAIN POWER"
switch on the main body to turn on the power.
If a display such as "1/16" and "N358" is shown in blue characters on one line at the top of the screen several
seconds later, the process adjustment mode has been entered. Pressing any of the cursor UP/DOWN/LEFT/
RIGHT keys will display the process adjustment items.
If you fail to enter the process adjustment mode (the same display as in the case of normal startup appears),
repeat the above-described steps again.

<Monitor process>

1) Using the remote control or main body switch, put the unit in a standby state. (The power LED is "Red".)

2) Press the "MAIN POWER" button to turn off the power.

3) Press the "POWER" button on the display section to turn off the power.

4) While pressing the "INPUT" and "UP" keys on the main body side together, press the "MAIN POWER" switch
on the main body to turn on the power.
It is also possible to enter the monitor process mode by setting "KOUTEI CHANGR" on the last line of the first
page of the main process mode to MONITOR with the VOL +/- key and pressing the ENTER key. To switch
from the monitor process mode to the main process mode, set "KOUTEI CHANGR" on the last line of the first
page of the monitor process mode to MAIN and press the ENTER key.

17

LC-M3700
LC-M3710

[Key operation]
MENU: Used to move up by one line.
RETURN: Used to move down by one line.
VOL +/-: Used to change the setting on the selected line (+1/-1).
Cursor UP/DOWN: Used to scroll by page (Previous/Next).
Cursor RIGHT/LEFT: Used to change the setting on the selected line (+10/-10).
INPUT: Used to change the input (INPUT1→ INPUT2→ INPUT3→ PC).
ENTER: Used to execute the function.

[Reading of process adjustment values]
The adjustment values set at the factory before shipping are stored on the main PWB of this unit (not covering all
the items in the process menu). In repairing the unit, if the problem is solved only by replacing the PCI/F unit, you
can read the stored adjustment values and therefore all you do is to adjust some items only.

• How to read the stored ex-factory adjustment values (backup data)
Select (page7) EEPROM RECOVER, set it from "OFF" to "ON" with the "VOL" key, and then press the "ENTER"
key. If "error" is displayed, you have failed to read the data and therefore have to adjust all the items.

• Adjustments required after reading the stored ex-factory adjustment values (when the data is read successfully)

Ë+Badj3.3V reference voltage adjustment
Ë+Badj1.8V important component operating voltage adjustment (It is adjusted automatically by pressing the

"ENTER" key after 3.3V adjustment above.)

ËN358 WB adjusting white balance adjustment (Video)
ËPAL WB adjusting white balance adjustment (Video)
ËCOMP 15K WB adjusting white balance adjustment (Component 525i)
ËCOMP 33K WB adjusting white balance adjustment (Component hi-vision)

18

[Actual adjustment]

TP4

P802P802P802

11

121212

Before entering the process adjustment mode, reset all the user settings.
(Execute Menu [Video Adjustment]-|[Reset].)

1. Analog adjustment

1) Voltage adjustment
Adjustment item Adjustment condition Adjusting method

LC-M3700
LC-M3710

1 3.3V adjustment page2

+BAdj3.3V
(NTSC color bar received)

2 1.8V adjustment page2

+BAdj1.8V

2) PAL signal adjustment
Adjustment item Adjustment condition Adjusting method

1 Signal input

Connect a voltmeter to TP4 of the PC I/F unit and
adjust the voltage to 3.30±0.01V.

TP4

TP4

If 3.3V adjustment is completed, pressing the ENTER
key on the remote control with the "+BADJ1.8V" line
selected will adjust the voltage automatically. If
"ERR" appears, adjust the voltage to 1.90V using pin
(1) of CN9 of the PC I/F unit.

Using a signal generator, feed PAL split field color
bars (containing 100% white and having color
saturation of 75%) to the video signal input terminal
of INPUT1 or INPUT2.

1 Setting

Set the color system is to PAL by selecting a PAL
source.

2

MAIN PAL Y
gain adjustment

Page3
PAL Y GAIN

Using pin (1) of P802, adjust the gain to

0.70±0.025Vp-p.

19

LC-M3700

0.53Vp-p

0.53Vp-p

LC-M3710

2) PAL signal adjustment
Adjustment item Adjustment condition Adjusting method

3

MAIN PAL color
density adjustment

4

MAIN PAL Cr level adjustment

5

MAIN CONTRAST
adjustment

PAL CB GAIN

CONTRAST 15k

Using pin (3) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

Using pin (5) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

0.53Vp-p

Using the IC8805 output (TP8805), adjust the
contrast to 0.90±0.025Vp-p above the pedestal.

TP8805TP8805

3) SECAM signal adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed SECAM split field

color bars (containing 100% white and having color
saturation of 75%) to the video signal input terminal
of INPUT1 or INPUT2.

Setting Set the color system to SECAM.

1

SECAM Y gain

2 Page4

adjustment

SECAM color density

3 Page4

adjustment

SECAM Y GAIN

SECAM CB GAIN

Using pin (1) of P802, adjust the gain to

0.70±0.025Vp-p.

Using pin (3) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

20

0.53Vp-p

3) SECAM signal adjustment
Adjustment item Adjustment condition Adjusting method

LC-M3700
LC-M3710

4 MAIN SECAM Cr level SECAM CR GAIN

adjustment

Using pin (5) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

0.53Vp-p

4) N358 signal adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed NTSC3.58 split field

color bars (containing 100% white and having color
saturation of 75%) to the video signal input terminal
of INPUT1 or INPUT2.

Setting Set the color system to N358.

1

MAIN N358 Y gain

2 page 5

adjustment

N358 Y GAIN

Using pin (1) of P802, adjust the gain to

0.70±0.025Vp-p.

MAIN N358 color

3 N358 CB GAIN

density adjustment

MAIN N358 Cr level

4 N358 CR GAIN

adjustment

MAIN N358 TINT

5 N358 TINT

adjustment

Using pin (3) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

Using pin (5) of P802, make adjustment so that the
interval indicated in the figure below becomes

0.53±0.025Vp-p.

0.53Vp-p

Using the TB124_MAIN output (P802-3pin), make
adjustment so that the bottoms of waveforms are
aligned as shown in the figure below.

Should be aligned like this.

21

LC-M3700
LC-M3710

5) Component 15kHz signal adjustment
Adjustment item Adjustment condition Adjusting method

Signal input

1 Setting

2 MAIN component 15K Page 6

CONTRAST adjustment COMP 15k (CONTRAST)

6) Component HDTV signal adjustment
Adjustment item Adjustment condition Adjusting method

Signal input

1 Setting

Using a signal generator, feed component 15K full
field color bars (containing 100% white and having
color saturation of 100%) to the component video
signal input terminal of INPUT3.

et to component 15kHz.

Using IC8805 (TP8805), adjust the contrast to

0.90±0.025Vp-p.

Using a signal generator, feed component 33K
(HDTV1080i) full field color bars (containing 100%
white and having color saturation of 100%) to the
component video signal input terminal of INPUT3.

Set to component 33kHz.

2 MAIN component HDTV Page 6

CONTRAST adjustment COMP HD CONTRAST

Using IC8805 (TP8805), adjust the 100% white to

0.90±0.025Vp-p above the pedestal.

22

2. Analog adjustment

1) N358 white balance adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed NTSC signal window

patterns (in-window 20IRE) to the video input
terminal of INPUT1.

20IRE

LC-M3700
LC-M3710

1 Setting
2 R CUTOFF adjustment Page7

N358 R CUTOFF

Set the color system to N358.

1. On the R CUTOFF item, press the ENTER key to
display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

3 G CUTOFF adjustment N358 G CUTOFF 1. On the G CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

4 B CUTOFF adjustment N358 B CUTOFF 1. On the B CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

5 Setting Set the window white level of the window pattern

from the signal generator to 80IRE.

80IRE

6 R DRIVE adjustment N358 R DRIVE 1. On the R DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

7 G DRIVE adjustment N358 G DRIVE 1. On the G DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

8 B DRIVE adjustment N358 B DRIVE 1. On the B DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

9 Setting On the item, press the ENTER key again to make the

special gamma disappear.

After performing steps 1 to 3 and 6 to 8, repeat adjustment so that the color becomes brightest for both 20IRE and 80IRE.

23

LC-M3700
LC-M3710

2) PAL white balance adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed NTSC signal window

patterns (in-window 20IRE) to the video input
terminal of INPUT1.

20IRE

1 Setting

2 R CUTOFF adjustment Page8

PAL R CUTOFF

Set the color system to PAL.

1. On the R CUTOFF item, press the ENTER key to
display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

3 G CUTOFF adjustment PAL G CUTOFF 1. On the G CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

4 B CUTOFF adjustment PAL B CUTOFF 1. On the B CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

5 Setting Change the ion-window white level of the window

pattern from the signal generator to 80IRE.

80IRE

6 R DRIVE adjustment PAL R DRIVE 1. On the R DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

7 G DRIVE adjustment PAL G DRIVE 1. On the G DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

8 B DRIVE adjustment PAL B DRIVE 1. On the B DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

9 Setting On the item, press the ENTER key again to make the

special gamma disappear.

After performing steps 1 to 3 and 6 to 8, repeat adjustment so that the color becomes brightest for both 20IRE and 80IRE.

24

3) Component 15K white balance adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed component 15K signal

(525i) window patterns (in-window 20IRE) to the
video input terminal of INPUT3. Y input only is
sufficient.

20IRE

LC-M3700
LC-M3710

1 Setting
2 R CUTOFF adjustment Page9

COMP 15k R CUTOFF

Set the input to INPUT3 component.

1. On the R CUTOFF item, press the ENTER key to
display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

3 G CUTOFF adjustment COMP 15k G CUTOFF 1. On the G CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

4 B CUTOFF adjustment COMP 15k B CUTOFF 1. On the B CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

5 Setting Change the in-window white level of the window

pattern from the signal generator to 80IRE.

80IRE

6 R DRIVE adjustment COMP 15k R DRIVE 1. On the R DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

7 G DRIVE adjustment COMP 15k G DRIVE 1. On the G DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

8 B DRIVE adjustment COMP 15k B DRIVE 1. On the B DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

9 Setting On the item, press the ENTER key again to make the

special gamma disappear.

After performing steps 1 to 3 and 6 to 8, repeat adjustment so that the color becomes brightest for both 20IRE and 80IRE.

25

LC-M3700

E

E

LC-M3710

4) Component 33K white balance adjustment
Adjustment item Adjustment condition Adjusting method

Signal input Using a signal generator, feed component 33K signal

(1080i) window patterns (in-window 20IRE) to the
video input terminal of INPUT3. Y input only is
sufficient.

20IR

1 Setting
2 R CUTOFF adjustment Page10

COMP HDTV R CUTOFF

Set the input to INPUT3 component.

1. On the R CUTOFF item, press the ENTER key to
display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

3 G CUTOFF adjustment COMP HDTV G CUTOFF 1. On the G CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

4 B CUTOFF adjustment COMP HDTV B CUTOFF 1. On the B CUTOFF item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

5 Setting Change the in-window white level of the window

pattern from the signal generator to 80IRE.

80IR

6 R DRIVE adjustment COMP HDTV R DRIVE 1. On the R DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

7 G DRIVE adjustment COMP HDTV G DRIVE 1. On the G DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

8 B DRIVE adjustment COMP HDTV B DRIVE 1. On the B DRIVE item, press the ENTER key to

display the special gamma.

2. Adjust the value so that the color in the window
becomes brightest.

9 Setting On the item, press the ENTER key again to make the

special gamma disappear.

After performing steps 1 to 3 and 6 to 8, repeat adjustment so that the color becomes brightest for both 20IRE and 80IRE.

26

3. Monitor section adjustment
Analog adjustment

1) Voltage adjustment
Adjustment item Adjustment condition Adjusting method

LC-M3700
LC-M3710

Using a signal generator, feed NTSC signal color
bars to the video input terminal of INPUT1.

1 Setting

2 VLS BIAS adjustment Monitor process

adjustment mode
Page2

3 GRAY LEVEL Monitor process

adjustment adjustment mode

Page2

4 COM BIAS adjustment Monitor process

adjustment mode
Page2

1. Set the input to INPUT1.

2. Enter the process adjustment mode, set the
KOUTEI CHANGR item on Page 1 to MONITOR
with the VOL key and press the ENTER key.

3. The monitor process adjustment mode is
established.

Connect a digital voltmeter to TL4103 (A-side) or
TL4103 (B-side) and adjust the VLS bias to

15.00V±0.05V.

Connect a digital voltmeter to TL4102 (A-side) or
TL4101 (B-side) and adjust the gray level to

14.50V±0.05V.

1. On the COM BIAS item, press the ENTER key to
display the adjustment pattern.

2. Set the value so that the flicker near the center of
the screen is minimized.

3. Press the ENTER key to make the pattern
disappear.

27

LC-M3700
LC-M3710

2) Monitor white balance adjustment (15k)
~ All the video adjustments on the MAIN side should be completed before making this adjustment.

Adjustment item Adjustment condition Adjusting method

Signal input

Using a signal generator, feed composite signal
(NTSC) raster patterns (20IRE) to the video input
terminal of INPUT1.

20IRE

1 Setting

1. [Video Adjustment]-[Reset] execution

2. [Energy-Saving Setting]-Brightness [+8]

3. [Video Adjustment]-[Pro Setting]-[Color
Temperature]-Middle

4. [Video Adjustment]-[Pro Setting]-[Black Extension]­OFF

2 Adjustment Page14 Using a color meter, adjust R GAMMA 15K (LO) and

B GAMMA 15K (LO) to x=0.287, y=0.285±0.0035
(Measure the central part of the screen.)

3 Setting Using a signal generator, feed composite signal

(NTSC) raster patterns (80IRE) to the video input
terminal of INPUT1.

80IRE

4 Adjustment Page14 Using a color meter, adjust R GAMMA 15K (HI) and

B GAMMA 15K (HI) to x=0.287, y=0.285±0.0015
(Measure the central part of the screen.)

5 Adjustment Page14 Change the WRITE GAMMA 15K item from OFF to

ON with the VOL key and press the ENTER key.
(Execution of writing of the adjusted values.)

28

3) Monitor white balance adjustment (HDTV)
~ All the video adjustments on the MAIN side should be completed before making this adjustment.

Adjustment item Adjustment condition Adjusting method

LC-M3700
LC-M3710

Signal input

1 Setting

2 Adjustment Page14

3 Setting

Using a signal generator, feed component signal
(1080i) raster patterns (20IRE) to the video input
terminal of INPUT3. Y input only is sufficient.

20IRE

1. [Video Adjustment]-[Reset] execution

2. [Energy-Saving Setting]-Brightness [+8]

3. [Video Adjustment]-[Pro Setting]-[Color
Temperature]-Middle

4. [Video Adjustment]-[Pro Setting]-[Black
Extension]-OFF

Using a color meter, adjust R GAMMA (LO) and B
GAMMA (LO) to x=0.287, y=0.285±0.0035
(Measure the central part of the screen.)

Using a signal generator, feed component signal
(1080i) raster patterns (80IRE) to the video input
terminal of INPUT3.

4 Adjustment Page14

5 Adjustment Page14

4. Factory settings
Adjustment item Adjustment condition Adjusting method

1 Settings
2 Factory settings Page1

80IRE

Using a color meter, adjust R GAMMA (HI) and B
GAMMA (HI) to x=0.287, y=0.285±0.0015
(Measure the central part of the screen.)

Change the WRITE GAMMA HDTV item from
OFF to ON with the VOL key and press the
ENTER key.
(Execution of writing of the adjusted values.)

Enter the process adjustment mode.
Set the INDUSTRY INIT item to ON with the VOL

+/- key and press the ENTER key.

2. When the process mode is exited and the input
is set to INPUT1, factory setting has been
completed.

3. Turn OFF the main power.

Items initialized through factory setting

• EUser adjustment value

• EPassword

• EAccumulated operating time (main side only)

• EID number

29

LC-M3700
LC-M3710

HOW TO UPGRADE THE INTERNAL PROGRAM

The program used in this unit is divided into the following two programs, which are rewritten by different methods.

• Main program

• Monitor program

[How to enter the process adjustment mode]

Caution:Take great care not to allow the customer to know the method of entering the process

adjustment mode described below. If the setting in the process adjustment mode is changed
indiscriminately, an unrecoverable error may be caused.

<Main process>

1) Plug the power cord in the wall outlet.

2) Press the "MAIN POWER" button to turn off the power.

3) While pressing the "INPUT" and "MENU" buttons together, press the "MAIN POWER" button to turn on the
power.
(Keep pressing the "INPUT" and "MENU" buttons until a display appears.)

If "1/16" is displayed in blue characters on the screen several seconds later, the process adjustment mode has
been entered. Pressing any of the cursor UP/DOWN/LEFT/RIGHT keys will display the 1st page of the process
adjustment mode.
If you fail to enter the process adjustment mode (the same display as in the case of normal startup appears),
repeat the above-described steps again.

[Necessary devices]

• Personal computer
Personal computer equipped with Windows 95/98/me/2000/xp
Personal computer with a COM port (RS-232C). An USB-RS232C converter may be used depending on the
setting, but consider the compatibility.

• RS-232C scroll cable
"Interlink cable" can be used.

[Preparations]

1) Software for rewriting is provided as an executable file having a name such as "MAIN_2002_10_10A.exe"

(tentative name). Create a directory with an appropriate name on the hard disc of the PC to be used for
rewriting and copy the software to it.

2) When this file is double-clicked on Windows, decompressing the compressed file is started. Carefully check

if the contents of the decompressed file correspond to the documentation attached to the program.

3) Using the RS-232C cable, connect the personal computer with the main body.

4) Enter the process adjustment mode according to "How to enter the process adjustment mode" described

above.

30

LC-M3700
LC-M3710

[How to rewrite the main program]

1) After entering the process adjustment mode, proceed to page 16 using the ÅgDOWNÅh key on the remote
control or main body ("16/16" is displayed on the upper-left corner).

2) Select "CENTER PROG UPDATE" with the "MENU" or "RETURN" key on the remote control.

3) Change "CENTER PROG UPDATE" from "OFF" to "ON" with the "VOL (+)/(-)" on the remote control.

4) Press the "ENTER" key on the remote control. The characters displayed on the screen disappear and the
screen becomes black.

5) Double-clock the decompressed batch file (specified by the attached documentation) in the directory on the
PC.

6) A black window (MS-DOS window) opens on the screen and writing is started automatically.
After a short time, "OK, Received successfully" is displayed on the screen.
Rewriting of the main program has been completed. Unplug the power cord to turn off the power and then turn
it on again.

7) For confirmation, enter the process adjustment mode again and check that the version information shown on
the lines "CENTER Version", "OSD version" and "CVIC Version" on the 1st page corresponds to the new
version shown on the attached documentation.

31

LC-M3700
LC-M3710

[How to rewrite the monitor program]

1) After entering the process adjustment mode, start up the terminal software obtained separately.
(Freeware products available on the Internet can be used.)

2) Make setting as shown below.
Baud rate: 9600
Data: 8 bits
Parity: NONE
Stop: 1 bit
Flow control: NONE

3) If the above setting is made correctly, pressing the ÅgENTERÅh key on the PC will make ÅgERRÅh appear on
the terminal software.

4) In this state, type the following. ( means the ENTER key.)
The characters displayed on the screen disappear and the screen becomes black.
IPL_0002

~ Immediately after the above entry, an unusual display may be appear on the terminal software, which means no

abnormal condition.

32

LC-M3700
LC-M3710

5) Change the baud rate to 115200.

6) Press the ÅgENTERÅh key to make appear the following display
ERR
SEND "MONITOR PROG UPDATE PROGRAM" from PC to MR

7) Using the file transmission function (function to transmit specified file contents) of the terminal software, select
the decompressed file (specified by the attached documentation) in the directory on the PC and execute
transmission.

8) When the following display appears on the terminal software, rewriting of the monitor program has been
completed. (Its contents may vary depending on the terminal software or program.)
Unplug the power cord to turn off the power and then turn it on again.

9) For confirmation, enter the process adjustment mode again and check that the version information shown on
the line "Monitor Version" on the 1st page corresponds to the new version shown on the attached documentation.

33

LC-M3700
LC-M3710

DESCRIPTION OF FUNCTION OF MAJOR ICs

• IC4701 (IXA332WJ)
This IC is a QS driver for EVEN.
It QS (Quick Shoot)-drives the input signal sent from the DVI receiver according to the temperature parameter
setting from the monitor microcomputer.

• EIC4901 (IXA332WJ)
This IC is a QS driver for ODD.
It QS (Quick Shoot)-drives the input signal sent from the DVI receiver according to the temperature parameter
setting from the monitor microcomputer. In addition, after QS-driving the H and V synchronization signal and
DE signal sent from the DVI receiver, it outputs the H and V synchronization signal and DE signal.

• EIC4501 (IXA457WJ)
This IC is a liquid crystal controller.
It allocate the video data of the 24-bit RGB signal, H and V synchronization signal and DE signal sent from the
QS driver (ODD and EVEN) to the left-side ODD and EVEN and the right-side ODD and EVEN of the liquid
crystal panel and outputs the control signal for driving the liquid crystal panel. It also generates the control
signal for dimmer control.

• EIC4303 (IXA345WJ)
This IC is a CPLD.
Because the QS driver and liquid crystal controller are general-purpose FPGAs, it is used to make setting for
each FPGA. After resetting, it reads the program data from IC4301 (flash) and makes setting for each IC
through serial transmission.

• EIC4105 (IXA350WJ)
This IC is a gray scale reference power for TFT liquid crystal. It incorporates ten circuits of gray scale output
buffer amp, a CMOS buffer amp and a reference voltage supply.

• EIC2004 (IXA3491CE)
This IC is a monitor microcomputer. It performs OSD control of the monitor section, detection of the panel
temperature through the thermistor, setting of the temperature parameter for the OS driver, setting of the timing
for the liquid crystal controller, setting of the dimmer control data, power control of the monitor section, monitoring
of each power line, remote control decoding and OPC control.

34

LC-M3700

Ë

VHiTFP501++-1Q (ASSY:IC1104)

Panel Bus HDCP DIGITAL RECEIVER

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

79 AGND — Analog ground—Ground reference and current return for analog circuitry.

79 AGND — Analog ground—Ground reference and current return for analog circuitry.

82,85,88,91 AVDD — Analog VDD—Power supply for analog circuitry. Nominally 3.3V.

67 CAP O

Bypass capacitorÅ\4.7 _F tantalum and 0.01 _F ceramic capacitors connected to ground.

41,40 CTL[2:1] O General purpose control signals—Used for user defined control. In normal mode

CTL1 is not powered down via PDO.

94 DDC_SA 1 Display data channel_serial address—I2C Slave address bit A0 for display data

channel (DDC). Refer to I2C Interface section for more details.

92 DDC_SCL I/O Display data channel_serial clock—I2C Clock for the DDC. External pullup

resistors = 10 k_ and 3.3V to lerant.

93 DDC_SDA I/O Display data channel_serial data—I2C Data for the DDC. External pullup

resistors = 10 k_ and 3.3V to lerant.

46 DE O Output data enable—Used to indicate time of active video display versus

nonactive display or blanking interval. During blanking, only HSYNC, VSYNC

and CTL1_2 are transmitted. During times of active display, or nonblanking,

only pixel data, QE[23:0] and QO[23:0], is transmitted.

High: active display interval

Low: blanking interval

1 DFO I Output clock data format—Controls the output clock (ODCK) format for either

TFT or DSTN panel support. For TFT support ODCK clock runs continuously.

For DSTN support ODCK only clocks when DE is high; otherwise, ODCK is held

low when DE is low.

High: DSTN support/ODCK held low when DE = low.

Low: TFT support/ODCK runs continuously.

5, 39, 68 DGND — Digital ground—Ground reference and current return for digital core.

6, 38 DVDD Digital VDD—Power supply for digital core. Nominally 3.3V.

48 HSYNC O Horizontal sync output

100 OCK_INV I ODCK Polarity _ Selects ODCK edge on which pixel data (QE[23:0] and QO

[23:0]) and control signals(HSYNC, VSYNC, DE, CTL1_2 ) are latched.

Normal mode:

High: latches output data on rising ODCK edge.

Low: latches output data on falling ODCK edge.

44 ODCK O Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0]

(if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC and CTL[2:1] are

synchronized to this clock.

19, 28,45, 58,76 OGND —

Output driver ground—Ground reference and current return for digital output drivers.

18, 29,43, 57,78 OVDD — Output driver VDD—Power supply for output drivers. Nominally 3.3V.

2 PD I Power down—An active low signal that controls the TFP501 power-down state.

During power down all output buffers are switched to a high-impedance state

and brought low through a weak pulldown. All analog circuits are powered down

and all inputs are disabled, except for PD.

If PD is left unconnected, an internal pullup defaults the TFP501 to normal operation.

High: normal operation

Low: power down

9 PDO I Output drive power down—An active low signal that controls the power-down

state of the output drivers.

During output drive power down, the output drivers (except SCDT and CTL1) are

driven to a high-impedance state. A weak pulldown slowly pulls these outputs to

a low level. When PDO is left unconnected an internal pullup defaults the

TFP501 to normal operation.

High: normal operation/output drivers on.

Low: output drive power down.

98 PGND — PLL ground _ Ground reference and current return for internal PLL.

4 PIXS I Pixel select—Selects between one or two pixel per clock output modes. During

2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are

output in tandem on a given clock cycle. During 1 pixel/clock, even and odd

pixels are output sequentially, one at a time, with the even pixel first, on the

even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The

second pixel per line is pixel-1, the odd pixel.)

High: 2 pixel/clock

Low: 1 pixel/clock

95 PROM_SCL I/O EEPROM_serial clock—I2C clock for EEPROM interface data. External pullup

resistors = 10 k_ and 3.3V to lerant.

96 PROM_SDA I/O EEPROM_serial data—I2C data for EEPROM interface data. External pullup

resistors = 10 k_ and 3.3V to lerant.

97, 99 PVDD (1, 2) PLL VDD—Power supply for internal PLL. Nominally 3.3V.

LC-M3710

35-2

35

35-1

LC-M3700

10_17 QE[0:7] O Even blue pixel output

—Output for even and odd blue pixels when in 1-pixel/

clock mode. Output for even only blue pixel when in 2-pixel/clock mode. Output

data is synchronized to the output data clock, ODCK.

LSB: QE0/pin 10

MSB: QE7/pin 17

20_27 QE[8:15] O Even green pixel output

—Output for even and odd green pixels when in 1-pixel/

clock mode. Output for even only green pixel when in 2-pixel/clock mode.

Output data is synchronized to the output data clock, ODCK.

LSB: QE8/pin 20

MSB: QE15/pin 27

30_37 QE[16:23] O Even red pixel output

—Output for even and odd red pixels when in 1-pixel/clock

mode. Output for even only red pixel when in 2-pixel/clock mode. Output data is

synchronized to the output data clock, ODCK.

LSB: QE16/pin 30

MSB: QE23/pin 37

49_56 QO[0:7] O Odd blue pixel output

—Output for odd only blue pixel when in 2-pixel/clock

mode. Not used, and held low, when in 1-pixel/clock mode. Output data is

synchronized to the output data clock, ODCK.

LSB: QO0/pin 49

MSB: QO7/pin 56

59_66 QO[8:15] O Odd green pixel output

—Output for odd only green pixel when in 2-pixel/clock

mode. Not used, and held low, when in 1-pixel/clock mode. Output data is

synchronized to the output data clock, ODCK.

LSB: QO8/pin 59

MSB: QO15/pin 66

69_75,77 QO[16:23] O Odd red pixel output

—Output for odd only red pixel when in 2-pixel/clock mode.

Not used, and held low, when in 1-pixel/clock mode. Output data is

synchronized to the output data clock, ODCK.

LSB: QO16/pin 69

MSB: QO23/pin 77

42 RSVD O Reserved—Must be tied high for normal operation.

80 Rx2+ I Channel-2 positive receiver input Positive side of channel-2 T.M.D.S. low

voltage signal differential input pair.

Channel-2 receives red pixel data in active display and CTL2 control signal

during blanking.

81 Rx2_ I Channel-2 negative receiver input

—Negative side of channel-2 T.M.D.S. low

voltage signal differential input pair.

83 Rx1+ I Channel-1 positive receiver input

—Positive side of channel-1 T.M.D.S. low

voltage signal differential input pair. Channel_1 receives green pixel data in

active display and CTL1 control signal during blanking.

84 Rx1_ I Channel-1 negative receiver input

—Negative side of channel-1 T.M.D.S. low

voltage signal differential input pair.

86 Rx0+ I Channel-0 positive receiver input

—Positive side of channel-0 T.M.D.S. low

voltage signal differential input pair. Channel-0 receives blue pixel data in active

display and HSYNC, VSYNC control signals during blanking.

87 Rx0_ I Channel-0 negative receiver input

—Negative side of channel-0 T.M.D.S. low

voltage signal differential input pair.

89 Rx0+ I Clock positive receiver input

—Positive side of reference clock T.M.D.S. low

voltage signal differential input pair.

90 RxC_ I Clock negative receiver input

—Negative side of reference clock T.M.D.S. low

voltage signal differential input pair.

8 SCDT O Sync detect _ Output to signal when the link is active or inactive. The link is

considered to be active when DE is actively switching. The TFP501 monitors the

state DE to determine link activity. SCDT can be tied externally to PDO to

power down the output drivers when the link is inactive.

High: active link

Low: inactive link

3 ST I Output drive strength select

—Selects output drive strength for high or low

current drive. (see dc specifications for IOH and IOL vs ST state.)

High: high drive strength

Low: low drive strength

7 STAG I Staggered pixel select _ An active low signal used in 2 pixel/clock pixel mode

(PIXS = high). Time staggers the even and odd pixel outputs to reduce ground

bounce. Normal operation outputs the odd and even pixels simultaneously.

High: normal simultaneous even/odd pixel output.

Low: time staggered even/odd pixel output.

47 VSYNC O Vertical sync output

Pin No. Pin Name I/O Pin Function

Ë

VHiCXA2171Q-1Q (ASSY:IC8801)

Video/Sync Selector

»Block Diagram

LC-M3710

36-2

36

36-1

LC-M3700

»Pin Function

Pin No. Pin Name I/O Pin Function

1 IN3_1 I IN3 system signal input terminals.

2 IN3_2 I Please input through a capacitor.

3 IN3_3 I Bias of the terminal voltage is carried out to 2.9V.

An input Y level should give me 0.7Vp-p and a composit input level as 0.7Vp-p

with a color bar 100%.

In Sync on Y and Sync on Green, please input a Sync level by 0.3 Vp-p.

IN3_1 : Cr/Cb/R signal input

IN3_2 : Cb/Pb/B signal input

IN3_3 : Y/YHD/G signal input

4 IN3_H I IN3_H : They are an self-support H synchronization or the input terminal of CS.

5 IN3_V I IN3_V : It is the input terminal of an self-support V synchronized signal.

Please input through the capacitor for a clamp. A bottom level is clamped by 1V.

Corresponds to positive/negative two-poles nature.

Please input an input on the level shown below.

0.4Vp-p < IN3_H < 4Vp-p

0.4Vp-p < IN3_V <4Vp-p

6 GND3 — GND of a synchronized signal system.

7 IN4_1 I IN4 system signal input terminals.

8 IN4_2 I Please input through a capacitor.

9 IN4_3 I Bias of the terminal voltage is carried out to 2.9V.

An input Y level should give me 0.7Vp-p and a composit input level as 0.7Vp-p

with a color bar 100%.

In Sync on Y and Sync on Green, please input a Sync level by 0.3 Vp-p.

IN4_1 : Cr/Cb/R signal input

IN4_2 : Cb/Pb/B signal input

IN4_3 : Y/YHD/G signal input

10 IN4_H I IN4_H : They are an self-support H synchronization or the input terminal of CS.

11 IN4_V I IN4_V : It is the input terminal of an self-support V synchronized signal.

Please input through the capacitor for a clamp. A bottom level is clamped by 1V.

Corresponds to positive/negative two-poles nature.

Please input an input on the level shown below.

0.4Vp-p < IN4_H < 4Vp-p

0.4Vp-p < IN4_V < 4Vp-p

12 VCC3 — Power supply terminal of a synchronized signal system.

13 H_PH Capacitor connection terminal for carrying out the peak hold of the Hsync.

14 V_PH Capacitor connection terminal for carrying out the peak hold of the Vsync.

15 YG_OUT O Composite Video signal output terminal for synchronous separation.

About 6dB of signals chosen by I2C bus "HYSW" is amplified, and they are

outputted.

16 YG_IN I Composite Video signal input terminal for synchronous separation.

Usually, the signal outputted by 15 pins is inputted through a clamp capacitor.

Sync Tip is clamped by 2.3V. Please input a Sync level by 0.5 - 0.6 Vp-p.

17 CLP_SW I

Input terminal of the pulse which switches clamp circuit operation of Y signal system.

18 IREF

Reference current setting terminal in IC (synchronized signal processing system).

Please connect resistance 10kohm of less than 1% of errors to opposite GND

(metal leather film resistance etc.). Terminal voltage is about 1V.

19 NC — No connect

20 EXTCLK/XTAL Reference clock change terminal for synchronous counters.

When using Inside VCO, it is set as I2C bus "CLK_SEL=0" and a 4MHz X'tal

oscillation element or a ceramic oscillation element is connected. When you

input the 4MHz clock of external, please set it as I2C bus "CLK_SEL=1."

21 NC — No connect

22 SELH_OUT O HV output terminal of selectors IN1-IN4.

VOH < 3.5V

23 SELV_OUT O VOL < 0.5V

24 GND2 — GND terminal of a picture signal system.

25 SELCR_OUT O Output terminal of selectors IN1-IN4. The signal by which YCbCr conversion

was carried out is outputted.

An output level is outputted by 6dB of an input level, when it is set as I2C bus

"GAIN_SEL=0."

26 SELCB_OUT O

27 SELY_OUT O

28 VCC2 — Power supply terminal of a picture signal system.

29 CLP_CR It is a constant terminal at the time of a diode clamp.

The minimum potential of a signal is clamped to 1.4V.

30 SCL I SCL (Serial Clock) input terminal of I2C bus reference.

31 SDA I SDA (Serial Data) input terminal of I2C bus reference.

32 ADDRESS slave address setting terminal of I2C bus.

8Eh : More than 4V

8Ch : Open

84h : Less than 1.5V

33 IN1_1 I IN1 system signal input terminals.

34 IN1_2 I Please input through a capacitor.

35 IN1_3 I Bias of the terminal voltage is carried out to 2.9V.

An input Y level should give me 0.7Vp-p and a composit input level as 0.7Vp-p

with a color bar 100%.

In Sync on Y and Sync on Green, please input a Sync level by 0.3 Vp-p.

IN1_1 : Cr/Cb/R signal input

IN1_2 : Cb/Pb/B signal input

IN1_3 : Y/YHD/G signal input

36 IN1_H/L1 I IN1_H : They are an self-support H synchronization or the input terminal of CS.

37 IN1_V/L2 I IN1_V : It is the input terminal of an self-support V synchronized signal.

Please input through the capacitor for a clamp. A bottom level is clamped by 1V.

Corresponds to positive/negative two-poles nature.

Please input an input on the level shown below.

0.4Vp-p < IN1_H < 4Vp-p

0.4Vp-p < IN1_V < 4Vp-p

Moreover, when it is set as I2 C bus "SELSTB_1=1", it becomes the input

terminal of the control lines 1 and 2 of D3 terminal. DC level of an input is

returned to status register "DECL1_1" and "DECL 2_1" by Three values.

38 IN1_L3 I Input terminal of the control line 3 of D3 terminal.

When it is set as I2C bus "SELSTB_1=1", Return DC level of an input to status

register "DECL3_1" with three values.

39 IN1_SW I Input terminal of the control line 3 of D3 terminal.

When it is set as I2C bus "SELSTB_1=1", Return DC level of an input to status

register "DECL3_1" with two values.

40 VCC1 — Power supply terminal of an input selector.

41 IN2_1 I IN2 system signal input terminals.

42 IN2_2 I Please input through a capacitor.

43 IN2_3 I Bias of the terminal voltage is carried out to 2.9V.

An input Y level should give me 0.7Vp-p and a composit input level as 0.7Vp-p

with a color bar 100%.

In Sync on Y and Sync on Green, please input a Sync level by 0.3 Vp-p.

IN2_1 : Cr/Cb/R signal input

IN2_2 : Cb/Pb/B signal input

IN2_3 : Y/YHD/G signal input

44 IN2_H/L1 I IN2_H : They are an self-support H synchronization or the input terminal of CS.

45 IN2_V/L2 I IN2_V : It is the input terminal of an self-support V synchronized signal.

Please input through the capacitor for a clamp. A bottom level is clamped by 1V.

Corresponds to positive/negative two-poles nature.

Please input an input on the level shown below.

0.4Vp-p < IN2_H < 4Vp-p

0.4Vp-p < IN2_V < 4Vp-p

Moreover, when it is set as I2 C bus "SELSTB_2=1", it becomes the input

terminal of the control lines 1 and 2 of D3 terminal. DC level of an input is

returned to status register "DECL1_2" and "DECL 2_2" by Three values.

46 IN2_L3 I Input terminal of the control line 3 of D3 terminal.

When it is set as I2C bus "SELSTB_2=1", Return DC level of an input to status

register "DECL3_2" with three values.

47 IN2_SW I Input terminal of the switch line of D3 terminal.

When it is set as I2C bus "SELSTB_2=1", Return DC level of an input to status

register "DECSW_2" with two values.

48 GND1 — GND of an input selector.

Pin No. Pin Name I/O Pin Function

LC-M3710

37-2

37

37-1

LC-M3700

Ë

VHiTB1274AF1QE(ASSY:IC801)

VIDEO/CHROMA/SYNC Processor

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

1 CVBS1/Y1-IN I CVBS1 or a Y1-IN signal is inputted.

2 SYNC-IN I Synchronized signal is inputted.

3 CVBS-OUT O Output terminal of CVBS or a Y+C signal.

4 VS O Counted-down vertical synchronized signal is outputted.

5 COMB Y-IN I Y-signal outputted from comb-filter is inputted.It opens, when not using it.

6 D-VDD — Power supply of a DDS/BUS/V-CD/H-CD block is supplied.DC5V (standard)

7 COMB C-IN I C-signal outputted from comb-filter is inputted.It opens, when not using it.

8 D-GND — GND terminal of a DDS/BUS/V-CD/H-CD block.

9 HS O Horizontal synchronized signal which required H-AFC is outputted.

10 SCP O Sand Castle Pulse is outputted. A clamp pulse and a horizontal Blanking pulse

are outputted.

11 Yvi-IN O Y-signal for a synchronous input selected by Video-SW is outputted.

12 SYNC-VCC — Power supply of a SYNC/HVCO block is supplied.DC5V (standard)

13 SCL I SCL terminal of I2CBUS.

14 SDA I/O SDA terminal of I2CBUS.

15 YS3 I Selecte SW of a main signal and RGB1 input signal.

(RGB1-in) Only when [RGB1-ENB] is set as "enable" by bus setup, the input of YS3

becomes effective.

16 SYNC-GND — GND terminal of a SYNC/HVCO block.

17 Cr1-IN I Y1-/Cb1/Cr1 signal is inputted.

18 Cb1-IN I

19 Y1-IN I

20 CLP-FIL — Filter for Y clamp is connected.

21 Y-OUT O Y/Cb/Cr signal is outputted.

22 Cb-OUT O

23 Cr-OUT O

24 YS1 I Selecte SW of a main signal and YCrCb2 input signal.

(YVbC2-IN)

25 B1-IN I RGB1 signal is inputted. This input is selected in YS3 or I2CBUS.

26 G1-IN I

27 R1-IN I

28 Y/C-GND — GND terminal of Y/C/Text/Video-SW / 1HDL block.

29 Cr2-IN I Y2/Cb2/Cr2 signal is inputted. This input is selected in YS1.

30 Cb2-IN I It opens, when not using it.

31 Y2-IN I

32 Y/C-VCC — Power supply of Y/C/Text/Video-SW / 1HDL block is supplied.DC5V (standard)

33 B2-IN I RGB2 signal is inputted. This input is selected in YS2.

It opens, when not using it.

34 G2-IN I

35 R2-IN I

36 YS2/YM I Selecte SW of a main signal and RGB2 input signal.

(RGB2-IN)

37 FIL. — Connects with a Y/C-VCC terminal.

38 X'TAL — 16.2MHz X'tal oscillation element is connected.

39 C3-IN I Chrominance signal is inputted. It opens, when not using it.

40 APC-FIL — Filter for a chrominance demodulater is connected.

41 CVBS3/Y3-IN I CVBS3 or Y3 signal is inputted. It opens, when not using it.

42 ADDRESS I Slave address is set up.

43 C2-IN I Chrominance signal is inputted. It opens, when not using it.

44 CVBS2/Y2-IN I CVBS2 or Y2 signal is inputted. It opens, when not using it.

45 COMB SYS O The distinction result of the received color system is outputted from this terminal

and a terminal 46.

46 Fsc-OUT O Subcarrier is outputted.

47 AFC-FIL — Filter for AFC detection is connected.

48 C1-IN I Chrominance signal is inputted. It opens, when not using it.

LC-M3710

38-2

38

38-1

LC-M3700

Ë

VHiPD64084+-1Q(ASSY:IC7001)

3-Dimensiona Y/C Separation LSI with a built-in 4M bit Memory

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

1,33,48,75 DGND — Digital part GND (common to I/O part grounding)

39,62,100 DVDD — Digital part 2.5V power supply

4-12,28-30, TEST01- Test terminal (OPEN or GND connection)

32,40-43, TEST26

78-85,99

13 EXTALTF O Extended 4fsc and an alternat-flag output terminal

14-23 EXTDYCO0- I/O Extended digital input-and-output terminal

EXTDYCO9

24-25 DGNDRAM — DRAM part GND

26-27 DVDDRAM — DRAM part 2.5V power supply

31 DVDDIO — I/O part 3.3V power supply

34-35 AGND — OSC circuit part GND

36 XI I Standard clock input

37 XO O Standard clock reversal output

38 AVDD — OSC circuit part 2.5V power supply

44 RPLL I Test input terminal (GND connection)

45 SLA0 I I2C-bus slave address selection input

46 SCL I I2C-bus clock input

47 SDA I/O I2C-bus clock output

49 AGND — I2C-bus data input-and-output terminal

50 AVDD — fsc DAC section 2.5V power supply

51 FSCO O fsc generator fsc output

52-53 AGND — 8fsc PLL section grounding

54 FSCI I 8fsc PLL fsc input

55 AVDD — 8fsc PLL section 2.5V power supply

56 CKMD I CLK8 test mode selection (GND connection)

57 CLK8 I/O CKMD = 0 : 8fSC clock output

CKMD = 1 : 8fsc clock input

58 RSTB I System reset input (active low)

59 ST0 O Internal signal monitor output

60 ST1 O Internal signal monitor output

61 NSTD O Non-standard detection monitor output

(L : A standard judging , H : Non-standard judging)

63-72 DYCO0-DYCO9 I/O Digital input and output

73 ALTF O 4fsc alternat-flag output

74 LINE I Compulsive line processing selection input

(L : It is usually Processing H. : Processing between compulsive lines)

76 KIL I External killer input

(L : It is usually Processing H. : Compulsive Y/C separation stop)

77 CSI I Composite sync. input (active low)

2 TESTIC1 I The test terminal for IC sorting (GND connection)

3 TESTIC2 I The test terminal for IC sorting (GND connection)

86 AVDD — Y-DAC and C-DAC part 2.5V power supply

87 CBPC O C-DAC phase compensation output

88 ACO O C-DAC analog C-signal output

89 AYO O C-DAC analog Y-signal output

90 CBPY O Y-DAC phase compensation output

91 AGND — Y-DAC and C-DAC part grounding

92 AGND — ADC section grounding

93 AYI I ADC analog composite signal input

94 VCLY O ADC clamp potential output

95 VRBY O ADC bottom standard voltage output

96 VRTY O ADC top standard voltage output

97 VCOMY O ADC standard voltage of the same phase

98 AVDD — ADC section 2.5V power supply

LC-M3710

39-2

39

39-1

LC-M3700

Pin No. Pin Name I/O Pin Function

1 GND_OUT O GND terminal only for RGB_OUT output stages.

2 YSYM2 I Control input terminal of YS2/YM2.

VM is turned off if an input level reaches the level of YM.

3 GND_SIG — GND terminal of Y-component and a RGB system.

4 B2_IN I Signal input terminal of an analog RGB 2.

5 G2_IN I

6 R2_IN I

7 YSYM1 I Control input terminal of YS1/YM1.

VM is turned off if an input level reaches the level of YM.

8 B1_IN I Signal input terminal of an analog RGB 1.

9 G1_IN I

10 R1_IN I

11 PABL_FIL Peak hold terminal of Peak ABL.

12 DPDT_OFF I Terminal which carries out signal section detection of dynamic picture (black

extension) operation and the rate of direct-current transmission to un-operating .

13 YF_OFF I Terminal for turning off VM, sharpness, and colour.

An input level corresponds with three values.

Ë

VHiCXA2150Q-1Q(ASSY:IC8802)

RGB processor

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

14 VM_OUT O VM output terminal.

The differentiation waveform of Y signal is outputted by positive.

15 VM_MOD I Terminal which modulates VM level.It becomes an output 0 less than 1.5V.

It becomes modulation by 1.5-3.5V.It becomes demodulation more than by 3.5V.

16 CLP_C Connection terminal of the capacitor for Y-system clamp.

17 BPH

A capacitor is connected to black detection of dynamic picture(black extension) at GND.

18 IREF_YC

Terminal for reference current creation of Y-component signal processing system.

19 Vcc5 — Power supply terminal of Y-component system, a RGB system, and the I2C

BUS section.

20 Y_IN I Signal input terminal of external YCbCr.

21 CB_IN I

22 CR_IN I

23 F0 I Free run frequency setting terminal.

24 F1 I

25 SDA I/O SDA (Serial Data) input terminal of a I2C BUS standard.

26 SCL I SCLÅiSerial ClockÅj input terminal of a I2C BUS standard.

27 SCP O Sand castle pulses output terminal.

H of Abbreviation 0-2.5V and a VBLK pulse are overlapped on the clamp pulse

of Abbreviation 0-5V, and it is outputted to them.

28 HS_IN I HSYNC input terminal. It inputs by the phase of a sync.

29 VREG5 Shant regulator of 5V is formed by connecting NPN-Tr for feedback to 30pin

30 VBIAS VBIAS and 29pin VREG5 by external.

31 IREF_HV H-system and V-system terminal for reference current creation.

32 AFC_FIL AFC lug-lead filter terminal.

33 CERA Terminal for 2.7MHz ceramic oscillation segment connection.

34 HPROT I Input terminal of the hold down signal of HD output.

If this terminal is carried out more than 2V more than 7V cycles, a hold down function will

work, HD output is held by Hi-Z, and it acts as all the Blanc kings of the RGB output.

35 VPROT I V-protection input terminal.

When a protection function works, a RGB output serves as all the blankings,

and "1" is outputted to a status register "VNG."

36 HCOMP_IN I Voltage input terminal for high-pressure change compensation.

The high-pressure compensation about DC amplitude of an EW_DRV signal

and the phase of a H_DRV signal is performed.

37 VCOMP_IN I Voltage input terminal for high-pressure change compensation.

The high-pressure compensation about the amplitude of a V_DRV signal is performed.

38 L2_FIL Filter terminal for 2nd loops of AFC.

39 HP_IN I Input terminal of H deviation pulse for H-AFC.

40 H_DRV O Output terminal of H-drive signal.

41 GND_H — GND terminal of a horizontal deviation (H) system.

42 VS_IN I VSYNC input terminal.

43 HC_PARA O Wide use V-parabola wave output terminal.

44 GND_V — GND terminal of a vertical deviation (V) system.

45 MP_PARA O Wide use V-parabola wave output terminal.

46 DF_PARA O

47 EW_DRV O V-parabola wave output terminal.

It is used for compensation of horizontal amplitude and horizontal pin distortion.

48 V_OSC Terminal for saw tooth wave creation.

49 V_AGC

Sample hold terminal for AGC which makes amplitude of V-saw tooth wave regularity.

50 VSAW0 O Output terminal of V-saw tooth wave (VSAW0).

51 VSAW1 O Output terminal of V-saw tooth wave (VSAW1).

52 V_DRV- O Output terminal of V-saw tooth wave.

53 V_DRV+ O V_DRV- and V saw tooth wave output terminal of reverse polarity.

54 VTIM O V-timing pulse output terminal.It is the plus terminal positive pulse of 0-5V.

The High period is in agreement with the position of VBLK of a RGB output.

55 Vcc9 — Power supply terminal of a vertical deviation (V) system.

56 ABL_IN I Terminal of the control signal input of ABL.It operates as an average value type.

57 ABL_FIL Capacitor is connected in order to form LPF to an ABL_IN incoming signal.

58 IK_IN I A reference pulse is returned to this terminal.

59 SABL_IN I Signal input terminal for SABL compensation.

60 PRE_RGB O Object for high-pressure drawing bend compensation, and a signal output

terminal for SABL compensation.

The signal which MIX(ed) the RGB signal is outputted.

61 VCC_OUT — Power supply terminal for RGB output stages.

62 B_OUT O RGB signal output terminal.Signal of 2.6 Vp-p is outputted by 100IRE.

63 G_OUT O

64 R_OUT O

»Pin Function

LC-M3710

40-2

40

40-1

LC-M3700

ËVHiSM5301AS-1Y(ASSY:IC8805)

3ch output video buffer with a built-in high band filter.

»Block Diagram

1 GINA/UINA I Analog GINA or a UINA signal input terminal. A synchronized signal is inputted

from a SYNCIN terminal.

2 GSG1 I The terminal for a GOUT/UOUT output buffer gain setup.

3 GINB/UINB I Analog GINB or a UINB signal input terminal. A synchronized signal is inputted

from a SYNCIN terminal.

4NC — Not connected

5 BINA/VINA I Analog BINA or a VINA signal input terminal. A synchronized signal is inputted

from a SYNCIN terminal.

6 GSB1 I The terminal for a BOUT/VOUT output buffer gain setup.

7 BINB/VINB I Analog BINB or a VINB signal input terminal. A synchronized signal is inputted

from a SYNCIN terminal.

8NC — Not connected

9 DISABLE I Power save function. Pull down resistance built-in.

L : Enable

H : Disable(output terminal : ROUT/YOUT, GOUT/UOUT and BOUT/VOUT are

high impedance.)

10 GND3 — Analog GND terminal.

11 BOUT/VOUT O B/V signal output terminal

12 VCC3 — Analog 5V power supply terminal.

13 GND2 — Analog GND terminal.

14 GOUT/UOUT O G/U signal output terminal

15 VCC2 — Analog 5V power supply terminal.

16 GND1 — Analog GND terminal.

17 ROUT/YOUT O R/Y signal output terminal

18 VCC1 — Analog 5V power supply terminal.

19 GND4 — Analog GND terminal.

20 RFC I

L.P.F.(Low path filter) The resistance connection terminal for a cutoff frequency setup.

21 VFC I

L.P.F.(Low path filter) The resistance connection terminal for a cutoff frequency setup.

22 MUXSEL I Input terminal selection signal. Pull down resistance built-in.

L : XINA terminal side is chosen.

H : YINB terminal side is chosen.

23 SYNCIN I The external H-sync signal input terminal for filter channels.

Active "H." Pull down resistance built-in.

24 VCC4 — Analog 5V power supply terminal.

25 RINA/YINA I

Analog RINA or a YINA signal input terminal. A synchronized signal is inputted from a SYNCIN terminal.

26 GSR1 I The terminal for a ROUT/YOUT output buffer gain setup.

27 RINB/YINB I

Analog RINB or a YINB signal input terminal. A synchronized signal is inputted from a SYNCIN terminal.

28 NC — Not connected

Pin No. Pin Name I/O Pin Function

»Pin Function

Ë

VHiTC90A69F-1Y(ASSY:IC401)

3 Line Digital Comb Filter

»Block Diagram

Pin No. Pin Name I/O Pin Function

»Pin Function

1 BIAS — Bias for ADC

2 VRT — D range upper bias for ADC

3 VDD1 — Power supply for ADC and DAC (analog system)

4 TESTI1 I Test input

5 VSS2 — GND for ADC (analog system)

6 VRB — D range lower bias for ADC

7 YCIN I Picture signal input

8 TEST O Reset control and TEST control at the time of shipment

9 KILLER I Y/C separation and vertical enhancer-off control

10 TESTI2 I Test input

11 VDD3 — Power supply for logic (digital system)

12 VSS3 — GND for Logic and DRAM (digital system)

13 VDD2 — Power supply for DRAM (digital system)

14 TESTI3 I Test input

15 SCL I Clock input of IIC BUS

16 SDA I Data input of IIC BUS

17 MODE1 O MODE1 output

18 TESTOUT I Test input

19 FSC I Clock input

20 VDD4 — Power supply for PLL (analog system)

21 VSS4 — GND for PLL (analog system)

22 FIL I VCO control

23 PD O PLL detection output

24 VB2 — Bias 2 for DAC

25 YOUT O Luminosity signal output

26 VSS1 — GND for DAC (analog system)

27 COUT O Color signal output

28 VB1 — Bias 1 for DAC

LC-M3710

41-2

41

41-1

LC-M3700

Ë

RH-iX3370CEN1,MSP3440G(ASSY:IC2501)

SOUND PROCCESSOR

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

1NC — Not connected

2 I2C_CL I/O I2C clock

3 I2C_DA I/O I2C data

4 I2S_CL I/O I2S clock

5 I2S_WS I/O I2S word strobe

6 I2S_DA_OUT O I2S data output

7 I2S_DA_IN1 I I2S1 data input

8 ADR_DA O ADR data output

9 ADR_WS O ADR word strobe

10 ADR_CL O ADR clock

11,12,1 DVSUP — Digital power supply 5V

14,15,16 DVSS — Digital ground

17 I2S_DA_IN2 I I2S2-data input

18,19,20 NC — Not connected

21 RESETQ I Power-on-reset

22,23 NC — Not connected

24 DACA_R O Headphone out, right

25 DACA_L O Headphone out, left

26 VREF2 — Reference ground 2

27 DACM_R O Loudspeaker out, right

28 DACM_L O Loudspeaker out, left

29 NC — Not connected

30 DACM_SUB O Subwoofer output

31,32 NC — Not connected

33 SC2_OUT_R O SCART 2 output, right

34 SC2_OUT_L O SCART 2 output, left

35 VREF1 — Reference ground 1

36 SC1_OUT_R O SCART 1 output, right

37 SC1_OUT_L O SCART 1 output, left

38 CAPL_A — Volume capacitor AUX

39 AHVSUP — Analog power supply 8V

40 CAPL_M — Volume capacitor MAIN

41,42 NC — Not connected

43,44 AHVSS — Analog ground

45 AGNDC — Analog reference voltage

46 NC — Not connected

47 SC4_IN_L I SCART 4 input, left

48 SC4_IN_R I SCART 4 input, right

49 ASG4 — Analog Shield Ground 4

50 SC3_IN_L I SCART 3 input, left

51 SC3_IN_R I SCART 3 input, right

52 ASG2 — Analog Shield Ground 2

53 SC2_IN_L I SCART 2 input, left

54 SC2_IN_R I SCART 2 input, right

55 ASG1 — Analog Shield Ground 1

56 SC1_IN_L I SCART 1 input, left

57 SC1_IN_R I SCART 1 input, right

58 VREFTOP — Reference voltage IF A/D converter

59 NC — Not connected

60 MONO_IN I Mono input

61,62 AVSS — Analog ground

63,64 NC — Not connected

65,66 AVSUP — Analog power supply 5V

67 ANA_IN1+ I IF input 1

68 ANA_IN- I IF common (can be left vacant, only if IF input 1 is also not in use)

69 ANA_IN2+ I IF input 2 (can be left vacant, only if IF input 1 is also not in use)

70 TESTEN I Test pin

71 XTAL_IN I Crystal oscillator

72 XTAL_OUT O

73 TP — Test pin

74 AUD_CL_OUT O Audio clock output(18.432MHz)

75,76 NC — Not connected

77 D_CTR_I/O_1 I/O D_CTR_I/O_1

78 D_CTR_I/O_0 I/O D_CTR_I/O_0

79 ADR_SEL I I2C Bus address select

80 STANDBYQ I Stand-by(low-active)

LC-M3710

42-2

42

42-1

LC-M3700

Ë

VHiNJU26150-1Q(ASSY:IC2510)

DIGITAL AUDIO PROCESSOR

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

1 SDO2 O Sound data output CH2

2 SDO1 O Sound data output CH1

3 SDO0 O Sound data output CH0

4 SDA2 I/O I2C I/O (for download)

5 SCL/SCK I I2C clock / serial clock

6 SDA/SDOUT I/O I2C I/O / serial out

7 AD1/SDIN I I2C address / serial in

8 AD2/SSX I I2C address / serial enable

9 VDDO — Power supply for oscillator (+2.5V)

10 XI I Clock input terminal

11 XO O Output for VCO connection

12 VSSO — Oscillator power supply GND

13 RESET I Reset terminal

14 VDDC — Internal power supply +2.5V

15 VSSC — Internal power supply GND

16 SCL2 I/O I2C clock output (for download)

17 VDDC — Internal power supply +2.5V

18 VDDC — Internal power supply +2.5V

19 VSSC — Internal power supply GND

20 VSSC — Internal power supply GND

21 VDDR — Power supply for I/O (+2.5V)

22 VDDR — Power supply for I/O (+2.5V)

23 VSSR — I/O ground

24 VSSR — I/O ground

25 SDI0 I Sound data output channel 0

26 SDI1 I Sound data output channel 1

27 SDI2 I Sound data output channel 2

28 LRI I LR clock input

29 BCKI I Bit clock input

30 MCK O A/D, D/A clock input

31 BCKO O Bit clock output

32 LRO O LR clock output

Ë

VHiTA2024++-1Y (ASSY:IC2303)

STEREO 15W (4Ω) DIGITAL AUDIO AMPLIFIER

»Block Diagram

Pin No. Pin Name I/O Pin Function

»Pin Function

2,3 DCAP2,

Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square

DCAP1

wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted

10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),

frequency, and phase as DCAP1.

4,9 V5D, V5A — Digital 5VDC, Analog 5VDC

5,8,17 AGND1, — Analog Ground

AGND2,

AGND3

6 REF — Internal reference voltage; approximately 1.0 VDC.

7 OVERLOADB A logic low output indicates the input signal has overloaded the mplifier.

10,14 OAOUT1, O Input stage output pins.

OAOUT2

11,15 INV1, Single-ended inputs. Inputs are a "virtual" ground of an inverting opamp with

INV2 approximately 2.4VDC bias.

12 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low

(grounded), both amplifiers are fully operational. If left floating, the device stays

in the mute mode. This pin should be tied to GND if not used.

16 BIASCAP Input stage bias voltage (approximately 2.4VDC).

18 SLEEP When set to logic high, device goes into low power mode. If not used, this pin

should be grounded

19 FAULT

A logic high output indicates thermal overload, or an output is shorted to ground,

or another output.

20,35 PGND2, — Power Grounds (high current)

PGND1

22 DGND — Digital Ground. Connect to AGND locally (near the TA2024).

24,27,

OUTP2 & OUTM2,

O Bridged output pairs

31,28

OUTP1 & OUTM1

25,26, VDD2,VDD2, Supply pins for high current H-bridges, nominally 12VDC.

29,30 VDD1,VDD1

13,21,23, NC — Not connected. Not bonded internally.

32,34

33 VDDA — Analog 12VDC

36 CPUMP Charge pump output (nominally 10V above VDDA)

1 5VGEN

Regulated 5VDC source used to supply power to the input section (pins 4 and 9).

LC-M3710

43-2

43

43-1

LC-M3700

Ë

VHiFA3675F/-1 (ASSY:IC1704)

6-channel DC-DC converter IC

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

1 VCC1 — Power supply for control circuit.

2RT — Oscillator timing resistor.

3CT — Oscillator timing capacitor.

4 CS3 — Soft start for Ch.3 & Ch.4.

5 CS5 — Soft start for Ch.6.

6 CS4 — Soft start for Ch.5.

7 CS1 — Soft start for Ch.1

8 CS2 — Soft start for Ch.2.

9 VREF O Reference voltage output.

10 CREF O Capacitor for reference voltage output.

11 VREG O Regulated for voltage output.

12 IN2- I Ch.2 inverting input to error amplifier.

13 FB2 O Ch.2 output of error amplifier.

14 IN1- I Ch.1 inverting input to error amplifier.

15 FB1 O Ch.1 output of error amplifier.

16 IN5+ I Ch.5 non-inverting input to error amplifier.

17 IN5- I Ch.5 inverting input to error amplifier.

18 FB5 O Ch.5 output of error amplifier.

19 IN6- I Ch.6 inverting input to error amplifier.

20 FB6 O Ch.6 output of error amplifier.

21 IN3+ I Ch.3 non-inverting input to error amplifier.

22 IN3- I Ch.3 inverting input to error amplifier.

23 FB3 O Ch.3 output of error amplifier.

24 IN4+ I Ch.4 non-inverting input to error amplifier.

25 IN4- I Ch.4 inverting input to error amplifier.

26 FB4 O Ch.4 output of error amplifier.

27 CP I Timing capacitor for timer latch delay.

28 GND — Ground.

29 TLSEL I Ch.3 & Ch.4 timer latch selection(Low:disable).

30 CNT5 I Ch.6 ON/OFF function.

31 CNT4 I Ch.5 ON/OFF function.

32 CNT2 I Ch.2 ON/OFF function.

33 CNT3 I Ch.3 & Ch.4 ON/OFF function.

34 CNT1 I Ch.1 ON/OFF function.

35 VCC2 — Power supply for output stage.

36 VDRV O Bias for logic circuit of output.

37 PGND1 — Power ground.

38 OUT1S O Ch.1 source electrode of output stage.

39 OUT1 O Ch.1 output(for Pch-MOSFET)

40 OUT4 O Ch.4 output(for Pch-MOSFET)

41 OUT3 O Ch.3 output(for Pch-MOSFET)

42 OUT2S O Ch.2 source electrode of output stage.

43 OUT2 O Ch.2 output(for Pch-MOSFET)

44 OUT6S O Ch.6 source electrode of output stage.

45 OUT6 O Ch.6 output(for Pch-MOSFET)

46 OUT5 O Ch.5 output(for Pch-MOSFET)

47 OUT5S O Ch.5 source electrode of output stage.

48 PGND2 — Power ground.

LC-M3710

44-2

44

44-1

LC-M3700

Ë

RH-iX3270CEZZ (ASSY:IC10001)

IC32bit RISC Micro Processor

»Pin Function

Pin No. Pin Name I/O Pin Function

34,36-44, D[15:0] I/O Data bus D[15:0]

46,48-52

23-26,28,30-32 D[23:16/PTA[7:0] I/O Data bus D[23:16]/I/O port A[7:0]

13-18,20,22 D[31:24/PTB[7:0] I/O Data bus D[31:24]/I/O port B[7:0]

86,84,82,78-72, A[25:0] O Address bus A[15:0]

70-68-60,56-53

96 CS0 O Chip select 0

98 CS2/PTK[0] O/(I/O) Chip select 2/I/O port K[0]

99 CS3/PTK[1] O/(I/O) Chip select 3/I/O port K[1]

100 CS4/PTK[2] O/(I/O) Chip select 4/I/O port K[2]

101 CS5/CE1E/PTK[3] O/(I/O) Chip select 5/CE1(area 5SPCMIA)/O port K[3]

102 CS6/CE1B 0 Chip select 6/CE1(area 6SPCMIA)

87 BS/PTK[4] O/(I/O) Bus cycle startup signal /I/O port K[4]

118 RAS3U/PTE[2] O/(I/O) RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port E[2]

106 RAS3L/PTJ[0] O/(I/O) RAS(area 3DRAM,SDRAM upper 32MB address)/I/O port J[0]

119 RAS2U/PTE[1] O/(I/O) RAS(area 2DRAM,SDRAM upper 32MB address)/I/O port E[1]

107 RAS2L/PTJ[1] O/(I/O) RAS(area 2DRAM,SDRAM upper 32MB address)/I/O portJE[1]

108

CASLL/CAS/PTJ[2]

O/(I/O) CAS(DRAM)/CAS(SDRAM)/I/O port J[2] for D7-D0.

110 CASLH/PTJ[3] O/(I/O) CAS(DRAM)/I/O port J[3] for D15-D18.

112 CASHL/PTJ[4] O/(I/O) CAS(DRAM)/I/O port J[4] for D23-D16.

113 CASHH/PTJ[5] O/(I/O) CAS(DRAM)/I/O port J[5] for D31-D24.

116 CAS2L/PTE[6] O/(I/O) CAS(area 2DRAM)/I/O port E[6] for D7-D0.

117 CAS2H/PTE[3] O/(I/O) CAS(area 2DRAM)/I/O port E[3] for D15-D8.

89 WE0/DQMLL O D7-D0 selection signal/DQM(SDRAM)

90 WE1/DQMLU/WE O D15-D8 selection signal/DQM(SDRAM)/PCMCIA WE

91 WE2/DQMUL/ O/(I/O) D23-D16 selection signal/DQM(SDRAM)/PCMCIA I/O port K[6]

ICIORD/PTK[6]

92 WE3/DQMUU/ O/(I/O) D31-D24 selection signal/DQM(SDRAM)/PCMCIA I/O write/I/O port K[7]

ICIOWR/PTK[7]

93 RD/WR O Read/write change signal

88 RD O Read strobe

105 CKE/PTK[5] O/(I/O) CK enable(Only for SDRAM)/I/O port K[5]

123 WAIT I Hardware weight demand.

11-8 IRL[3:0]/IRQ[3:0]/ I External interruption demand/I/OportH[3:0]

PTH[3:0]

12 IRQ4/PTH[4] I External interruption demand/I/OportH[4]

7 NMI I Non maskable interruption demand.

160 IRQOUT O Interruption demand output

182 WAKEUP/PTD[3] O/(I/O) Interruption demand output at the time of standby mode/I/OportD[3]

159 TCLK/PTH[7] I/O Clock input output/I/OportH[7] for TMU/RTC.

191 DREQ0/PTD[4] I DMA demand 0/I/OportD[4]

114 DACK0/PTD[5] O/(I/O) DMA acknowledge 0/I/O port D[5]

192 DREQ1/PTD[6] I DMA demand 0/I/O port D[6]

115 DACK1/PTD[7] O/(I/O) DMA acknowledge 1/I/O port D[7]

189 DRAK0/PTD[1] O/(I/O) DMA acknowledge 0/I/O port D[1]

190 DRAK1/PTD[0] O/(I/O) DMA acknowledge 0/I/O port D[0]

171 RxD0/SCPT[0] I Input port [0] for receiving data 0/SCI.

164 TxD0/SCPT[0] O Output port [0] for transmission data 0/SCI.

165 SCK0/SCPT[1] I/O I/O port [1] for serial clock 0/SCI.

172 RxD1/SCPT[2] I Input port [2] for receiving data 1/SCI.

166 TxD1/SCPT[2] O Output port [2] for transmission data 1/SCI.

167 SCK1/SCPT[1] I/O I/O port [3] for serial clock 1/SCI.

174 RxD2/SCPT[4] I Input port [4] for receiving data 2/SCI.

168 TxD2/SCPT[4] O Output port [4] for transmission data 2/SCI.

169 SCK2/SCPT[5] I/O I/O port [5] for serial clock 2/SCI.

170 RTS2/SCPT[6] O/(I/O) Requests to Send 2/for SCI/I/O port [6]

176

CTS2/IRQ5/SCPT[7]

I Transmitting clearance 2/an external interruption demand/Input port [7] for SCI.

104 CE2B/PTE[5] O/(I/O) Chip enable 2/I/O port E[5] for Pc card 0.

126 IOIS16/PTG[7] I Write protection/Input port G[7]

103 CE2A/PTE[[4] O/(I/O) Chip enable 2/I/O port E[4] for PC card 1.

146,149" CAP[1:2] — External capacity terminal for PLL [1:2]

156 EXTAL I External clock/Crystal oscillation element terminal

155 XTAL O Crystal oscillation element terminal

162 CKIO I/O System clock input and output

5 EXTAL2 I Crystal oscillation element terminal for RTC.

Pin No. Pin Name I/O Pin Function

4 XTAL O Crystal oscillation element terminal for RTC.

193 RESETP I Power-on reset demand

124 RESETM I Manual reset demand

122 BREQ I Bus demand

121 BACK O Bus acknowledge.

2,1,144 MD[2:0] I Clock mode setup

196,195 MD[4:3] I Area 0 bus wide setup.

197 MD5 I Endian setup

194 CA O Chip active.

158,157 STATUS[1:0]/ I/O Processor status[1:0]/I/O port J[7:6]

PTJ[7:6]

204-199 AN[5:0]/PTL[6:7] I A/D conversion input[5:0]/input port L[5:0]

206,207 AN[6:7]/DA[1:0]/ I/O A/D conversion input[6:7]/D/A conversion output[1:0]/input port L[6:7]

PTL[6:7]

177-180,185-188

PTC[7:0]/PINT[7:0]

I/O I/O port C[7:0]/port Interruption [7:0]

184

PTD[2]/RESETOUT

I/O I/O port D[2]/reset output

120,94 PTE[0]/PTE[7] I/O I/O port E[0]/I/O port E[7]

136-143

PTF[7:0]/PINT[15:8]

I I/O port F[7:0]/port Interruption [15:8]

127-131,135 PTG[6:0] I I/O port G[6:0]

125 PTH[5]/ADTRG I I/O port H[5]/Analog trigger

151 PTH[6] I I/O port H[6]

21,29,35,47,59,71, Vcc — power supply (3.3V)

81,85,97,111,134,

154,163,175,183,

145,150 Vcc(PLL) — power supply (3.3V)

3 Vcc(RTC) — power supply (3.3V)

205 Avcc — Analog power supply (3.3V)

19,27,33,45,57, Vss — power supply (0V)

69,79,83,95,109,

132,152,153,161,

173,181

147,148 Vss(PLL) — power supply (0V)

6 Vss(TRC) — power supply (0V)

198,208 Avss — Analog power supply (0V)

LC-M3710

45-2

45

45-1

LC-M3700

Ë

9DK001-15103 (CXA3516R) (ASSY:IC10004)

3ch 8bit 165MSPS A/D Converter Amplifier PLL

»Block Diagram

Pin No. Pin Name I/O Pin Function

1 B/CbOUT O B/Cb Amplifier output signal monitor

2 ADDRESS I I2C slave address setup

3 R/CrOUT O R/Cr Amplifier output signal monitor

4NC — Not connected

5NC — Not connected

6 XPOWERSAVE I Power save setup

7 DGNDREG — GND for registers

8 DVCCREG — Power supply for registers

9 SDA I Control register data input

10 SCL I Control register clock signal input

11 XSENABLE I Enable signal input for 3 line control registers

12 SEROUT O 3 line control register data read-out

13 3WIREÅ^I2C I Selection in I2C-bus mode and 3 line bus mode

15 AVCCADREF — Power supply for reference voltage of ADC

16,94 AVCCAD3 — Analog power supply of ADC

17 VRT O The top reference voltage output of ADC

18,92 DVCCAD3 — Digital power supply of ADC

19,32,42,54, DVCCADTTL — Power supply for a TTL output of ADC

65,76,90

20,33,44,55, DGNDADTTL — GND for a TTL output of ADC

67,77,89

21,22, RA0~RA7 O R channel port A side data output

24-28,31

»Pin Function

Pin No. Pin Name I/O Pin Function

23,30,43,50, DGNDAD3 — Digital GND of ADC

59,66,79,86

29,80 AGNDAD3 — Analog GND of ADC

34-41 RB0~RB7 O R channel port B side data output

45-49,51-53 BA0~BA7 O B channel port A side data output

56-58,60-64 BB0~BB7 O B channel port B side data output

68-75 GA0~GA7 O G channel port A side data output

78,81-85,87,88 GB0~GB7 O G channel port B side data output

91 DVCCAD — Digital power supply of ADC

93 VRB O Bottom reference voltage output of ADC

95 AGNDADREF — GND for reference voltage of ADC

96 DVCCPLLTTL — Power supply for a TTL output of PLL

97 DGNDPLLTTL — Power supply for a TTL output of PLL

98 XCLKCLK O CLK reversal output

99 1/2XCLK O CLK output

100 1/2CLK O 1/2 CLK reversal output

101 DSYNC/ O 1/2 CLK output

103 DIVOUT O DSYNC signal output/DIVOUT signal output

104 UNLOCK O UNLOCK signal output terminal

105 SOGOUT O Synchronization signal output of a sync-on green signal

106 HOLD I Input of de-servile signal of phase comparison

107 XTLOAD I Reset setup of a programmable counter

108 EVEN/ODD I Sampling clock reversal pulse input of ADC

109 XCLKIN I Negative clock input for a test

110 CLKIN I Positive clock input for a test

111 SYNCIN1 I Synchronization signal input 1

112 SYNCIN2 I Synchronization signal input 2

113 CLPIN I Clamp pulse input

114 DVCCPLL — Power supply for PLL

115 DGNDPLL — Digital ground for PLL

116 AVCCVCO — Analog power supply for VCO of PLL

117 AGNDVCO — Analog ground for VCO of PLL

118 RC1 — PLL loop filter external terminal 1

119 RC2 — PLL loop filter external terminal 2

120 AVCCIR — Analog power supply for IRFE

121 IREF I Current setup

123 AGNDIR — Analog ground for IRFE

124 G/YIN1 I G/Y signal input 1

125 AVCCAMPG — Power supply for G/Y amplifier

126 G/YIN2 I G/Y signal input 2

127 AGNDAMPG — Ground for G/Y amplifier

128 G/YCLP — Clamp capacitor connection terminal for G/Y brightness

129 B/CbCLP — Clamp capacitor connection terminal for B/Cb brightness

130 R/CrCLP — Clamp capacitor connection terminal for R/Cr brightness

132 SOGIN1 I Sync-on green signal input 1

133 B/CbIN1 I B/Cb signal input1

134 AVCCAMPB — Power supply for B/Cb amplifier parts

135 SOGIN2 I Sync-on green signal input 2

136 B/CbIN2 I B/Cb signal input 2

137 AGNDAMPB — Ground for B/Cb amplifier parts

139 R/CrIN1 I R/Cr signal input 1

140 AVCCAMPR — Power supply for R/Cr amplifier parts

141 R/CrIN2 I R/Cr signal input 2

142 AGNDAMPR — Ground for R/Cr amplifier parts

143 G/YOUT O Amplifier output signal monitor

144 DACTEST O For amplifier part control registers

Test output terminal of DAC

14,102,122, OUTDPGND — Ground

131,138

LC-M3710

46-2

46

46-1

LC-M3700

Ë

RH-iXA312WJN1Q(MT48LC2M32B2-512K) (ASSY:IC4702,4903)

64Mb: x32 SDRAM

»Block Diagram

»Pin Function

Pin No. Pin Name I/O Pin Function

68 CLK I Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter and

controls the output registers.

67 CKE I Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF

REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in

any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is

synchronous except after the device enters power-down and self refresh

modes, where CKE becomes asynchronous until after exiting the same mode.

The input buffers, including CLK, are disabled during power-down and self

refresh modes, providing low standby power. CKE may be tied HIGH.

20 CS# I Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS#provides for external bank selection on systems with multiple banks.

CS# is considered part of the command code.

17, 18, 19 WE#, CAS#,RAS# I Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the

command being entered.

16, 71, 28, 59 DQM0-DQM3 I Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is masked

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) during a READ cycle. DQM0 corresponds to DQ0-DQ7; DQM1

corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23; and DQM3

corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when

referenced as DQM.

22, 23 BA0, BA1 I Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied.

25-27, 60-66, 24 A0-A10. I Address Inputs: A0-A10 are sampled during the ACTIVE command (rowaddress

A0-A10) and READ/WRITE command (column-address A0-A7 with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine

if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1

(LOW). The address inputs also provide the op-code during a LOAD MODE

REGISTER command.

2, 4, 5, 7, 8, 10, DQ0-DQ31 I/O Data I/O: Data bus.

11, 13,

74, 76, 77, 79,

80, 82, 83,

85, 31, 33, 34,

36, 37, 39,

40, 42, 45, 47,

48, 50, 51,

53, 54, 56

14, 21, 30, 57, NC — No Connect: These pins should be left unconnected.

69,70, 73

3, 9, 35, 41, 49, N.C. — DQ Power Supply: Isolated on the die for improved noise immunity.

55, 75, 81

6, 12, 32, 38, VR4 O DQ Ground: Provide isolated ground to DQs for improved noise immunity.

46, 52, 78, 84

1, 15, 29, 43 VR3 O Power Supply: +3.3V ±0.3V.

44, 58, 72, 86 N.C. — Ground.

LC-M3710

47-2

47

47-1

LC-M3700

Ë

RH-iXA350WJZZQ(IR3E11M1) (ASSY:IC4105)

IC for TFT-LCD of gradation reference voltage.

»Block Diagram

Pin No. Pin Name I/O Pin Function

»Pin Function

1 VL1 O L1 amplifier output

2 VL2 O L2 amplifier output

3 N.C. — Non-connected terminal

4 VL3 O L3 amplifier output.

5 VL4 O L4 amplifier output.

6 N.C. — Non-connected terminal

7 N.C. — Non-connected terminal

8 N.C. — Non-connected terminal

9 VCC2 — Power supply terminal.

10 N.C. — Non-connected terminal.

11 VR4 O R3 amplifier output.

12 VR3 O R4 amplifier output.

13 N.C. — Non-connected terminal

14 VR2 O R2 amplifier output.

15 VR1 O R1 amplifier output.

16 N.C. — Non-connected terminal

17 VR0 O R0 amplifier output.

18 VCC1 — Power supply terminal.

19 VR I REF amplifier reference input terminal.

20 VREF O REF amplifier output.

21 N.C. — Non-connected terminal

22 VA0 I R0 amplifier reference input terminal.

23 VA1 I R1 amplifier reference input terminal.

24 N.C. — Non-connected terminal

25 VA2 I R2 amplifier reference input terminal.

26 VA3 I R3 amplifier reference input terminal.

27 N.C. — Non-connected terminal

28 VA4 I R4 amplifier reference input terminal.

29 GND2 — Ground terminal.(for OP amplifier)

30 N.C. — Non-connected terminal

31 N.C. — Non-connected terminal.

32 N.C. — Non-connected terminal.

33 VB4 I L4 amplifier reference input terminal.

34 N.C. — Non-connected terminal.

35 VB3 I L3 amplifier reference input terminal.

36 VB2 I L2 amplifier reference input terminal.

37 N.C. — Non-connected terminal.

38 VB1 I L1 amplifier reference input terminal.

39 VB0 I L0 amplifier reference input terminal.

40 N.C. — Non-connected terminal.

41 GND1 — Ground terminal.

42 COMI I COM amplifier reference input terminal.

43 COMO O COM amplifier output.

44 COMS I COM amplifier reversal input terminal

45 N.C. — Non-connected terminal.

46 N.C. — Non-connected terminal.

47 VLO O L0 amplifier output.

48 N.C. — Non-connected terminal.

LC-M3710

48-2

48

48-1

LC-M3700

Ë

VHiMB8346BV-1Y(ASSY:IC2006)

D/A CONVERTOR

»Block Diagram

Pin No. Pin Name I/O Pin Function

17 DI I Data input terminal.

12-bit serial data is inputted.

14 DO O Data output terminal.

Bit data of MSB of a 12-bit shift register is outputted.

16 CLK I Shift clock input terminal.

Incoming signal from DI terminal is inputted into a 12-bit shift register in the

leading edge of a shift clock.

15 LD I Load signal input terminal.

An input of the "H" level loads the data of a 12-bit shift register to a decoder and

the register for an D/A output.

18 AO1 O D/A output terminal.

19 AO2 O Analog data of a 8-bit D/A converter with an OP amplifier is outputted.

2 AO3 O

3 AO4 O

4 AO5 O

5 AO6 O

6 AO7 O

7 AO8 O

8 AO9 O

9 AO10 O

12 AO11 O

13 AO12 O

11 Vcc — MCU interface and the power supply terminal of an OP amplifier.

20 GND — MCU interface and the ground terminal of an OP amplifier.

10 Vdd — Power supply terminal for D/A converter.

1 Vss — Ground terminal for D/A converter.

»Pin Function

»Pin Function

Ë

VHiMD1422N+-1Y(ASSY:IC1703)

DC-DC converter power IC

»Block Diagram

Pin No. Pin Name I/O Pin Function

1 S/S I capacitor connection terminal for a soft start.

2 OCL- I Over(-) current-detection terminal.

3 OCL+ I Over-current (+) detection terminal.

4,26 GND — GND terminal.

5 R/C I Remote ON/OFF control terminal.

6 Vcc — Power supply terminal of a control circuit.

8 Vboot I Power supply terminal of a main switch and MOSFET control circuit.

9 VGL I Gate terminal of the Low side MOSFET for periodic rectification.

11~14 VOUT O Output terminal of the power stage.

16 P.GND — GND terminal of an output circuit.

18~21 VDD — Power supply terminal of the main switch MOSFET.

23 VGH I Gate terminal of the high side MOSFET for periodic rectification.

25 VB I Output bootstrap terminal.

Capacitor is connected between VB terminal and VOUT and the circuit for

control of MOSFET inside IC is bootstrapped.

27 VTS — Terminal for TEST. Please do not connect anywhere.

28 Vref I Internal standard voltage output terminal.

30 ampOUT O Built-in error amplifier output terminal.

32 amp- I Built-in error amplifier reversal input terminal. .

7,10,15,17, N/C — It is a no-connection terminal.

22,24,29,31

LC-M3710

49-2

49

49-1

LC-M3700

Ë

RH-iXA332WJZZQ(ASSY;IC4701)

QS駆動（EVEN）IC

»Pin Function

Pin No. Pin Name I/O Pin Function

1 GND

2 TMS

3 HSIN

4 VSIN

5 DEIN

6 REMS7

7 REMS6

8 REMS5

9 REMS4

10 REMS3

11 GND

12 VCCO

13 VCCINT

14 REMS2

15 REMS1

16 REMS0

17 GEMS7

18 GEMS6

19 GND

20 GEMS5

21 GEMS4

22 GEMS3

23 GEMS2

24 GEMS1

25 GND

26 VCCO

27 GEMS0

28 VCCINT

29 BEMS7

30 BEMS6

31 BEMS5

32 GND

33 BEMS4

34 BEMS3

35 BEMS2

36 BEMS1

37 BEMS0

38 VCCINT

39 VCCO

40 GND

41 NC

42 NC

43 NC

44 NC

45 NC

46 NC

47 NC

48 NC

49 NC

50 M1

51 GND

52 M0

53 VCCO

54 M2

55 NC

56 NC

57 MP_DA

58 MP_CK

59 MP_CS

60 DDC_RST

61 DQ23

62 DQ22

63 DQ21

64 GND

65 VCCO

66 VCCINT

67 DQ20

68 DQ19

69 DQ18

70 DQ17

71 DQ16

72 GND

73 DQM2

74 A2

75 A1

76 VCCINT

77 CLK(GCK1)

78 VCCO

79 GND

80 GCK0

81 A0

82 A10

83 BA1

84 BA0

85 GND

86 CS#

87 RAS#

88 CAS#

89 WE#

90 NC

91 VCCINT

92 VCCO

93 GND

94 DQM0

95 DQ7

96 DQ6

97 DQ5

98 DQ4

99 DQ3

100 DQ2

101 DQ1

102 DQ0

103 GND

104 DONE

105 VCCO

106 PROGRAM

107 INIT

108 NC

109 NC

110 NC

111 NC

112 NC

113 NC

114 NC

115 NC

116 GND

117 VCCO

118 VCCINT

119 NC

120 RE7

121 RE6

122 RE5

123 RE4

124 GND

125 RE3

126 RE2

127 RE1

128 VCCINT

129 RE0

130 VCCO

131 GND

132 GE7

133 GE6

134 GE5

135 GE4

136 GE3

Pin No. Pin Name I/O Pin Function

LC-M3710

50-2

50

50-1

LC-M3700

137 GND

138 GE2

139 GE1

140 GE0

141 NC

142 BE7

143 VCCINT

144 VCCO

145 GND

146 BE6

147 BE5

148 BE4

149 BE3

150 BE2

151 BE1

152 BE0

153 DIN

154 DOUT

155 CCLK

156 VCCO

157 TDO

158 GND

159 TDI

160 DQ15

161 DQ14

162 DQ13

163 DQ12

164 DQ11

165 DQ10

166 DQ9

167 DQ8

168 DQM1

169 GND

170 VCCO

171 VCCINT

172 SDCLK

173 SDCLKE

174 A9

175 A8

176 A7

177 GND

178 A6

179 A5

180 A4

181 A3

182 GCK2

183 GND

184 VCCO

185 CLK(GCK3)

186 VCCINT

187 DQM3

188 DQ31

189 DQ30

190 GND

191 DQ29

192 DQ28

193 DQ27

194 DQ26

195 DQ25

196 VCCINT

197 VCCO

198 GND

199 DQ24

200 NC

201 NC

202 NC

203 NC

204 NC

205 NC

206 NC

Pin No. Pin Name I/O Pin Function

207 TCK

208 VCCO

Pin No. Pin Name I/O Pin Function

LC-M3710

51-2

51-1

51

LC-M3700

Pin No. Pin Name I/O Pin Function

1 GND

2 TMS

3NC

4NC

5NC

6NC

7NC

8NC

9NC

10 NC

11 GND

12 VCCO

13 VCCINT

14 NC

15 ROMS7

16 ROMS6

17 ROMS5

18 ROMS4

19 GND

20 ROMS3

21 ROMS2

22 ROMS1

23 ROMS0

24 GOMS7

25 GND

26 VCCO

27 GOMS6

28 VCCINT

29 GOMS5

30 GOMS4

31 GOMS3

32 GND

33 GOMS2

34 GOMS1

35 GOMS0

36 BOMS7

37 BOMS6

38 VCCINT

39 VCCO

40 GND

41 BOMS5

42 BOMS4

43 BOMS3

44 BOMS2

45 BOMS1

46 BOMS0

47 HSIN

48 VSIN

49 DEIN

50 M1

51 GND

52 M0

53 VCCO

54 M2

55 NC

56 NC

57 MP_DA

58 MP_CK

59 MP_CS

60 DDC_RST

61 DQ23

62 DQ22

63 DQ21

64 GND

65 VCCO

66 VCCINT

Ë

RH-iXA332WJZZQ(ASSY:IC4901)

QS駆動（ODD）IC

»Pin Function

67 DQ20

68 DQ19

69 DQ18

70 DQ17

71 DQ16

72 GND

73 DQM2

74 A2

75 A1

76 VCCINT

77 CLK(GCK1)

78 VCCO

79 GND

80 GCK0

81 A0

82 A10

83 BA1

84 BA0

85 GND

86 CS#

87 RAS#

88 CAS#

89 WE#

90 NC

91 VCCINT

92 VCCO

93 GND

94 DQM0

95 DQ7

96 DQ6

97 DQ5

98 DQ4

99 DQ3

100 DQ2

101 DQ1

102 DQ0

103 GND

104 DONE

105 VCCO

106 PROGRAM

107 INIT

108 BO0

109 BO1

110 BO2

111 BO3

112 BO4

113 BO5

114 BO6

115 BO7

116 GND

117 VCCO

118 VCCINT

119 NC

120 GO0

121 GO1

122 GO2

123 GO3

124 GND

125 GO4

126 GO5

127 GO6

128 VCCINT

129 GO7

130 VCCO

131 GND

132 RO0

133 RO1

134 RO2

135 RO3

136 RO4

Pin No. Pin Name I/O Pin Function

LC-M3710

52-2

52

52-1

LC-M3700

Pin No. Pin Name I/O Pin Function

137 GND

138 RO5

139 RO6

140 RO7

141 NC

142 NC

143 VCCINT

144 VCCO

145 GND

146 DEOUT

147 HSOUT

148 VSOUT

149 NC

150 NC

151 NC

152 NC

153 DIN

154 DOUT

155 CCLK

156 VCCO

157 TDO

158 GND

159 TDI

160 DQ15

161 DQ14

162 DQ13

163 DQ12

164 DQ11

165 DQ10

166 DQ9

167 DQ8

168 DQM1

169 GND

170 VCCO

171 VCCINT

172 SDCLK

173 SDCLKE

174 A9

175 A8

176 A7

177 GND

178 A6

179 A5

180 A4

181 A3

182 GCK2

183 GND

184 VCCO

185 GCK3

186 VCCINT

187 DQM3

188 DQ31

189 DQ30

190 GND

191 DQ29

192 DQ28

193 DQ27

194 DQ26

195 DQ25

196 VCCINT

197 VCCO

198 GND

199 DQ24

200 NC

201 NC

202 NC

203 NC

204 NC

205 NC

206 NC

207 TCK

208 VCCO

Pin No. Pin Name I/O Pin Function

LC-M3710

53-2

53-1

53

LC-M3700

Pin No. Pin Name I/O Pin Function

1 VCCIO

2A13

3 GND

4WE

5 FRST

6A12

7 RY/BY

8 VCCINT

9 GND

10 A11

11 GND

12 GND

13 GND

14 GND

15 A10

16 M0

17 M1

18 GND

19 M2

20 A9

21 GND

22 GND

23 GND

24 A8

25 GND

26 PROGRAM

27 D/P

28 A7

29 GND

30 CCLK

31 INIT

32 OE

33 DIN

34 CE

35 A6

36 GND

37 VCCIO

38 CLK

39 DONE

40 A5

41 DATA

42 VCCINT

43 RESET

44 GND

45 A4

46 PROG

47 GND

48 GND

49 GND

50 A3

51 GND

52 GND

53 GND

54 GND

55 VCCIO

56 A2

57 GND

58 GND

59 GND

60 A1

61 GND

62 GND

63 TDI

64 GND

65 TMS

66 A0

Ë

IC4303(RH-IXA787WJZZQ)

CPLD

»Pin Function

67 TCK

68 GND

69 GND

70 GND

71 A-1

72 GND

73 VCCIO

74 DQ0

75 GND

76 GND

77 GND

78 DQ1

79 GND

80 GND

81 GND

82 DQ2

83 GND

84 VCCINT

85 GND

86 DQ3

87 GND

88 GND

89 GND

90 GND

91 DQ4

92 GND

93 GND

94 GND

95 DQ5

96 GND

97 GND

98 GND

99 GND

100 GND

101 DQ6

102 GND

103 GND

104 GND

105 GND

106 DQ7

107 GND

108 GND

109 VCCIO

110 MODE0

111 MODE1

112 GND

113 GND

114 GND

115 A19

116 GND

117 GND

118 GND

119 GND

120 GND

121 A18

122 TDO

123 GND

124 GND

125 A17

126 GND

127 VCCIO

128 GND

129 GND

130 A16

131 GND

132 GND

133 GND

134 GND

135 A15

136 GND

Pin No. Pin Name I/O Pin Function

LC-M3710

54-2

54

54-1

LC-M3700

Pin No. Pin Name I/O Pin Function

137 GND

138 GND

139 GND

140 A14

141 VCCINT

142 GND

143 SET

144 GND

Pin No. Pin Name I/O Pin Function

Ë

RH-iXA457WJZZ(ASSY:IC4501)

FG256

»Pin Function

A1 GND

A2 IGE1

A3 RST

A4 GACS

A5 SCK

A6 SDA

A7 IBE0

A8 PMUTE

A9 DE

A10 HS

A11 VS

A12 OFL2

A13 IBO0

A14 OFL

A15 TDI

A16 GND

B1 IRE2

B2 GND

B3 IGE0

B4 IBE4

B5 IBE3

B6 IBE2

B7 IBE1

B8 CLK(GCK3)

B9 IGO0

B10 IBO4

B11 IBO3

B12 IBO2

B13 IBO1

B14 TDO

B15 GND

B16 IRO2

C1 IRE0

C2 IRE1

C3 VCCINT

C4 TCK

C5 IBE7

C6 IBE6

C7 IBE5

C8 IGO2

C9 GCK2

C10 IGO1

C11 IBO6

C12 IBO5

C13 IRO3

C14 VCCINT

C15 DOUT

C16 IRO0

D1 IRE4

D2 IRE3

D3 TMS

D4 VCCINT

D5 IGE5

D6 IGE4

D7 IGE3

D8 IGE2

D9 IGO5

D10 IGO4

D11 IGO3

D12 IBO7

D13 VCCINT

D14 DIN

D15 CCLK

D16 IRO1

E1 OEM_INV

E2 IRE7

LC-M3710

55-2

55-1

55

LC-M3700

Pin No. Pin Name I/O Pin Function

E3 IRE6

E4 IRE5

E5 VCCINT

E6 IGE7

E7 IGE6

E8 VCCO(0)

E9 VCCO(1)

E10 IGO7

E11 IGO6

E12 VCCINT

E13 IRO7

E14 IRO6

E15 IRO5

E16 IRO4

F1 OEM

F2 LOB0

F3 LOB1

F4 LOB2

F5 LOB3

F6 GND

F7 GND

F8 VCCO(0)

F9 VCCO(1)

F10 GND

F11 GND

F12 RER7

F13 RER6

F14 RER5

F15 RER4

F16 GSP1

G1 LEB0

G2 LOB4

G3 LOB5

G4 LOB6

G5 LOB7

G6 GND

G7 GND

G8 GND

G9 GND

G10 GND

G11 GND

G12 RER3

G13 RER2

G14 RER1

G15 RER0

G16 GSP2

H1 LEB1

H2 LEB2

H3 LEB3

H4 LEB4

H5 VCCO(7)

H6 VCCO(7)

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCCO(2)

H12 VCCO(2)

H13 ROR5

H14 ROR6

H15 ROR7

H16 GLBR

J1 LEG0

J2 LEB5

J3 LEB6

J4 LEB7

J5 VCCO(6)

J6 VCCO(6)

J7 GND

J8 GND

Pin No. Pin Name I/O Pin Function

J9 GND

J10 GND

J11 VCCO(3)

J12 VCCO(3)

J13 ROR4

J14 ROR3

J15 ROR2

J16 ROR1

K1 LEG1

K2 LEG2

K3 LEG3

K4 LEG4

K5 LEG5

K6 GND

K7 GND

K8 GND

K9 GND

K10 GND

K11 GND

K12 ROG7

K13 ROG6

K14 ROG5

K15 ROG4

K16 ROR0

L1 SPIO1

L2 LOG6

L3 LOG7

L4 LEG6

L5 LEG7

L6 GND

L7 GND

L8 VCCO(5)

L9 VCCO(4)

L10 GND

L11 GND

L12 ROG3

L13 ROG2

L14 ROG1

L15 ROG0

L16 LBR

M1 SPOI1

M2 LOG3

M3 LOG4

M4 LOG5

M5 VCCINT

M6 LOR7

M7 LER7

M8 VCCO(5)

M9 VCCO(4)

M10 ROB6

M11 ROB7

M12 VCCINT

M13 REG7

M14 REG6

M15 REG5

M16 REG4

N1 LPOL1

N2 LOG1

N3 M0

N4 VCCINT

N5 LOR5

N6 LOR6

N7 LER6

N8 GCK0

N9 ROB3

N10 ROB5

N11 REB2

N12 REB3

N13 VCCINT

N14 REG3

LC-M3710

56-2

56

56-1

LC-M3700

N15 INIT

N16 REG1

P1 LPOL2

P2 M1

P3 VCCINT

P4 NC

P5 LOR4

P6 LER2

P7 LER5

P8 ROB1

P9 ROB2

P10 ROB4

P11 REB1

P12 REB4

P13 REB6

P14 VCCINT

P15 PROGRAM

P16 REG0

R1 LOG2

R2 GND

R3 M2

R4 NC

R5 LOR3

R6 LER1

R7 LER4

R8 GCK1

R9 ROB0

R10 SPOI2

R11 REB0

R12 REB5

R13 REB7

R14 DONE

R15 GND

R16 REG2

T1 GND

T2 LOG0

T3 LOR0

T4 LOR1

T5 LOR2

T6 LER0

T7 LER3

T8 LS

T9 REV

T10 OCK

T11 SPIO2

T12 RPOL1

T13 RPOL2

T14 POWER

T15 GCK

T16 GND

Pin No. Pin Name I/O Pin Function

Pin No. Pin Name I/O Pin Function

1 KEY1

2 OSTEMP

3 AVSS

4 F_MODE

5 XOUT

6XIN

7 VSS

8 OSCIN

9 OSCOUT

10 RESET

11 FVPP

12 TMDS_RST

13 RSTB_TMDS

14 SR_UP

15 LSYNC

16 IREM

17 L_FL_ERR

18 TV_POW2

19 TV_POW

20 DDC_SCL

21 DDC_SDAI

22 DDC_SDAO

23 CONFIG_SCL

24 CONFIG_SDAI

25 CONFIG_SDAO

26 MREADY

27 REQOUT

28 VSH_IN

29 VSH_OUT

30 CSEN1

31 FAN-ERR

32 POWDTC_M

33 VCC

34 POWR_LED

35 OPC_LED

36 TIM_LED

37 POWG_LED

38 SMPOW

39 DACCS1

40 DACCS2

41 DACRST

42 PAMUTE

43 SMUTE

44 FAN-CNT

45 PANEL_POW

46 AUDIO_ERR1

47 SP_INOUT

48 RXD0_M

49 TXD0_M

50 MP_DA

51 MP_CS

52 MP_CLK

53 PMUTE

54 DDCRST

55 CSEN2

56 DDCPOW

57 STBY_POW

58 AVCC

59 CCKM

60 OPC

61 KEY3

62 AREA2

63 AREA1

64 KEY2

Ë

RH-iX3491CEZZQ(ASSY:IC2004)

モニターマイコン

»Pin Function

LC-M3710

57-2

57

57-1

CHASSIS LAYOUT

LC-M3700
LC-M3710

INVERTER-1 PWB

H

MOMITOR PWB

INVERTER-3 PWB

DC/DC PWB

G

F

MAIN PWB

KEY PWB

E

INVERTER-2 PWB

D

INVERTER-4 PWB

INPUT-1 PWB INPUT-2 PWB

C

B

R/C, LED PWB

SPEAKER-R PWB SPEAKER-L PWBAC INLET PWB

A

121110987654321

58

59

SYSTEM BLOCK DIAGRAM

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

121110987654321

60

61

SIGNAL FLOW BLOCK DIAGRAM

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

121110987654321

62

63

PC I/F UNIT BLOCK DIAGRAM

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

121110987654321

64

65

LC-M3700
LC-M3710

BLOCK DIAGRAM (Display)

H

G

BLOCK DIAGRAM (MONITOR)

F

E

DO

OFL 1, 2

LCD BACKLIGHT

LCD PANEL

RGB
8X3X2 8X3X2

LCD CONTROLLER

BGA (256) pin

(LCDCONT)

IC4501 (A457WJ)

CTRL

RGB

Gradation signal

Reverse signal

Dimming, resolution control, test pattern

POWER LINS ON MONITOR PWB

DC6V input
(Pin (4) of CN7707)

DC15V input
(Pin (2) of CN7707)

GRADATION POWER

(V0, V64, V96, V128,

V160,

V192, V224, V256)

BIAS SETUP D/A

(GRAYLEVEL)

DA control

5V Reg

IC7701

12V Reg

IC7707

5V Reg

IC7703

2.5V Reg

IC7704

3.3V Reg

IC7705

3.3V Reg

IC7706

13V Reg

IC4102

6V Reg

IC4106

R/C. LED

Monitor microcomputer (power), sync detection

Monitor microcomputer (Flash rewrite power)

PC interface connect confirm signal

LCD controller, QS (odd), QS (even) core power

LCD controller, QS (odd), QS (even) I/O power;
CPLD and flash, SDRAM power

Panel power (VSH)

Panel gradation reference power

DC / DC

32V

DC / DC

– 6V

DC / DC

15V

Panel power (VGH)

Panel power (VGL)

Panel power (VLS)

D

CONF
FLASH

REWRITE
CONNECTOR

C

SDRAM(OS_EVEN)

IC4702 A312WJ

CONF
CTRL
CPLD
IC4303
(A345WJ)

16 (data)

17 (address, etc.)

CLK, DONE

QS DRIVER (EVEN)

QFP (208) pin

(QS_EVEN)

RGB
8X3

D2

IC4701 (A332WJ)

H, V,
DE

BUF

H, V,
DE

QS DRIVER (ODD)

QFP 208-pin

IC4901 (A332WJ)

CL
K

B

RGB
8X3

(QS_ODD)

RGB
8X3

D1

16 (data)

17 (address, etc.)

H, V,
DE

H

SDRAM (OS_ODD)

IC4902 (A312WJ)

QS control, test pattern

SYNC JUDGE CIRCUIT

MONITOR

MICROPROCESSOR

H8

(MICON)

IC2004 (3491CE)

KEY

2

PROM

E

Thermistor

Power detection

Power unit control

Power circuit control

Mute

REWRITE
CONNECTOR

SIGNAL 1 CONNECTOR ((80) pin)

CN4701 (M0054CE)

A

SYSTEM CONNECTOR (15) pin)

CN2001 (MA082WJ)

* Main communication UARI
* Flash write control
* Power control
* Various detections
* SR remote control signal

121110987654321

66

67

O VERALL WIRING DIAGRAM-1/2

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

121110987654321

68

69

O VERALL WIRING DIAGRAM-1/2

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

121110987654321

70

71

LC-M3700
LC-M3710

DESCRIPTION OF SCHEMATIC DIAGRAM

VOLTAGE MEASUREMENT CONDITION:

1. When the exclusive-use AC adapter is used, the colour
bar signal of colour bar generator for service is input to
get the normal screen. When the audio is minimized,
the voltage value is measured with the 20 kΩ/V tester.

WAVEFORM MEASUREMENT CONDITION:

1. When the exclusive-use AC adapter is used, the colour
density, lightness and colour hue are set to the center
position, and the signal of colour bar generator for
service is observed to get waveform.

2. indicates waveform check points (See chart,
waveforms are measured from point indicated to
chassis ground.)

INDICATION OF RESISTOR & CAPACITOR:

RESISTOR

1. The unit of resistance “Ω” is omitted.
(K=kΩ=1000 Ω, M=MΩ).

2. All resistors are ± 5%, unless otherwise noted.
(J= ± 5%, F= ± 1%, D= ± 0.5%)

3. All resistors are Carbon type, unless otherwise noted.

C : Solid W : Cement
S : Oxide Film T : Special
N : Metal Coating

CAPACITOR

1. All capacitors are mF, unless otherwise noted.
(P=pF=mmF).

2. All capacitors are Ceramic type, unless otherwise
noted.
(ML) : Mylar (TA) : Tantalum
(PF) : Polypro Film (ST) : Styrol

CAUTION:

This circuit diagram is original one, therefore there may be a
slight difference from yours.

IMPORTANT SAFETY NOTICE:

PARTS MARKED WITH
IMPORTANT FOR MAINTAINING THE SAFETY OF
THE SET. BE SURE TO REPLACE THESE PARTS
WITH SPECIFIED ONES FOR MAINTAINING THE
SAFETY AND PERFORMANCE OF THE SET.

“å”

( )ARE

AVIS DE SECURITE IMPORTANT:

LES PIECES MARQUEES “å” ( )SONT
IMPORTANTES POUR MAINTENIR LA SECURITE
DE L'APPAREIL.
NE REMPLACER CES PIEDES QUE PAR DES
PIECES DONT LE NUMERO EST SPECIFIE POUR
MAINTENIR LA SECURITE ET PROTEGER LE BON
FONCTIONNEMENT DE L'APPAREIL.

72

LC-M3700
LC-M3710

Ë

R/C, LED Unit

H

G

F

E

Ë

KEY Unit

D

C

B

A

654321

73

LC-M3700
LC-M3710

Ë

MONITOR Unit-1/8

H

G

F

E

D

C

B

A

121110987654321

74

75

LC-M3700
LC-M3710

Ë

MONITOR Unit-2/8

H

G

F

E

D

C

B

A

121110987654321

76

77

LC-M3700
LC-M3710

Ë

MONITOR Unit-3/8

H

G

F

E

D

C

B

A

121110987654321

78

79

LC-M3700
LC-M3710

Ë

MONITOR Unit-4/8

H

G

F

E

D

C

B

A

121110987654321

80

81

LC-M3700
LC-M3710

Ë

MONITOR Unit-5/8

H

G

F

E

D

C

B

A

121110987654321

82

83

LC-M3700
LC-M3710

Ë

MONITOR Unit-6/8

H

G

F

E

D

C

B

A

121110987654321

84

85

LC-M3700
LC-M3710

Ë

MONITOR Unit-7/8 (LC-M3700)

H

G

F

E

D

C

B

A

121110987654321

86

87

LC-M3700
LC-M3710

Ë

MONITOR Unit-7/8 (LC-M3710)

H

G

F

E

D

C

B

A

121110987654321

88

89

LC-M3700
LC-M3710

Ë

H

G

F

MONITOR Unit-8/8

E

D

C

B

A

654321

90

LC-M3700
LC-M3710

Ë

INVERTER Unit-1

H

G

F

E

D

C

B

A

654321

91

LC-M3700
LC-M3710

Ë

H

G

F

INVERTER Unit-2

E

D

C

B

A

654321

92

LC-M3700
LC-M3710

Ë

INVERTER Unit-3

H

G

F

E

D

C

B

A

654321

93

LC-M3700
LC-M3710

Ë

H

G

F

INVERTER Unit-4

E

D

THERMISTOR

C

B

A

654321

94

LC-M3700
LC-M3710

Ë

AC INLET Unit

H

G

F

E

Ë

THERMISTOR Unit

D

C

B

A

654321

95

LC-M3700
LC-M3710

Ë

MAIN Unit-1/7

H

G

F

E

D

C

B

A

121110987654321

96

97

LC-M3700
LC-M3710

Ë

MAIN Unit-2/7

H

G

F

E

D

C

B

A

121110987654321

98

99

LC-M3700
LC-M3710

Ë

MAIN Unit-3/7

H

G

F

E

D

C

B

A

121110987654321

100

101

LC-M3700
LC-M3710

Ë

MAIN Unit-4/7

H

G

F

E

D

C

B

A

121110987654321

102

103

LC-M3700
LC-M3710

Ë

MAIN Unit-5/7

H

G

F

E

D

C

B

A

121110987654321

104

105

LC-M3700
LC-M3710

Ë

MAIN Unit-6/7

H

G

F

E

D

C

B

A

121110987654321

106

107

LC-M3700
LC-M3710

Ë

H

G

F

MAIN Unit-7/7

E

D

C

B

A

654321

108

LC-M3700
LC-M3710

Ë

SPEAKER-L Unit

H

G

F

E

Ë

SPEAKER-R Unit

D

C

B

A

654321

109

LC-M3700
LC-M3710

Ë

DC/DC Unit

H

G

F

E

D

C

B

A

121110987654321

110

111

LC-M3700
LC-M3710

Ë

INPUT-1 Unit

H

G

F

E

D

C

B

A

121110987654321

112

113

LC-M3700
LC-M3710

Ë

INPUT-2 Unit

H

G

F

E

D

C

B

A

121110987654321

114

115

LC-M3700
LC-M3710

Ë

PO WER Unit

H

G

F

E

D

C

B

A

121110987654321

116

117

LC-M3700
LC-M3710

Ë

PC I/F Unit-1/7

MAT6

IC400A

1
2

TC74LVX86FT

IC400B

4
5

TC74LVX86FT

IC400C

9

10

TC74LVX86FT

IC400D

12
13

TC74LVX86FT

IC19

Cap

OUT

Vdd

GNDNC

R3112N151A

IC2

OUT

Cap

Vdd

GNDNC

R3112N291A

+

C24
10uF/16V
C26

0.1uF

VCC

TEST

SCL

R1270 0^NU-R[M]
R1271 0^NU-R[L]
R1272 0
R1273 0
R1274 0
R1275 8.2K

VD+3.3

147

3

147

6

147

8

147

11

VD+1.8

1
2
34

C31

0.1uF

VD+3.3

1
2
34

C33 0.1uF

VD+3.3

R1285

8
7
6

10K

EEPROMWP
SCL4
SDA4I

R1203

100

R1204

100

-C1_INT5
SSYSTEM3

CSEN1_SH3
DO_HDISP6,7

DO_VSYNC6,7

VD+3.3

SM_RST3

MON_DET7
HPMUTE13

LMUTE3
SCL3O3
SDA3O3
AWCS_R3

AWCS_W3

EXTPORT63

-RST_PL7
HVSEL4

R17
33K

LED1

2

Grn

4 3

Red

SML-020MLT

*

VD+1.8

-RESET 2

PLT1

1

1

OG-502620R

PLT4

1

1

OG-502620R

MAT1
MAT2
MAT3

0.1uF

C922

LED0

LED1

VD+3.3

MAT4
MAT5

MAT62

H

G

F

E

D

リセット電圧1.5V

5

C30

0.047uF

C

5

C32

0.047uF

B

IC3

1

A

A0

2

A1

3

NC

4 5

GND SDA

AT24C128N-10SI-2.7

AGC_13
AGC_23

1

MON_DET

SCL3O
SDA3O

SCL4A

R1205

PLT2

1

1

OG-502620R

PLT5

1

1

OG-502620R

LUG1

SD00433-41

VD+3.3

MA3S137

AFT_23
AFT_13

PSEL_23
PSEL_13

NU-R2

47uF/6.3V

D[15..0]2,5

A[25..0]2,5

PLT3

1

1

OG-502620R

PLT6

1

1

OG-502620R

LUG2

SD00433-41

D50

C923

2

K2

3

R922
10K

+

1

PLT7

1

OG-502620R

LUG3

SD00433-41

1

A1

K1A2

VD+3.3

81

765

R652

EXBV8V103J

234

VD+3.3

D[15..0]

C531
47uF/6.3V

A[25..0]

1

LUG4

SD00433-41

2

K2

3

NMI

K1A2

1

A1

D51
MA3S137

LED1

SCL1_A
SDA1O

LED0

D15
D14

D13
D12
D11
D10
D9
D8
D7

D5
D4

D3
D2
D1
D0

R1206

+

1

LUG5

SD00433-41

R920 100

R921 100

VD+1.8

-RESET

TL89

1

0(1/10W)

C532

0.1uF

R1127 10K

C14

0.1uF

0.1uF
C22

0.1uF
C25

0.1uF
C27

0.1uF
C29

PWB1

RPCI-A007WJ△2

基板

FLASHWP2

HOTPLUG7

CLR_SW4

VD+3.3

CLR_SW

CCK

CCK2

C2

C1

0.1uF

0.1uF

207

208

AN7

AVSS

1

MD1

2

MD2

3

VCC

4

XTAL2

5

EXTAL2

6

VSS

7

NMI

8

IRQ0

9

IRQ1

10

IRQ2

11

IRQ3

12

IRQ4

13

PTB7

14

PTB6

15

PTB5

16

PTB4

17

PTB3

18

PTB2

19

VSS

20

PTB1

21

VCC

22

PTB0

23

PTA7

24

PTA6

25

PTA5

26

PTA4

27

VSS

28

PTA3

29

VCC

30

PTA2

31

PTA1

32

PTA0

33

VSS

34

D15

35

VCC

36

D14

37

D13

38

D12

39

D11

40

D10

41

D9

42

D8

43

D7

44

D6

45

VSS

46

D5

47

VCC

48

D4

49

D3

50

D2

51

D1

52

D0

A0A1A2A3VSSA4VCCA5A6A7A8A9A10

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

VSH3CORE

A0

A1

A2

10K^NU-R1[M]

R1291

R1284

10K^NU-R1[L]

SDA4O

C7 0.1uF

C6

0.1uF

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

CA

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AVCC

AVSS

MD3

MD4

MD5

DREQ0

DREQ1

RESETP

PTD0

PTD1

PTC0

PTC1

PTC2

PTC3

PTD2

VCC

0.1uF

C8

175

176

177

178

179

180

181

182

VSS

PTC7

PTC6

PTC5

PTC4

PTD3

SCPT7

IC1

SH-7709

RH-IX3270CEZZ

A11

A12

A13

VSS

A14

VCC

A15

A16

A17

A18

A19

A20

A21

VSS

A22

VCC

A23

VSS

A24

VCC

C34

0.1uF

A3

A4

A6

A8

A5

A7

B1

XHPSN30P08JS0^SCREW[L]

ビス

B2

XHPSN30P08JS0^SCREW[L]

ビス

B3

XHPSN30P08JS0^SCREW[L]

ビス

B4

XHPSN30P08JS0^SCREW[L]

ビス

B5

XHPSN30P08JS0^SCREW[L]

ビス

C35

0.1uF

A16D6A14

A15

A13

A11

A10

A12

A9

C36

C37

0.1uF

0.1uF

A23

A21

A24

A22

A19

A18

A20

A17

A25

174

VCC

RXD2

A25

PTK4RDWE0

EXTPORT5 3
EXTPORT4 3

X1
6MHz

156
155

154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

TXD0

RXD0

-RST_C1 3,5

TXD2 2
PCDVISEL 4

CTS2 2

TV_COL1 3
EXTPORT8 4
TV_COL2 3

RXD2 2
RTS2 2
XPWR_SV 3

RXD1
TXD1

21

34

150

R654

MAT1

MAT3
MAT4
MAT5
MAT6

MAT2

SDA_1
SDA3I

1

0.1uF

0.1uF

0.1uF

0.1uF

BREQ

0.1uF

TL17

1.8432MH 2

SH_ON 3
EXTPORT3 3
EXTPORT2 3

C1215pF

C1315pF

C17

C18

C19

C20

C21

470pF
CHECKER

C23

C28

-CS4

-CS0

470pF

SDA2I

-CS6

-CS5

VD+3.3

R1202 0

81

765

R10

EXBV8V103J

234

*

234

R19

EXBV8V103J

765

81

765

R29

EXBV8V103J

234

VD+3.3

EXBV8V103J

SDA4I

8 1

VD+3.3

-CS3

81

765

R11

234

MON_DET

EEPROMWP

-CS2 5

VD+3.3

R650 10K

FSTATUS 2

AWDATA 3
KOUTEI 3

ACL_SIG 3

-DEBUG

CASH
CASL

EVENODD 4
OVGA_OE 6

CKIO 5

EXTPORT7 3

-WAIT_C1 5

SRESET 3
RES_OUT3 3
ACL_SW 3
EXTPORT1 3

-RST_PLL 6
DAC_CLK 3
DAC_DATA 3

CASH 2
CASL 2

FLWP 2
RAS 2
WXGA_OE 6

TL96

CNA4

A1

A1

1

A2

A2

2

A3

A3

3

A4

A4

4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

FH12-30S-0.5SV-ICE

-CS0

-CS6

TL97

1

1

TXD0

RXD0

TL232
PAD2.0

1

SCL4A
SDA4O
SCL2O
SDA2O

TXD1

RXD1

VD+3.3

R1208
10K

SDA3_53,4

VD+5

11

C802 0.1uF
IC404

2

1A

5

2A

9

3A

12

4A

1

1OE

4

2OE

10

3OE

13

4OE

14

VCC

HD74HCT125T

VD+3.3

147

SDA2_5

SDA1O

SCL1_A

1Y
2Y
3Y
4Y

R877 10K

SDA2O
SCL2O

1.8432MH

C9 0.1uF

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

TXD2

SCK1

RD/WR

PTE7

TXD1

VSS

0.1uF

SCK0

CS0

TXD0

VCC

C38

-CS2

VSS

VCC

PTJ7

CKIO

PTH7

IRQOUT

CS2

CS3

CS4

CS5

CS6

CE2A

100

101

102

103

FLS_W 3

-WR/RD 2
DVIPDO 4
SCDT 4

-WEH 2,5

-WEL 2,5

-RD 2,5
DVIPD 4

PTJ6

EXTAL

XTAL

PTH6
CAP2

CAP1

PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
PTF7

PTG0
PTG1
PTG2

PTG3
PTG4
PTG5
PTG6
PTG7
PTH5

RESETM

WAIT
BREQ
BACK

PTE0

PTE1

PTE2

PTE3

PTE6

DACK1
DACK0

PTJ5

PTJ4

CASLH

CASLL
RAS2L
RAS3L

CE2B

104

VCC
VSS
VSS

VCC
VSS

VSS
VCC

MD0

VCC
VSS

VCC
VSS

CKE

VSS

RTS2

SCK2

RXD0

RXD1

WE1

PTK6

PTK7

-WR/RD

-RD

-WEL

-WEH

for ICE

VD+3.3 VD+3.3

C4 0.1uF-T

-CS4
A3
A4 A5
A7
A8
A11
A12
A15
A16
A19
A20
A23

-CS5

-CS6
D2
D3
D6
D7
D10
D11
D14
D15

-WEL

-WEH
CASL

-CS3
CASH

R1133 NU-R1

C908 0.1uF

IC53D

12
13

TC74LVX86FT

VD+3.3

R1059

3.9K

3
6
8
11

R340
10K

R20 NU-R1

R21 NU-0R

IC53C

9

10

TC74LVX86FT

C800 0.1uF

IC402

2

1A

5

2A

9

3A

12

4A

1

1OE

4

2OE

10

3OE

13

4OE

14

VCC

74LVX125MTC

R1062

R1061

3.9K

3.9K

C5 0.1uF-T

-ROMCS

147

1Y
2Y
3Y
4Y

-WR/RD

-CS2
NMI

-RESET

R924

4.7K

3
6
8
11

R1060

3.9K

8

A1
A2

A6
A9
A10
A13
A14
A17
A18
A21
A22
A0
D0
D1
D4
D5
D8
D9
D12
D13

-RD

FH12-30S-0.5SV-ICE

VD+3.3

R22
10K

R1058

4.7K

VD+5

SDA4I
SCL2_5
SDA2_5

CNB4

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5

A4

4

A4

A3

3

A3

A2

2

A2

A1

1

A1

-ROMCS

-CS0 2

TXD0_M 2

RXD0_M 2

TXD1_T 3

RXD1_T 3

VD+3.3

SDA_1 7
SCL1 7

SDA3I
SDA2I

SCL4
SDA4I
SCL2_5 3,4
SDA2_5 3,4

118

121110987654321

119

LC-M3700
LC-M3710

Ë

PC I/F Unit-2/7

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

RST#

RY/BY#

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

CE#
OE#

WE#

WP#
VPP

VD+3.3

C42

0.1uF

VD+3.3

TL128
PAD3.5

1

R656

Q12

34

E2C2

2

5

B2

B1

1

6

C1

E1

IMB3A

DTr1:PNP
DTr2:PNP

IC53A

147

TC74LVX86FT

81

R33

EXBV8V103J

R35

EXBV8V103J

765

R43

EXBV8V103J

234

765

R50

EXBV8V103J

234

765

R57

EXBV8V103J

234

765

R65

EXBV8V103J

234

765

234

81

765

234

81

EXBV8V103J

81

EXBV8V103J

81

EXBV8V103J

81

1
2

EXBV8V103J

R36

EXBV8V103J

R44

R51

R58

3

VD+3.3

81

765

R62

EXBV8V100J

234

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

D0
D1
D2
D3
D4
D5
D6
D7

D8
D9
D10
D11
D12
D13
D14
D15

A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11
A12
A13
A14
A15
A16

A17
A18
A19
A20
A21
A22
A23
A24

A25

29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45

26
28

11
12

14
13
15

4727

NCGND

CASH
CASL
RAS

-WR/RD

4.7K

FWMODEN

81

765

R34

234

81

765

234

81

765

234

81

765

234

81

765

234

CCKM

SSSS812-B-2B

S1

NORMAL

3

2

1A1A2A3A4

WRITE

TXD21
TXD0_M1
RTS21

RTS2CN5I
TXD2CN5I
CTS2CN5I
RXD2CN5I

VD+5

R1006

2.2K

Q103

2

2SC2412KQ

1 3

R1009

2.2K
R1012

1K

H

1.8432MH1

FLWP1

R40 68

C352

NU-C1

C353
NU-C1

X3

3 4
2

DSO751SV(1.8432M)

VD+3.3

R27
27K

OUTVDC

CntlGND

G

FLASHWP1

147

IC53B

4
5

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21

TC74LVX86FT

VD+3.3

C43

0.1uF

D[15..0]1,5

F

A[25..0]1,5

E

C350

0.1uF

6

25

A0

24

A1

23

A2

IC27

22

A3

21

A4

20

A5

19

A6

18

A7

8

A8

7

A9

6

A10

5

A11

4

A12

3

A13

2

A14

1

A15

48

A16

17

A17

16

A18

9

A19

10

A20

37

VCC

46

GND

LH28F320BFE-PTTL80

FSTATUS1

D

C

B

-RESET1

VD+3.3

-RD1,5

-CS01

C361

47uF/6.3V

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10

+

C51

0.1uF

C52

0.1uF

C53

0.1uF

21
22
23
24
27
28
29
30
31
32

1
6

25

11
15
16
19
20
36
40

A1
A2
A3
A4

IC28

A5
A6
A7
A8
A9
A10

VCC
VCC
VCC

NC
NC
NC
NC
NC
NC
NC

MSM51V18165F

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

LCAS

UCAS

2

DQ0

3

DQ1

4

DQ2

5

DQ3

7

DQ4

8

DQ5

9

DQ6

10

DQ7

41

DQ8

42

DQ9

43
44
46
47
48
49

17

WE

18

RAS

35
34
33

OE

26

VSS

45

VSS

50

VSS

CASH1
CASL1
RAS1

-WR/RD1

-WEL1,5

-WEH1,5

A

VD+3.3

C924

0.1uF
1

2

03/04/11

CTS21

RXD21

RXD0_M1

234

EXBV8V103J

8 1

765

0.1uF^NU-C1[L]

2.2uF/25V(2125)^NU-C2125[L]

RTS2CN9I
TXD2CN9I
CTS2CN9I
RXD2CN9I

2.2uF/25V(2125)^NU-C2125[M]

C8030.1uF^NU-C1[M]

C806

2.2uF/25V(2125)^NU-C2125[M]

R1011 33K

IC423A

14

74LCX08MTC

3

7

VD+3.3

14

74LCX08MTC

6

7

IC423C

14

8

7
14

11

7

R1269

-RESET1

VD+3.3

C926

C929

IC405

C804

1

VDD

2

C1+

3

VCC

4

C1-

5

C5+

6

C5-

7

Din1

8

Din2

9

Rout1

10 11

Rout2 Rin2

uPD4721G^NU-uPD[M]

CCK 1

IC423B

CTS2CN5I

4

CTS2CN9I

5

74LCX08MTC

RXD2CN9I

9

RXD2CN5I

10

IC423D

74LCX08MTC

RXD0CN1I

12
13

2
3
5

6
11
10
14
13

1
15

2.2uF/25V(2125)^NU-C2125[L]
IC425

C927

1

VDD

2

C1+

3

VCC

4

C1-

5

C5+

6

C5-

7

Din1

8

Din2

9

Rout1

10 11

Rout2 Rin2

uPD4721G^NU-uPD[L]
R77

1
2
3
4 5

VD+5BKVD+5BK

20

C4+

19

GND

18

C4-

17

VSS

16

STBY

15

VCHA

14

Dout1

13

Dout2

12

Rin1

CSEN13
CSEN23

SRST3

FLASH_W3

TXD0CN1I
RXD0CN1I

SMPOW3
SENCE3

VD+5BK

R1207

NU-R1^0[M]

VD+5BK

168

IC424

4

1A

1Y

1B

VCCGND

7

2A

2Y

2B

9

3A

3Y

3B

12

4A

4Y

4B
A/B

G

STBY

VCHA

Dout1
Dout2

1

8

2

7

3456

NU-RJ^EXBV8VR00J[L]

C805

2.2uF/25V(2125)^NU-C2125[M]

C807

VD+5BK

74ACT157MTC

VD+5BKVD+5BK

20

C4+

19

GND

18

C4-

17

VSS

16
15

2.2uF/25V(2125)^NU-C2125[L]

14
13
12

Rin1

8
7
6

2.2uF/25V(2125)^NU-C2125[M]

132

D54

MA3120WA^NU-D1[M]

R1101

8 1

2

7

3

6

4

5

EXBV8V560J

R1102

8 1

2

7

3

6

4

5

EXBV8V560J

234

R1268

EXBV8V103J

8 1

765

C850

100uF/6.3V(PXA)

TXD2CN9I
TXD2CN5I

TXD0CN1IRXD2CN5I
RTS2CN9I
RTS2CN5I

C925

0.1uF

C928

2.2uF/25V(2125)^NU-C2125[L]

C930

R1209 100

132

D55

D56

MA3120WA^NU-D1[M]

MA3120WA^NU-D1[M]

CSEN1CN
CSEN2CN

SRSTCN
FLASHWCN

CCKM

TXD0CN

RXD0CN
SMPOWCN
SENCECN

VD+1.8

+

100uF/6.3V(PXA)

SMPOW3

R1210 100

132

132

D57

MA3120WA^NU-D1[M]

VD+5BK

C847
100uF/6.3V

VD+3.3

C851

MAT61

R1211 100

R927

100^NU-R1[M]

R929

100^NU-R1[M]

R928

100^NU-R1[M]

R930

100^NU-R1[M]

CN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

CGP4714-0101

VD+5

+

VA+5

+
C849
100uF/6.3V

+

V+6

+

C852

47uF/16V

FWMODEN

R1212 100

FB50 BLM21BB201SN1^NU-BLM21[M]

1 2

BLM21BB201SN1^NU-BLM21[M]
FB52

1 2

FB51 BLM21BB201SN1^NU-BLM21[M]

1 2

FB53

1 2

BLM21BB201SN1^NU-BLM21[M]

VD+5BK

C853

0.1uF

R1292 4.7K

CN5

1
6
2
7
3
8
4
9
5

RXD2CN
RTS2CN
TXD2CN
CTS2CN

POWER CON

JEY-9P-1A3F^NU-DSUB9[M]

10 11

CN9

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

S20B-PHDSS

120

121110987654321

121

LC-M3700
LC-M3710

Ë

PC I/F Unit-3/7

R1279 NU-RJ^EXBV8V680J[M]

CN7

1

A1

2

A2

3

H

G

A3
A4

FH12-40S-0.5SV

1

TL210

SUB_SC

SUB_SY

SUB_V

SUB_FBLK
SUB_Cb

SUB_Y

SUB_Cr

MAIN_R

MAIN_G

MAIN_B

TL209

1

ACL_SWCN
ACL_SIG

MAIN_R 4

MAIN_G 4

MAIN_B 4

MAIN_HD

MAIN_VD

MAIN_HD 4
MAIN_VD 4

ACL_SIG 1

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

F

CN6

1

1

2

A1

A1

2

3

A2

A2

3

4

A3

A3

4

5

A4

A4

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

E

D

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

FH12-50S-0.5SV

SCL2_5

SCL3_5

R1080 0
R1081 0

R947

R1236 0

C

AWCS_R1
AWCS_W1
HPMUTE11
RES_OUT31
LMUTE1

TV_COL11

AWCS_RCN
AWCS_WCN
D_CLKCN
AWDATACN
D_DATACN

SH_ONCN

IO_STB
SRESETCN

LMUTECN
HPMUT1CN
RESO3CN

5
6
7
8 1

81
R950

EXBV8V682J

KOUTEI 1
SDA1_5 7

SCL1_5 7
SDA2_5 1,4
SCL2_5 1,4
SDA3_5 1,4

SMPOW 2
SENCE 2

CSEN2 2

TV_CL1CN
TV_CL2CN

4
3
2

EXBV8V560J

8 1
7
6
5

765

EXBV8V682J

234

RXD1_T 1
TXD1_T 1

AGC_1 1
AGC_2 1
AFT_2 1
AFT_1 1

R1235

2
3
4

EXBV8V560J

81

765

R951

234

C813

0.1uF

B

C814

0.1uF

TV_COL21
ACL_SW1
SRESET1
XPWR_SV1
SM_RST1
FLS_W1
SH_ON1

A

CSEN1_I

81

765

R955

EXBV8V682J

234

OV1_V 6
OV1_H 6

VA+5

L27

C945

330pF(CH)^NU-C1[M]

R1222

75(1/10W)^NU-R2[M]
R1224

75(1/10W)^NU-R2[M]

8

Vcc

7

G2

6

Y1

3
6
8
11

BLM31PG601SN1^NU-L3216[M]

330pF(CH)^NU-C1[M]

C955

C960

330pF(CH)^NU-C1[M]

R1226

C964

330pF(CH)^NU-C1[M]

TL242

CSEN2

D_CLKCN
D_DATACN

SCL3_5

SDA3_51,4

-RST_C11,5

1

CSEN2 2
INPUT_CK 4

NU-R1^4.7K[M]

R1216
0^NU-R1[M]

SUB_FBLK

SUB_Cb

SUB_Y

SUB_Cr

VD+3.3

R1079

8 1

2

7

3

6

4

5

EXBV8V560J

R1234

8 1

2

7

3

6

4

5

EXBV8V560J

VD+5

74VHCT244AMTC

20

IC408

2

18

1Y1

1A1

4

16

Vcc

1Y2

1A2

6

14

1Y3

1A3

8

12

1Y4

1A4

11
13
15
17

19

11
13
15
17

19

1

2
4
6
8

1

IC410

2A1
2A2
2A3
2A4

1G
2G

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

1G
2G

9

2Y1

7

2Y2

5

2Y3

3

2Y4

GND

10

VD+5

74VHCT244AMTC

20

18

1Y1

16

Vcc

1Y2

14

1Y3

12

1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

GND

10

CSEN1_I

EXTPORT4 1
EXTPORT2 1
EXTPORT3 1
EXTPORT1 1

EXTPORT6 1
EXTPORT7 1
EXTPORT5 1
SPDIF 4

AWCS_RCN
AWCS_WCN
HPMUT1CN
RESO3CN
LMUTECN

TV_CL1CN

TV_CL2CN
ACL_SWCN
SRESETCN

SRST
SH_ONCN

PSEL_1 1
PSEL_2 1
SSYSTEM 1
AWDATA 1

R1085
10K

XPWR_SVO 4
SRST 2
FLASH_W 2

CSEN1 2

R1131
10K

R1132 100

R1083
1K

IO_STB

VD+5BK

DAC_CLK1
DAC_DATA1

SDA3O1
SCL3O1

R1084
10K

C905

0.1uF(K)^560pF[M]

IC419A

1

A

2

B

14

VCC

C

15

R/C

GND

3

CLR

74VHC123AMTC

0^NU-R1[M]

0^NU-R1[M]

R1223
0^NU-R1[M]

R1225
0^NU-R1[M]

CSEN1_SH 1

Q
Q

L23

R1217

MLF1608A3R3KT^NU-L1608[M]

R1221

MLF1608A3R3KT^NU-L1608[M]

IC419B

9

A

10

B

6

C

7

R/C

11

CLR

74VHC123AMTC

D73

1SS400

1 2

13
4

16

C904 0.1uF

8

VD+5

C916 0.1uF

MLF1608A3R3KT^NU-L1608[M]

75(1/10W)^NU-R2[M]

VCC

GND

R1218 75(1/10W)^NU-R2[M]

R1219

L24

L25

Q
Q

75(1/10W)^NU-R2[M]

L26

MLF1608A3R3KT^NU-L1608[M]

R1227

NU-R2

R1228

NU-R2

R1231

NU-R2

5
12

16
8

C913 0.1uF

1

G1

2

A1

3

Y2

4 5

GND A2

IC420
NC7WZ126K

IC422

2

1Y

1A

5

2Y

2A

9

3A

3Y

12

4A

4Y

1

1OE

4

2OE

10

3OE

13

4OE

14

VCC

HD74HCT125T

VA+5-VPC

C9780.1uF^NU-C1[M]

TL234

1

C952

0.22uF^NU-C1[M]

C954

NU-C2125

C956

0.22uF^NU-C1[M]
C959

NU-C2125

0.22uF^NU-C1[M]
C961

C962
NU-C2125

VD+5

R1110

R1213 75(1/10W)^NU-R2[M]
R1214 75(1/10W)^NU-R2[M]
R1215 75(1/10W)^NU-R2[M]

SUB_SC
SUB_SY
SUB_V

+

C977
33uF/10V^NU-CE5[M]

0.22uF^NU-C1[M]
C965

R1229 100^NU-R1[M]

R925
NU-R1^4.7K[M]

1500pF^NU-C1[M]

R1232 100^NU-R1[M]
R1233 100^NU-R1[M]

VD+3.3

+

0.068uF^NU-C1[M]
C963

C967

C966

390pF^NU-C1[M]

C971
47uF/6.3V^NU-CE5[M]

IC427

5

BUS1

LTC1694^NU-LTC[M]

SDA3_5
SCL3_5

C931

0.68uF^NU-C1[M]
C933

0.68uF^NU-C1[M]

C936

0.68uF^NU-C1[M]

C937

10uF(3216)^NU-C3216[M]

C939
1500pF^NU-C1[M]

C942
390pF^NU-C1[M]

C946

C947

+

+

100uF/6.3V^NU-CE6[M]

100uF/6.3V^NU-CE6[M]

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1500pF^NU-C1[M]

0.047uF^NU-C1[M]

TL243

VD+5

1

VCC

2

GND

34

NCBUS2

SDA3_5 1,4

SCL3_5 4

C934

NU-C2125

C932

0.68uF^NU-C1[M]

C935

0.68uF^NU-C1[M]

C948

0.1uF^NU-C1[M]

80

VREF

FB1IN

GNDAI

VSUPAI

AISGND

B1/CB1IN
G1/Y1IN
R1/CR1IN
B2/CB2IN
G2/Y2IN
R2/CR2IN
ASGF
NC
VSUPCAP
VSUPD
GNDD
GNDCAP
SCL

VPC3230D^NU-VPC[M]

SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
FFWE
FFRSTW
FFRE
FFOE
CLK20

GNDPA

VSUPPA

LLC2

LLC1

VSUPLLC

252627282930313233343536373839

C974

C972

C975

1

0.1uF^NU-C1[M]
C976

CIN

VIN1

VIN2

VIN3

VIN4

VOUT

IC426

GNDLLCY7Y6Y5Y4

GNDY

C973

0.068uF^NU-C1[M]

C981

100pF^NU-C1

C982

100pF^NU-C1

C983

100pF^NU-C1

TL233

1

10uF(3216)^NU-C3216[M]
C938

1500pF^NU-C1[M]

390pF^NU-C1[M]

656667686970717273747576777879

VRT

GNDF

ISGND

VSUPF

I2CSEL

VSTBY
FPDAT

MSY/HS

FSY/HC

VSUPSY

GNDSY

VSUPC

VSUPYY3Y2Y1Y0

40

0.068uF^NU-C1[M]

C940

C943

0.047uF^NU-C1[M]

100uF/6.3V^NU-CE6[M]

64

ASGF

63

XTAL2

62

XTAL1

61

NC

60

CLK5

AVO

INTLC

GNDC

YY1
YY2 OVG2

YY4
YY5
YY6
YY7

1

59
58

1

57

VS

56
55
54
53
52
51
50

C0

49

C1

48

C2

47

C3

46
45
44

C4

43

C5

42

C6

41

C7

R934 EXBV8V680J

6
7

7

8

8

R936 EXBV8V680J

6

6

7

7

8

8

YY0
YY1
YY2
YY3

R1280

YY4
YY5
YY6
YY7

R1281

UV0
UV1
UV2
UV3

R1282 NU-RJ^EXBV8V680J[M]

UV4
UV5
UV6
UV7

R1283 NU-RJ^EXBV8V680J[M]

C949

TL240

TL241

3456
2
1

45
3
2
1

6

3456

7

2

7

8

1

8

+

C950

C970

0.068uF^NU-C1[M]

OVG0YY0

45

OVG1

3
2

OVG3YY3

1

OVG4

45

OVG5

3

OVG6

2

OVG7

1

45
3
2
1

1pF^NU-C1[M]
C957

1

8

1

8

2

7

2

7

3

6

3456

45
1

8

1

8

NU-RJ^EXBV8V680J[M]

2

7

2

7

3

6

3

6

45

45

1

8

NU-RJ^EXBV8V680J[M]

1

8

2

7

2

7

3

6

3456

45
1

8

1

8

2

7

2

7

3

6

3456

45

OV1_V 6
OV1_H 6

OV1_VAL 6

R1220 1K^NU-R1[M]

C951

+

10uF/16V^NU-CE4[M]

C953
2200pF^NU-C1[M]

1pF^NU-C1[M]

C958

X7

2,3

1,4

20.25MHz^NU-CX5[M]

C969 0.047uF^NU-C1[M]

C968

1500pF^NU-C1[M]

UV0
UV1
UV2 OVR2

UV4
UV5
UV6
UV7

OVG[7..0] 6

R1237
10K

TL235

1

R940 EXBV8V680J

45

45

3

6

6

3

2

7

7

2

1

8

8

1

R941 EXBV8V680J

45
3

6

3456

2

7

2

7

1

8

1

8

TL244

1

TL239

1

OVR0
OVR1

OVR3UV3

OVR4
OVR5

OVR6

OVR7

TL237

TL236

TL238

1

1

1

OV1_V

OV1_V 6

OV1_H

OV1_H 6

OV1_VAL 6

R1230
NU-R1

OV1_ACT 6

OVR[7..0] 6

OV1_VCLK 6

122

121110987654321

123

LC-M3700
LC-M3710

Ë

PC I/F Unit-4/7

SPDIF3

12

C128

0.33uF(PF)

330pF(CH)

C127
100pF

109

110

111

CLKIN

XCLKIN

SYNCIN1

DSYNC/DIVOUT

DGNDPLLTTL

DVCCPLLTTL
AGNDADREF

DVCCADTTL
DGNDADTTL

DGNDADTTL
DVCCADTTL

GA2

GA3

GA4

72

LC0GI1A2

LC0GI1A4

LC0GI1A3

VA+5-PLL

C125

0.1uF

EVEN/ODD

XTLOAD

HOLD

SOGOUT

XUNLOCK

DPGND

1/2CLK

1/2XCLK

XCLK

AVCCAD3

VRB

DVCCAD3

DVCCAD

DGNDAD3

AGNDAD3
DGNDAD3

SCDT1
DVIPD1
DVIPDO1

108
107
106
105
104
103
102
101
100
99

CLK

98
97
96
95
94
93
92
91
90
89
88

GB7

87

GB6

86
85

GB5

84

GB4

83

GB3

82

GB2

81

GB1

80
79
78

GB0

77
76
75

GA7

74

GA6

73

GA5

VD+5-ADC

R1245

EXBV8V560J^NU-RJ[L]

TL84

1

VD+5-ADC

C776

NU-PXA

LCBI1A7
LCBI1A6
LCBI1A5
LCBI1A4

LCBI1A3
LCBI1A2
LCBI1A1
LCBI1A0

L1

OV0_H 6
OV0_V 6

PC_C3 6

R1243

EXBV8V103J

BLM31PG601SN1

L2

BLM31PG601SN1

C83

+

0.1uF

PC_HH

PC_C

C84

33uF/10V

8 1
7
6
5

EXBV8V103J

CN8

S18B-PHDSS

R1076

C143

0.1uF

C145

0.1uF

2
3
4

1
2
3
4
5
6
7
8
9
10
11
12

MAIN_G2

13
14
15

MAIN_B2

16

MAIN_R2

17
18

H

V+6

C81

0.01uF

1SS355

IC7
PQ050DZ01Z

1

VINVCVO

D20

12

GND

5

VA5REGO

3
2

C777

0.1uF

G

F

C921 100uF/6.3V(PXA)

+

E

D

MAIN_HD3
MAIN_VD3

PCDVISEL1

HVSEL1

DVI-A-H
PC_V
DVI-A-V

PC_C

PC_HH
PC_VV

R1248 0
R1249 NU-R1
R1250 0
R1251 NU-R1

C907

0.1uF

11
10
14
13

15

VD+3.3

168

IC411

2

1Y

1A

3

1B

VCCGND

5

2A

2Y

6

2B
3A

3Y
3B
4A

4Y
4B

1

A/B
G

74LCX257MTC

PC_HHPC_H
PC_VV

MAIN_VD3
MAIN_HD3

TL218

TL219

TL220

1

1

1

4
7
9
12

234

8 1

765

C

D9

12

1SS355

IC8

C82

0.01uF

PQ033EZ01

1

VI

2

VC

VADJ

GND

5

ROUT0

OGOUT0

BOUT0

3

VO

4

TL227

VA+3.3AD

C149

0.1uF

TL228

TL229

1

1

1

+

C564
100uF/6.3V(PXA)

VA+5

+

C79

B

A

47uF/6.3V

ROUT07

OGOUT07

BOUT07

RI1A[7..0]6

RI1B[7..0]6

VA+5-AMP

+

C144

47uF/10V(PXA-5)

VA+5-PLL

+

C146
33uF/10V

MAIN_R3

MAIN_G3

MAIN_B3

PC_G

PC_B
PC_R

PC_H
PC_V

PC_C
R1240 NU-R1
R1089 100
R1247 100
R1289 NU-R1
R1290 NU-R1

VD+5

L4

BLM31PG601SN1

47uF/6.3V

SDA2_51,3
SCL2_51,3

RI1A0

RI1A1

RI1A2

RI1A3

RI1A4

RI1A5

RI1A6

RI1A7

RI1B0
RI1B1

6

RI1B2

7

RI1B3

RI1B4
RI1B5
RI1B6
RI1B7

7

8

8

R965
EXBV8V680J

R968

6
7

7

8

8

EXBV8V680J

EXTPORT8 1
CLR_SW 1
INPUT_CK 3
SCL3_5 3
SDA3_5 1,3

XPWR_SVO3

VD+5-ADC

+

C96

VA+5-AMP
VA+3.3AD

R959
EXBV8V680J

45
3

6

3456

2

7

2

7

1

8

8

1

45
3

6

3456

2

7

2

7

1

8

1

8

R962
EXBV8V680J

45
3

3456

2

2

1

1

LCRI1B4

45

LCRI1B5

3

3456

LCRI1B6

2

2

LCRI1B7

1

1

C115

0.1uF

R867

MAIN_R2

R868

MAIN_G2

R869

MAIN_B2
VA+5-AMP

DVI-A-R
DVI-A-G
DVI-A-B

NU-R1^0[L]

NU-R1^0[L]

NU-R1^0[L]

D85
MA3S137

R745 0
R747 0
R749 0

BOUT0
ROUT0

C110

0.1uF

C112

0.1uF
C111

0.1uF

C113
1uF(K)

C114

0.1uF
C767

+

NU-PXA

C116

0.1uF

R1286

NU-R1^0[M]

R1287

NU-R1^0[M]

R1288

NU-R1^0[M]

1

2

D86

A1

K2

MA3S137

K1A2

3

R1276
R1277
R1278

R1239

R1241 NU-R1
R1242 NU-R1
R1244 NU-R1
R1246 NU-R1

I2C=1001000r

ANLG_G
ANLG_B
ANLG_R

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

150(1/10W)
150(1/10W)
150(1/10W)

R96

150(1/10W)

R88

150(1/10W)

R80

150(1/10W)

1

2

A1

K2

K1A2

3

C562

0.1uF
C563

0.1uF

ANLG_SOG

ANLG_R
ANLG_G
ANLG_B

ANLG_SOG

OGOUT0

VA+5-AMP

B/CbOUT
ADDRESS
R/CrOUT
NC
NC
XPOWER SAVE
DGNDREG
DVCCREG
SDA
SCL
XSENABLE
SEROUT
3WIRE/IIC
DPGND
AVCCADREF
AVCCAD3
VRT
DVCCAD3
DVCCADTTL
DGNDADTTL
RA0
RA1
DGNDAD3
RA2
RA3
RA4
RA5
RA6
AGNDAD3
DGNDAD3
RA7
DVCCADTTL
DGNDADTTL
RB0
RB1
RB2

VD+5-ADC

C78

D87
MA3S137

C565

0.1uF

0.1uF

C70

0.1uF

C62

0.1uF

2

K2

C979

0.1uF

142

143

144

G/YOUT

AGNDAMPR

DAC TEST OUT

1

A1

K1A2

3

C138 0.1uF

140

141

R/CrIN2

AVCCAMPR

138

139

R/CrIN1

136

137

DPGND

B/CbIN2

AGNDAMPB

C137 0.1uF

134

135

SOGIN2

AVCCAMPB

132

133

B/CbIN1

C136 0.1uF

130

131

DPGND

SOGIN1

C135 0.1uF

C134 0.1uF

128

129

R/CrCLP

B/CbCLP

C133 0.1uF

126

127

G/YIN2

G/YCLP

AGNDAMPG

VA+5-AMP

C132

1uF(K)

123

124

125

G/YIN1

AGNDIR

AVCCAMPG

122

DPGND

D82
MA3S137

D83
MA3S137

D84
MA3S137

R133

3K(1%)

C131

120

121

IREF

AVCCIR

0.1uF

117

118

119

RC1

RC2

IC4
CXA3506R

RB3

RB4

RB5

RB6

RB7

DVCCADTTL

DGNDAD3

DGNDADTTL

BA0

BA1

BA2

BA3

BA4

DGNDAD3

BA5

BA6

BA7

DVCCADTTL

DGNDADTTL

BB0

BB1

BB2

DGNDAD3

BB3

BB4

BB5

LCBI1B1

LCBI1B2

LCBI1B4

LCBI1B3

BB6

LCBI1B5

LCBI1B6

LCBI1B7

3738394041424344454647484950515253545556575859606162636465666768697071

0.1uF

LCBI1A4

LCBI1A3

LCBI1A5

LCBI1A6

C118

LCBI1A7

LCBI1B0

C117 0.1uF

LCBI1A1

LCBI1A0

LCBI1A2

2

K2

K1A2

3

2

K2

K1A2

3

2

K2

K1A2

3

D78 1SS380

R132

3.3K(1%)

C566

C130
100pF

114

115

116

DVCCPLL

DGNDPLL

AVCCVCO

AGNDVCO

BB7

DVCCADTTL

DGNDAD3

DGNDADTTL

C119 0.1uF

LC0GI1A0

1

A1

1

A1

1

A1

C126
1uF(K)

112

113

CLPIN

SYNCIN2

GA0

GA1

LC0GI1A1

6
7
8

TL225

TL202

1

+

C122

1uF(K)

C121

0.1uF

C120

0.1uF

6
7
8

EXBV8V680J

6
7
8

EXBV8V680J

1

6
7
8

OVCLK6
OV0_H6
OV0_DE6
OV0_V6

TL245

R967

7
8

R970

7
8

45
3
2
1

1

LC0GI1A7
LC0GI1A6
LC0GI1A5

3456
2
1

3456
2
1

45
3
2
1

SDA2_51,3
SCL2_51,3

TL221

TL83

1

1

R128 10
R732 NU-R1

0.1uF
C123

LC0GI1B7
LC0GI1B6

LC0GI1B5
LC0GI1B4
LC0GI1B3
LC0GI1B2
LC0GI1B1

LC0GI1B0

BI1A7

45

BI1A6

3

BI1A5

2

BI1A4

1

BI1A3

45

BI1A2

3

BI1A1

2

BI1A0

1

R1238

6
7

7

8

8

EXBV8V560J^NU-RJ[L]

OV0_H

R1109 0

VD+5-ADC

VA+3.3AD

0.1uF
C124

LC0GI1B7
LC0GI1B6
LC0GI1B5
LC0GI1B4

EXBV8V680J

LC0GI1B3
LC0GI1B2
LC0GI1B1
LC0GI1B0

EXBV8V680J

BI1A[7..0] 6

DVI-D-DE
DVI-D-H
DVI-D-V

45
3

3456

2

2

1

1

OV0_CLP 6
OV0_HSNR 6

EVENODD 1
OV0_PDEN 6

OVCLK 6

R960

OGI1B7

45

OGI1B6

3

6

3456

OGI1B5

2

7

2

7

OGI1B4

1

8

1

8

R963

OGI1B3 OGI1A3

45

OGI1B2

3

6

3456

OGI1B1

2

7

2

7

OGI1B0

1

8

1

8

LCBI1B7
LCBI1B6
LCBI1B5
LCBI1B4

LCBI1B3
LCBI1B2
LCBI1B1
LCBI1B0

R966

6

6

7

7

8

8

EXBV8V680J

R969

6
7

7

8

8

EXBV8V680J

DVI-D-CK

OGI1B[7..0] 6

LC0GI1A7
LC0GI1A6
LC0GI1A5
LC0GI1A4

LC0GI1A3
LC0GI1A2
LC0GI1A1
LC0GI1A0

45

45

3

3

2

2

1

1

45
3

3456

2

2

1

1

BI1B7
BI1B6
BI1B5
BI1B4

BI1B3
BI1B2
BI1B1
BI1B0

RI1B7
RI1B6
RI1B5
RI1B4

RI1B3
RI1B2
RI1B1
RI1B0

OGI1B7
OGI1B6
OGI1B5
OGI1B4

OGI1B3
OGI1B2
OGI1B1
OGI1B0

BI1B7
BI1B6
BI1B5
BI1B4

BI1B3
BI1B2
BI1B1
BI1B0

RI1A7
RI1A6
RI1A5
RI1A4

RI1A3
RI1A2
RI1A1
RI1A0

OGI1A7
OGI1A6
OGI1A5
OGI1A4

OGI1A3
OGI1A2
OGI1A1
OGI1A0

BI1A7
BI1A6
BI1A5
BI1A4

BI1A3
BI1A2
BI1A1
BI1A0

DVI-A-R
DVI-A-G
DVI-A-B
DVI-A-V
DVI-A-H

R1129
10K

R961

6
7

7

8

8

EXBV8V680J

R964

6
7

7

8

8

EXBV8V680J

R1130
10K

45
3

3456

2

2

1

1

45
3

3456

2

2

1

1

BI1B[7..0] 6

OGI1A7
OGI1A6
OGI1A5
OGI1A4

OGI1A2
OGI1A1
OGI1A0

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

CN11

FH16-80S-0.3SHW^NU-FH80[L]

OV0_SOG 6
OV0_HSC2 6

OGI1A[7..0] 6

124

121110987654321

125

LC-M3700
LC-M3710

Ë

PC I/F Unit-5/7

A[25..0]1,2

H

G

D[15..0]1,2

F

E

D

C

B

A

-RST_C11,3

-WAIT_C11

-C1_INT1
CKIO1

-CS21

-RD1,2

-WEL1,2

-WEH1,2

SDD64
SDD65
SDD66
SDD67

SDD68
SDD69
SDD70
SDD71

SDD72
SDD73
SDD74
SDD75

SDD76
SDD77
SDD78
SDD79

SDD80
SDD81
SDD82
SDD83

SDD84
SDD85
SDD86
SDD87

SDD88
SDD89
SDD90
SDD91

SDD92
SDD93
SDD94
SDD95

SDD96
SDD97
SDD98
SDD99

SDD100
SDD101
SDD102
SDD103

SDD104
SDD105
SDD106
SDD107

SDD108 SDD44
SDD109
SDD110
SDD111

SDD112
SDD113
SDD114
SDD115

SDD116
SDD117
SDD118
SDD119

SDD120
SDD121
SDD122
SDD123

SDD124
SDD125
SDD126
SDD127

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15

26

BA_0

25
24

139

23
138
245

22
137
244

21
136
243
342

20
135
242
341
134
241
340
431
133
240
339
430

144

28
143
250

27
142
249
348
141
248
347
247
346
437
345
436

211
140
246

145
252

251
349
350

289

76

77

78

79
190

80

81

295
389
388
292

386
291
385
290

82

83
194

84

85

86
197
198

90
200
301
394

480
393
392
296

472
473
387
475

476
390
556
478

192
294
191
293

189
188
187
384

391
479
481
396

395
302
201

91

199
300
299
196

298
195 284
297
193

IC25A

BA_1
BA_2
BA_3
BA_4
BA_5
BA_6
BA_7
BA_8
BA_9
BA_10
BA_11
BA_12
BA_13
BA_14
BA_15
BA_16
BA_17
BA_18
BA_19
BA_20
BA_21
BA_22
BA_23
BA_24
BA_25

BD_0
BD_1
BD_2
BD_3
BD_4
BD_5
BD_6
BD_7
BD_8
BD_9
BD_10
BD_11
BD_12
BD_13
BD_14
BD_15

XRESET
BWAIT
BINT

BCLK
XBCS

RD
XBWE_0
XBWE_1

SDD_64
SDD_65
SDD_66
SDD_67

SDD_68
SDD_69
SDD_70
SDD_71

SDD_72
SDD_73
SDD_74
SDD_75

SDD_76
SDD_77
SDD_78
SDD_79

SDD_80
SDD_81
SDD_82
SDD_83

SDD_84
SDD_85
SDD_86
SDD_87

SDD_88
SDD_89
SDD_90
SDD_91

SDD_92
SDD_93
SDD_94
SDD_95

SDD_96
SDD_97
SDD_98
SDD_99

SDD_100
SDD_101
SDD_102
SDD_103

SDD_104
SDD_105
SDD_106
SDD_107

SDD_108
SDD_109
SDD_110
SDD_111

SDD_112
SDD_113
SDD_114
SDD_115

SDD_116
SDD_117
SDD_118
SDD_119

SDD_120
SDD_121
SDD_122
SDD_123

SDD_124
SDD_125 SDD_61
SDD_126
SDD_127

CVIC2

MCLK

SDMODE0
SDMODE1

XRAS
XCAS

XWE

DQM_0
DQM_1
DQM_2
DQM_3

DQM_4
DQM_5
DQM_6
DQM_7

SDA_0
SDA_1
SDA_2
SDA_3

SDA_4
SDA_5
SDA_6
SDA_7

SDA_8

SDA_9
SDA_10
SDA_11

SDA_12
SDA_13

SDD_0

SDD_1

SDD_2

SDD_3

SDD_4

SDD_5

SDD_6

SDD_7

SDD_8

SDD_9

SDD_10
SDD_11

SDD_12
SDD_13
SDD_14
SDD_15

SDD_16
SDD_17
SDD_18
SDD_19

SDD_20
SDD_21
SDD_22
SDD_23

SDD_24
SDD_25
SDD_26
SDD_27

SDD_28
SDD_29
SDD_30
SDD_31

SDD_32
SDD_33
SDD_34
SDD_35

SDD_36
SDD_37
SDD_38
SDD_39

SDD_40
SDD_41
SDD_42
SDD_43

SDD_44
SDD_45
SDD_46
SDD_47

SDD_48
SDD_49
SDD_50
SDD_51

SDD_52
SDD_53
SDD_54
SDD_55

SDD_56
SDD_57
SDD_58
SDD_59

SDD_60
SDD_62

SDD_63

XCS

NC3
NC2
NC1

179

440
416
537

92
202

57
170
371
274

272
369
55
168

273
370
56
169

51
164
269
367

270
165
52
271

166
53
368
457

54
167

61
63
64
65

66
67
178
68

376
463
375
279

278
277
173
275

69
70
181
71

72
73
74
75

383
288
287
286

285
379
378
377

276
459
372
373

460
374
461
541

281
280
177
176

175
174
62
172

464
466
380
467

381
382
469
470

186
185
184
183

182
180

282

R692 0
R694 0

R687 NU-R1

R693 0
R695 0

VD+3.3CV

R688 0

R691 NU-R1

DQM0
DQM1
DQM2
DQM3

DQM4
DQM5
DQM6
DQM7

SD_BA0
SD_BA1

SDA0
SDA1
SDA2
SDA3

SDA4
SDA5
SDA6
SDA7

SDA8
SDA9
SDA10

SDD0
SDD1
SDD2
SDD3

SDD4
SDD5
SDD6
SDD7

SDD8
SDD9
SDD10
SDD11

SDD12
SDD13
SDD14
SDD15

SDD16
SDD17
SDD18
SDD19

SDD20
SDD21
SDD22
SDD23

SDD25
SDD26
SDD27

SDD28
SDD29
SDD30
SDD31

SDD32
SDD33
SDD34
SDD35

SDD36
SDD37
SDD38
SDD39

SDD40
SDD41
SDD42
SDD43

SDD45
SDD46
SDD47

SDD48
SDD49
SDD50
SDD51

SDD52
SDD53
SDD54
SDD55

SDD56
SDD57
SDD58
SDD59

SDD60
SDD61
SDD62
SDD63

XCS

XCAS

XWE

XRAS

DQM[7..0]

SDA[10..0]

MCLK

SDD[127..0]

25

IC319

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQM0
DQM1
DQM2
DQM3

NC
NC
NC
NC
NC
NC
NC

C5760.1uF

C5820.1uF

A0

26

A1

27

A2

60

A3

61

A4

62

A5

63

A6

64

A7

65

A8

66

A9

24

A10(AP)

22

BA0

23

BA1

68

CLK

67

CKE

20

/CS

19

/RAS

18

/CAS

17

/WE

3

VccQ

9

VccQ

35

VccQ

41

VccQ

49

VccQ

55

VccQ

75

VccQ

81

VccQ

6

VssQ

12

VssQ

32

VssQ

38

VssQ

46

VssQ

52

VssQ

78

VssQ

84

VssQ

1

Vcc

15

Vcc

29

Vcc

43

Vcc

44

Vss

58

Vss

72

Vss

86

Vss

SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10

SD_BA0
SD_BA1

R696 10K

VD+3.3 VD+3.3

+

C573

100uF/6.3V(PXA-5)

C5800.1uF

C5790.1uF

C5810.1uF C5750.1uFC5950.1uF

SDD0SDA0D0

2

SDD1

4

SDD2

5

SDD3

7

SDD4

8

SDD5

10

SDD6

11

SDD7

13

SDD8

74

SDD9

76

SDD10

77

SDD11

79

SDD12

80

SDD13

82

SDD14

83

SDD15

85

SDD16

31

SDD17

33

SDD18

34

SDD19

36

SDD20

37

SDD21

39

SDD22

40

SDD23

42

SDD24

45

SDD25

47

SDD26

48

SDD27

50

SDD28

51

SDD29

53

SDD30

54

SDD31

56

DQM0

16
71
28

DQM1

59

14
21
30
57
69
70
73

SDA0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10

SD_BA0
SD_BA1

HY57V63220CT-7

SDA0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10

SD_BA0
SD_BA1

R698 10K

C5940.1uF

C5930.1uF

C5890.1uF

C5900.1uF

C5960.1uF

25

IC321

A0

26

A1

27

A2

60

A3

61

A4

62

A5

63

A6

64

A7

65

A8

66

A9

24

A10(AP)

22

BA0

23

BA1

68

CLK

67

CKE

20

/CS

19

/RAS

18

/CAS

17

/WE

3

VccQ

9

VccQ

35

VccQ

41

VccQ

49

VccQ

55

VccQ

75

VccQ

81

VccQ

6

VssQ

12

VssQ

32

VssQ

38

VssQ

46

VssQ

52

VssQ

78

VssQ

84

VssQ

1

Vcc

15

Vcc

29

Vcc

43

Vcc

44

Vss

58

Vss

72

Vss

86

Vss

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQM0
DQM1
DQM2
DQM3

NC
NC
NC
NC
NC
NC
NC

SDD32

2

SDD33

4

SDD34

5

SDD35

7

SDD36

8

SDD37

10

SDD38

11

SDD39

13

SDD40

74

SDD41

76

SDD42

77

SDD43

79

SDD44

80

SDD45

82

SDD46

83

SDD47

85

SDD48

31

SDD49

33

SDD50

34

SDD51

36

SDD52

37

SDD53

39

SDD54

40

SDD55

42

SDD56

45

SDD57

47

SDD58

48

SDD59

50

SDD60

51

SDD61

53

SDD62

54

SDD63

56

DQM2

16
71

DQM3

28
59

14
21
30
57
69
70
73

SDA0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10

SD_BA0
SD_BA1

HY57V63220CT-7

R689 470

R690 NU-R1

C574

C5830.1uF

VD+3.3VD+3.3

C5970.1uF

VD+3.3CV

R697 10K

+

100uF/6.3V(PXA-5)

C5770.1uF

C5780.1uF

C5850.1uF

C5840.1uF

C5860.1uF

R699 10K

C5910.1uF

C5920.1uF

C5990.1uF

C5980.1uF

C6000.1uF

25

A0

26

IC320

A1

27

A2

60

A3

61

A4

62

A5

63

A6

64

A7

65

A8

66

A9

24

A10(AP)

22

BA0

23

BA1

68

CLK

67

CKE

20

/CS

19

/RAS

18

/CAS

17

/WE

3

VccQ

9

VccQ

35

VccQ

41

VccQ

49

VccQ

55

VccQ

75

VccQ

81

VccQ

6

VssQ

12

VssQ

32

VssQ

38

VssQ

46

VssQ

52

VssQ

78

VssQ

84

VssQ

1

Vcc

15

Vcc

29

Vcc

43

Vcc

44

Vss

58

Vss

72

Vss

86

Vss

HY57V63220CT-7

25

A0

26

IC322

A1

27

A2

60

A3

61

A4

62

A5

63

A6

64

A7

65

A8

66

A9

24

A10(AP)

22

BA0

23

BA1

68

CLK

67

CKE

20

/CS

19

/RAS

18

/CAS

17

/WE

3

VccQ

9

VccQ

35

VccQ

41

VccQ

49

VccQ

55

VccQ

75

VccQ

81

VccQ

6

VssQ

12

VssQ

32

VssQ

38

VssQ

46

VssQ

52

VssQ

78

VssQ

84

VssQ

1

Vcc

15

Vcc

29

Vcc

43

Vcc

44

Vss

58

Vss

72

Vss

86

Vss

HY57V63220CT-7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQM0
DQM1
DQM2
DQM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQM0
DQM1
DQM2
DQM3

SDD64

2

SDD65

4

SDD66

5

SDD67

7

SDD68

8

SDD69

10

SDD70

11

SDD71

13

SDD72

74

SDD73

76

SDD74

77

SDD75

79

SDD76

80

SDD77

82

SDD78

83

SDD79

85

SDD80

31

SDD81

33

SDD82

34

SDD83

36

SDD84

37

SDD85

39

SDD86

40

SDD87

42

SDD88

45

SDD89

47

SDD90

48

SDD91

50

SDD92

51

SDD93

53

SDD94

54

SDD95

56

DQM4

16

DQM5

71
28
59

14

NC

21

NC

30

NC

57

NC

69

NC

70

NC

73

NC

SDD96

2

SDD97

4

SDD98

5

SDD99

7

SDD100SDD24

8

SDD101

10

SDD102

11

SDD103

13

SDD104

74

SDD105

76

SDD106

77

SDD107

79

SDD108

80

SDD109

82

SDD110

83

SDD111

85

SDD112

31

SDD113

33

SDD114

34

SDD115

36

SDD116

37

SDD117

39

SDD118

40

SDD119

42

SDD120

45

SDD121

47

SDD122

48

SDD123

50

SDD124

51

SDD125

53

SDD126

54

SDD127

56

DQM6

16
71
28

DQM7

59

14

NC

21

NC

30

NC

57

NC

69

NC

70

NC

73

NC

121110987654321

126

127

LC-M3700
LC-M3710

Ë

PC I/F Unit-6/7

R971

RSII2

EXBV8V330J

RSII3
RSII4
RSII5

R972

H

RI1A[7..0]4

OGI1A[7..0]4

G

BI1A[7..0]4

RI1B[7..0]4

F

OGI1B[7..0]4

BI1B[7..0]4

E

OVCLK4
OV0_DE4
OV0_H4
OV0_V4
PC_C34
OV0_SOG4
OV0_HSC24

OVR[7..0]3

D

OVG[7..0]3

C

OV1_VCLK3
OV1_VAL3
OV1_H3
OV1_V3

OV1_ACT3

B

A

R977 10K

R942

0

OVR0
OVR1
OVR2
OVR3
OVR4
OVR5
OVR6
OVR7

OVG0
OVG1
OVG2
OVG3
OVG4
OVG5
OVG6
OVG7

RI1A0
RI1A1
RI1A2
RI1A3
RI1A4
RI1A5
RI1A6
RI1A7

OGI1A0
OGI1A1
OGI1A2
OGI1A3
OGI1A4
OGI1A5
OGI1A6
OGI1A7

BI1A0
BI1A1
BI1A2
BI1A3
BI1A4
BI1A5
BI1A6
BI1A7

RI1B0
RI1B1
RI1B2
RI1B3
RI1B4
RI1B5
RI1B6
RI1B7

OGI1B0
OGI1B1
OGI1B2
OGI1B3
OGI1B4
OGI1B5
OGI1B6
OGI1B7

BI1B0
BI1B1
BI1B2
BI1B3
BI1B4
BI1B5
BI1B6
BI1B7

104
213
214
315
408
493
317
318

485
400
307
206

96
399
306
205

404
311
488
403
310
209
100

99

103
314
407
405
312
102
210
101

398
305
204

95
304
203

94

93
402

309
208
401
308
207

98

97
320

412
494
216
105
106
215
316
107
409
113
221

108
217
411
496
109
319
219
220

10

11
126
233
332
234
333
424

121
229

123
230
329
421

321
413
118
112
228
327
328
419
120
111
115
223

117

119
226
325
326
417

12
127

13
128
235
334
425

14

124
231
330
125
232
331
422

V0_RA0
V0_RA1
V0_RA2
V0_RA3
V0_RA4
V0_RA5
V0_RA6
V0_RA7

V0_GA0
V0_GA1
V0_GA2
V0_GA3
V0_GA4
V0_GA5
V0_GA6
V0_GA7

V0_BA0
V0_BA1
V0_BA2
V0_BA3
V0_BA4
V0_BA5
V0_BA6
V0_BA7

V0_RB0
V0_RB1
V0_RB2
V0_RB3
V0_RB4
V0_RB5
V0_RB6
V0_RB7

V0_GB0
V0_GB1
V0_GB2
V0_GB3
V0_GB4
V0_GB5
V0_GB6
V0_GB7

V0_BB0
V0_BB1
V0_BB2
V0_BB3
V0_BB4
V0_BB5
V0_BB6
V0_BB7

V0_PVDCLK
V0_NVDCLK
V0_VDCLK_I
V0_VAL
V0_HSYNC
V0_VSYNC
V0_CSYNC
V0_GSYNC
V0_HSYNC2
V0_ACT
V0_PVCLK
V0_NVCLK

V1_RA0
V1_RA1
V1_RA2
V1_RA3
V1_RA4
V1_RA5
V1_RA6
V1_RA7

V1_GA0
V1_GA1
V1_GA2
V1_GA3
V1_GA4
V1_GA5
V1_GA6
V1_GA7

5

V1_BA0
V1_BA1
V1_BA2

V1_BA4
V1_BA5
V1_BA6
V1_BA7

V1_PVDCLK
V1_NVDCLK
V1_VDCLK_I
V1_VAL
V1_HSYNC
V1_VSYNC
V1_CSYNC
V1_GSYNC
V1_HSYNC2
V1_ACT
V1_PVCLK
V1_NVCLK

V1_RB0

3

V1_RB1

4

V1_RB2
V1_RB3
V1_RB4
V1_RB5
V1_RB6
V1_RB7

V1_GB0
V1_GB1
V1_GB2
V1_GB3
V1_GB4
V1_GB5
V1_GB6
V1_GB7

9

V1_BB0
V1_BB1
V1_BB2
V1_BB3
V1_BB4
V1_BB5
V1_BB6
V1_BB7

CVIC2

IC25B

DO_RA0
DO_RA1
DO_RA2
DO_RA3
DO_RA4
DO_RA5
DO_RA6
DO_RA7
DO_RA8
DO_RA9

DO_GA0
DO_GA1
DO_GA2
DO_GA3
DO_GA4
DO_GA5
DO_GA6
DO_GA7
DO_GA8
DO_GA9

DO_BA0
DO_BA1
DO_BA2
DO_BA3
DO_BA4
DO_BA5
DO_BA6
DO_BA7
DO_BA8
DO_BA9

DO_RB0
DO_RB1
DO_RB2
DO_RB3
DO_RB4
DO_RB5
DO_RB6
DO_RB7
DO_RB8
DO_RB9

DO_GB0
DO_GB1
DO_GB2
DO_GB3
DO_GB4
DO_GB5
DO_GB6
DO_GB7
DO_GB8
DO_GB9

DO_BB0
DO_BB1
DO_BB2
DO_BB3
DO_BB4
DO_BB5
DO_BB6
DO_BB7
DO_BB8
DO_BB9

DO_HSYNC
DO_VSYNC

DO_HDISP
DO_VDISP

DO_FEILD

V0_VDCLK_O

V0_PADCLK
V0_NADCLK
V0_PADRST
V0_NADRST

V0_CLP

V0_HSYNR

V0_HSYNF

V0_PDEN

V1_VDCLK_O

V1_PADCLK
V1_NADCLK
V1_PADRST
V1_NADRST

V1_CLP

V1_HSYNRV1_BA3

V1_HSYNF

V1_PDEN

BIASIN_VI

BIASOUT_VI

BIASIN_DO

BIASOUT_DO

DCLK

LCLK
LCLKP
LCLKN

S0_D0
S0_D1
S0_D2
S0_D3

S1_D0
S1_D1
S1_D2
S1_D3

MCK_REF

PLL_S

PLL_TEST

XTST

SMCK

IMODE

INITO

CPUS_0
CPUS_1
CPUS_2
CPUS_3

CCS_0
CCS_1

MST

XSM

INITI

RSII0

355

RSII1

354

RSII2

257

RSII3

152

RSII4

39

RSII5

256

RSII6

151

RSII7

38

RSII8

150

RSII9

37

OGSII0

446

OGSII1

357

OGSII2

445

OGSII3

356

OGSII4

259

OGSII5

154

OGSII6

41

OGSII7

258

OGSII8

153

OGSII9

40

BSII0

448

BSII1

359

BSII2

262

BSII3

358

BSII4

261

BSII5

156

BSII6

43

BSII7

260

BSII8

155

BSII9

42

RTII0

361

RTII1

264

RTII2

159

RTII3

449

RTII4

360

RTII5

263

RTII6

158

RTII7

45

RTII8

157

RTII9

44

OGTII0

452

OGTII1

363

OGTII2

266

OGTII3

161

OGTII4

451

OGTII5

362

OGTII6

265

OGTII7

160

OGTII8

47

OGTII9

46

BTII0

366

BTII1

365

BTII2

268

BTII3

163

BTII4

50

BTII5

364

BTII6

267

BTII7

162

BTII8

49

BTII9

48

DO_HS_O

36

DO_VS_O

35

DO_DE

149
254
148

225
114
222
322
414
218
406
313
410

227
224
324
415
499
110
68
7
122

323
575
253
351

146
255
33
147

236
129
15
16

427
336
130
131

497

IPD

212
487
397

303
418
500
518

34
17
335
132
239
238
237
19
18

RSII6
RSII7
RSII8
RSII9

RSII0
RSII1

OGSII1
OGSII2

OGSII3
OGSII4
OGSII5

OGSII6
OGSII7
OGSII8
OGSII9

BSII2
BSII3
BSII4
BSII5

BSII6
BSII7
BSII8
BSII9

BSII0
BSII1
RTII8
RTII9
EXBV8V330J^NU-RJ[L]
RTII0
RTII1
RTII2
RTII3
EXBV8V330J^NU-RJ[L]
RTII4
RTII5
RTII6
RTII7
EXBV8V330J^NU-RJ[L]
OGTII0
OGTII1
OGTII2
OGTII3
EXBV8V330J^NU-RJ[L]
OGTII4
OGTII5
OGTII6
OGTII7
EXBV8V330J^NU-RJ[L]
BTII8
BTII9
OGTII8
OGTII9
EXBV8V330J^NU-RJ[L]
BTII0
BTII1
BTII2
BTII3
EXBV8V330J^NU-RJ[L]
BTII4
BTII5
BTII6
BTII7
EXBV8V330J^NU-RJ[L]

R978 0
R979 0
R980 0

TL122

1

TL246

1

DCLKIN

-RST_PLL 1

VD+3.3CV

EXBV8V330J

R1255

EXBV8V330J^NU-RJ[L]

R973

EXBV8V330J

R974

EXBV8V330J

R975

EXBV8V330J

R976

EXBV8V330J

R1256

R1257

R1258

R1260

R1261

R1262

R1263

R1264

TL222

TL112

1

OV0_CLP 4
OV0_HSNR 4

OV0_PDEN 4

TL247

1

LCLK_O

RSI2

45

RSI3

3

6

3456

RSI4

2

7

2

7

RSI5

1

8

1

8

RSI6

45

RSI7

3

6

3456

RSI8

2

7

2

7

RSI9

1

8

1

8

RSI0

45

45

RSI1

3

6

6

3

OGSI0OGSII0

2

7

7

2

OGSI1

1

8

8

1

OGSI2

45

OGSI3

3

6

3456

OGSI4

2

7

2

7

OGSI5

1

8

1

8

OGSI6

45

OGSI7

3

6

3456

OGSI8

2

7

2

7

OGSI9

1

8

1

8

BSI2

45

BSI3

3

6

3456

BSI4

2

7

2

7

BSI5

1

8

1

8

BSI6

45

45

BSI7

3

6

6

3

BSI8

2

7

7

2

BSI9

1

8

8

1

BSI0

1

8

1

8

BSI1

2

7

2

7

RTI8

3

6

3456

RTI9

45

RTI0

1

8

1

8

RTI1

2

7

2

7

RTI2

3

6

3456

RTI3

45

RTI4

1

8

1

8

RTI5

2

7

2

7

RTI6

3

6

3456

RTI7

45

OGTI0

1

8

1

8

OGTI1

2

7

2

7

OGTI2

3

6

3456

OGTI3

45

OGTI4

1

8

1

8

OGTI5

2

7

2

7

OGTI6

3

6

3456

OGTI7

45

BTI8

1

8

1

8

BTI9

2

7

2

7

OGTI8

3

6

3456

OGTI9

45

BTI0

1

8

1

8

BTI1

2

7

2

7

BTI2

3

6

3456

BTI3

45

BTI4

1

8

1

8

BTI5

2

7

2

7

BTI6

3

6

3456

BTI7

45

TL113

1

1

DO_HSYNC 7
DO_VSYNC 1,7
DO_HDISP 1,7

TL114

1

R1201 100

RSI[9..2] 7

OGSI[9..2] 7

BSI[9..2] 7

R1259 0^NU-R1[M]

FL98

BMS100^33(1/10W)^NU-R2[L]

123

R1266 0(1/10W)

R1135
10K

C695
NU-C1

DO_DE
DO_HS_O
DO_VS_O

R1128

DCLKXTAL

X4

3 4

OUTVDC

CntlGND

DSO751SV(25.000M)

R1252 0^NU-R1[L]
R1253 0^NU-R1[L]
R1254 0^NU-R1[L]

X6

3 4

OUTVDC

DSO751SV(25.175M)^NU-CX7[M]

47^NU-R1[M]

X5

3 4

OUTVDC

91.3M

VD+3.3

12

RSI9
RSI7

RSI5
RSI3
RSI1
RTI9

RTI7
RTI5
RTI3
RTI1

OGSI9
OGSI7
OGSI5
OGSI3

OGSI1
OGTI9
OGTI7
OGTI5

OGTI3
OGTI1
BSI9
BSI7

BSI5
BSI3
BSI1
BTI9

BTI7
BTI5
BTI3
BTI1

RSI8
RSI6

RSI4
RSI2
RSI0
RTI8

RTI6
RTI4
RTI2
RTI0

OGSI8
OGSI6
OGSI4
OGSI2

OGSI0
OGTI8
OGTI6
OGTI4

OGTI2
OGTI0
BSI8
BSI6

BSI4
BSI2
BSI0
BTI8

BTI6
BTI4
BTI2
BTI0

PD4R080N9B^NU-PD80[L]

LCLK 7

12

CntlGND

12

CntlGND

C697

0.01uF

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

1
2
3
4
5
6
7
8
9

CN10

A1
A2
A3
A4

OVGA_OE 1

VD+3.3

C919

0.01uF^NU-C1[M]

VD+3.3

C759

0.01uF

WXGA_OE 1

IC25C

1

VSS

2

VSS

29

VSS

30

VSS

31

VSS

32

VSS

58

VSS

59

VSS

60

VSS

87

VSS

88

VSS

89

VSS

116

VSS

283

VSS

338

VSS

344

VSS

352

VSS

353

VSS

433

VSS

443

VSS

455

VSS

482

VSS

484

VSS

501

VSS

502

VSS

503

VSS

506

VSS

507

VSS

510

VSS

511

VSS

514

VSS

515

VSS

519

VSS

520

VSS

521

VSS

522

VSS

525

VSS

526

VSS

529

VSS

530

VSS

533

VSS

534

VSS

538

VSS

539

VSS

540

VSS

544

VSS

545

VSS

548

VSS

549

VSS

552

VSS

553

VSS

557

VSS

558

VSS

559

VSS

563

VSS

564

VSS

567

VSS

568

VSS

571

VSS

572

VSS

576

VSS

PCVICPLL

C846
1uF

R1134
47

VD+3.3 VD+3.3CV

VD+1.8

BLM31PG121SN1

CVIC2

491

A_VDD

490

A_VSS

FL32 BLM31PG121SN1

FL31

12

12

+

VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL

VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH

C367
150uF/4V(PXA)

504
505
508
509
512
513
516
517
523
524
527
528
531
532
535
536
542
543
546
547
550
551
554
555
561
562
565
566
569
570
573
574

171
337
343
420
423
426
428
429
432
434
435
438
439
441
442
444
447
450
453
454
456
458
462
465
468
471
474
477
483
486
489
492
495
498
560

+

C366
100uF/6.3V(PXA)

VD+1.8CV

10uF(3225)^NU-C3216

C10

C815 0.1uF
C816 0.1uF
C817 0.1uF
C818 0.1uF
C819 0.1uF
C820 0.1uF
C821 0.1uF
C822 0.1uF
C823 0.1uF
C824 0.1uF
C825 0.1uF
C826 0.1uF
C827 0.1uF
C828 0.1uF
C829 0.1uF
C830 0.1uF

C831 0.1uF
C832 0.1uF
C833 0.1uF
C834 0.1uF
C835 0.1uF
C836 0.1uF
C837 0.1uF
C838 0.1uF
C839 0.1uF
C840 0.1uF
C841 0.1uF
C842 0.1uF
C843 0.1uF
C844 0.1uF
C845 0.1uF

C848 0.1uF

TP10
PAD1.6

TP11
PAD1.6

TP12
PAD1.6

TP13

PAD1.6

128

121110987654321

129

LC-M3700
LC-M3710

Ë

PC I/F Unit-7/7

H

FL209

VD+3.3

FL200

FL201

BLM31PG121SN1^NU-BLM31[M]

12

C855

C856

82pF^NU-C1[M]

0.1uF^NU-C1[M]

C857

+

10uF/16V^NU-CE4[M]

1 2

0.1uF^NU-C1[M]

BLM31PG121SN1^NU-BLM31[M]

G

RSI[9..2]6

OGSI[9..2]6

BSI[9..2]6

VD+5

6
5

1SS355^NU-D3^NU-D3[M]

12

D75

C867

+

10uF/16V^NU-CE4[M]

V_SII

C869

0.1uF^NU-C1[M]

F

VD+3.3

IC412

1

VC

VIN

2

GND

GND1

3 4

NR VO

PQ1R33^NU-PQ1R33^NU-PQ1R33[M]
C868

0.1uF^NU-C1^NU-C1[M]

E

TP4

TESTPIN

TL231
PAD1.6

VD+3.3

1

D

C858

82pF^NU-C1[M]

OGSI5
OGSI4
OGSI3

OGSI2
BSI9
BSI8

BSI7
BSI6
BSI5
BSI4
BSI3
BSI2

DO_HDISP1,6
DO_HSYNC6
DO_VSYNC1,6
MON_DET1

-RST_PL1
SCL11
SDA_11

C859

1 2

BLM31PG121SN1^NU-BLM31[M]

+

C860
10uF/16V^NU-CE4[M]

LCLK6

C864

C872

0.1uF^NU-C1[M]

C874

82pF^NU-C1[M]

82pF^NU-C1[M]

49

PVCC2

50

D11

51

D10

52

D9

53

D8

54

D7

55

D6

56

IDCK-

57

IDCK+

58

D5

59

D4

60

D3

61

D2

62

D1

63

D0

64

GND

1K^NU-R1[M]

RSI2

RSI3

RSI4

RSI5

RSI6

RSI7

RSI8

RSI9

OGSI6

OGSI7

OGSI8

OGSI9

V_SII_VD

48

D22

D21

D20

D19

D18

D17

D16

D15

PGND2

D13/MASI

D12/DUAL

D14/SYNCO

IC413

SiI170^NU-S170[M]

DK1/MCL

DE

VREF

HSYNC/SYNC1

VSYNC

DK3

DK2/MDA

VCC

23456

R1007

EDGE/CHGPDVCC

MSEN

8

719101213141516

11

100^NU-R1[M]

R1008

100^NU-R1[M]

333435363738394041424344454647

D23

VCC

GND

RESERVED

EXT_SWING

ISEL/RST

DSEL/SDA

BSEL/SCL

GND

100^NU-R1[M]

R1002

R1003

C879

82pF^NU-C1[M]

AGND

TX2+

AVCC

TX1+

AGND

TX0+

AVCC

TXC+

TXC-

AGND

PVCCI

PGND1

TX2-

TX1-

TX0-

C863
82pF^NU-C1[M]

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V_SII_VA

82pF^NU-C1[M]

C865

C870

82pF^NU-C1[M]

R999

82pF^NU-C1[M]

510^NU-R1[M]

C876

0.1uF^NU-C1[M]

DV_TXD2+
DV_TXD2-

DV_TXD1+
DV_TXD1-

DV_TXD0+
DV_TXD0-

DV_TXDC+
DV_TXDC-

VD+3.3

Q102

1

G1

2

S2

3 4

G2 D2

NDC7002N

D1
S1

DV_TXD2-

DV_TXD1-

DV_TXD0-

DV_TXDC+

6
5

H1H2

CN3

1 2

D2- D2+

3 4

D2/4SH D4-

HOOK1HOOK2

5 6

D4+ DDC_CLK

7 8

DDC_DATA AVSYN

9 10

D1- D1+

11 12

D1/3SH D3-

13 14

D3+ +5V

15 16

GND HOTPD

17 18

D0- D0+

19 20

D0/5SH D5-

21 22

D5+ CLKSH

23 24

CLK+ CLK-

C1 C2

RED GREEN

C3 C4

BLUE AHSYNC

C5

AGND

VD+5BKC875

R1000

NU-R1^1.8K[M]

AGND

HOOK3 HOOK4

H3 H4

74320-1004^NU-DVI[M]

R1001

NU-R1^1.8K[M]

DV_TXD2+

DV_TXD1+

R1104 10K^NU-R1[M]

DV_TXD0+

DV_TXDC-

C6

5

LTC1694^NU-LTC[M]

FL204

VD+5DVI

BLM31PG121SN1^NU-BLM31[M]

IC428

BUS1

VCC
GND

NCBUS2

SCL1_5 3
SDA1_5 3

R1267 27K

VD+5

12

VD+5BK

1
2
34

HOTPLUG 1

0.1uF^NU-C1[M]

C980

ROUT0 4

C

OGOUT0 4

BOUT0 4

B

R1042
820

R1043
820

R1044
820

A

121110987654321

130

131

PRINTED WIRING BOARD ASSEMBLIES

H

G

F

LC-M3700
LC-M3710

E

D

C

B

A

MONITOR Unit (Side-A)

132

121110987654321

133