SGS Thomson Microelectronics ST62T25BN3, ST62T25BN1, ST62T25BM6, ST62T25BM3, ST62T25BM1 Datasheet

Rev. 3.2

July 2001 1/105

ST6215C/ST6225C

8-BIT MCUs WITH A/D CONVERTER,

TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

■ Memories

– 2K or 4K bytes Program memory (OTP,

EPROM, FASTROM or ROM) with read-out
protection

– 64 bytes RAM

■ Clock, Re set and Supply M a nagement

– Enhanced reset system
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or

RC netwo rk, ex tern al cloc k, bac kup o scillat or

(LFAO)
– Oscillator Safeguard (OSG)
– 2 Power Saving Modes: Wait and Stop

■ Interrupt Management

– 4 interrupt vectors plus NMI and RESET
– 20 external interrupt lines (on 2 vectors)
– 1 external non-interrupt line

■ 20 I/ O P o rts

– 20 multifunctional bidirectional I/O lines
– 16 alternate function lines
– 4 high sink outputs (20mA)

■ 2 Timers

– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler

■ Analog Peripheral

– 8-bit ADC with 16 input channels

■ Instructio n Set

– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

(See Section 12.5 for Ordering Information)

PDIP28

S028

CDIP28W

SS0P28

Features

ST62T15C(OTP)

ST6215C(ROM)

ST62P15C(FASTROM)

ST62T25C(OTP)

ST6225C(ROM)

ST62P25C(FASTROM

ST62E25C(EPROM)

Program memory - bytes 2K 4K
RAM - byte s 64
Operati ng S upply 3.0V to 6V
Clock Fre quency 8MHz Max
Operati ng T em perature -40°C to +125°C

Packages PDIP28 / S O28 / SSOP28 CDIP28 W

1

Table of Contents

105

2/105

2

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9

3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.6 Data ROM Window Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.3 Low Frequency Au xi liary Osc illator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3.3 RESET

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.5.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.6 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.6.1 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table of Contents

3/105

3

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

7.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.4 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3

9.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.3.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table of Contents

105

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10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1.1 M inimu m and M axim um Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.1.5 Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.3.1 G eneral Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 66

11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11.4.2 W AIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

11.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.5.1 G eneral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.5.3Cry st al and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.5.5Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 76

11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.6.1RA M and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.6.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.7.1 F unct ional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.9.1A sy nchronous RE SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

1

Table of Contents

5/105

11.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

12.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.6.1FASTROM Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.6.2ROM Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

14 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

16 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

1

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1 INTRODUCTION

The ST6215C, 25C devices are low cost members
of the ST62xx 8-bit HCMOS family of microcontrol­lers, which is targeted at low to medium complexity
applications. All ST62xx devices are based on a
building block approach: a common core is sur­rounded by a number of on-chip peripherals.

The ST62E25C is the erasable EPROM version of
the ST62T15C, T25C devices, which may be used
during the development phase for the ST62T15C,
T25C target devices, as well as the respective
ST6215C, 25C ROM devices.

OTP and EPROM devices are functional ly identi­cal. OTP devices offer a ll the advantages of us er
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple c ode vers ions or
last minute programmabilit y are required.

The ROM based versions offer the same function­ality, selecting the options defined in the program-

mable option bytes of the OTP/EPR OM versions
in the ROM option list (See Section 12.6 on page

97).

The ST62P15C/P2 5C are the Factory Advanced
Service Technique ROM (FASTROM) versions of
ST62T15C,T25C OTP devices.

They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 12 on page 91).

These compact low -cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program­mable prescaler, an 8-bit A/D Converter with 16
analog inputs and a Digital Wa tchdog timer, mak­ing them well suited for a wide range of automo­tive, appliance and industrial applications.

For easy reference, all parametric data is locat ed
in Section 11 on page 63.

Figure 1. Block Diagram

NMI

INTERRUPTS

PROGRAM

PC

STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6

POWER
SUPPLY

OSCILLATOR

RESET

DATA RO M

USER

SELECTABLE

DATA RAM

64 Bytes

PORT A

PORT B

PORT C

TIMER

8-BIT CO RE

8-BIT

A/D CONVERTER

PA0..PA3 (20mA Sink)
PA4..PA7 / Ain

PB0..PB7 / Ain

PC4..PC7 / Ain

TIMER

V

DDVSS

OSCin OSCout RESET

WATCHDOG

:

MEMORY

TIMER

(2K or 4K Bytes)

V

PP

4

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2 PIN DESCRI PTION

Figure 2. 28-Pin Package Pinout

Table 1. Device Pin Description

15

16

17

18

19

20

28
27
26
25
24
23
22
21

1
2
3
4
5
6
7
8
9
10
11
12
13

14

V

DD

TIMER

Ain/PB5

Ain/PB6

Ain/PB7

RESET

V

PP

Ain/PC4

Ain/PC5

Ain/PC6

Ain/PC7

NMI

OSCout

OSCin

V

SS

PA0/20mA Sink

PB4/Ain

PB3/Ain

PB2/Ain

PB1/Ain

PB0/Ain

PA7/Ain

PA6/Ain

PA5/Ain

PA4/Ain

PA3/20mA Sink

PA2/20mA Sink

PA1/20mA Sink

it2

it1

it2

itX associated interrupt vector

it2

Pin n° Pin Name

Type

Main Function

(after Reset)

Alternate Function

1 V

DD

S Main power supply

2

TIMER

I/O Timer input or output
3 OSCin I External clock input or resonator oscillator inverter input
4 OSCout O Resonator oscillator inverter output or resistor input for RC oscillator
5 NMI I Non maskable interrupt (falling edge sensitive)
6 PC7/Ain I/O Pin C7 (IPU) Analog input
7 PC6/Ain I/O Pin C6 (IPU) Analog input
8 PC5/Ain I/O Pin C5 (IPU) Analog input
9 PC4/Ain I/O Pin C4 (IPU) Analog input

10 V

PP

Must be held at Vss for normal operation, if a 12.5V level is applied to the pin
during the reset phase, the device enters EPROM programming mode.

11 RESET

I/O Top priority non maskable interrupt (active low)
12 PB7/Ain I/O Pin B7 (IPU) Analog input
13 PB6/Ain I/O Pin B6 (IPU) Analog input

5

ST6215C/ST6225C

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Legend / Abbreviations for Table 1:

I = input, O = output, S = supply, IPU = input pull-up
The input with pull-up configuration (reset state) is valid as long as the user software does not change it.
Refer to Section 8 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports.

14 PB5/Ain I/O Pin B5 (IPU) Analog input
15 PB4/Ain I/O Pin B4 (IPU) Analog input
16 PB3/Ain I/O Pin B3 (IPU) Analog input
17 PB2/Ain I/O Pin B2 (IPU) Analog input
18 PB1/Ain I/O Pin B1 (IPU) Analog input
19 PB0/Ain I/O Pin B0 (IPU) Analog input
20 PA7/Ain I/O Pin A7 (IPU) Analog input
21 PA6/Ain I/O Pin A6 (IPU) Analog input
22 PA5/Ain I/O Pin A5 (IPU) Analog input
23 PA4/Ain I/O Pin A4 (IPU) Analog input
24 PA3/ 20mA Sink I/O Pin A3 (IPU)
25 PA2/ 20mA Sink I/O Pin A2 (IPU)
26 PA1/ 20mA Sink I/O Pin A1 (IPU)
27 PA0/ 20mA Sink I/O Pin A0 (IPU)
28 V

SS

S Ground

Pin n° Pin Name

Type

Main Function

(after Reset)

Alternate Function

6

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3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES

3.1 MEMORY AND REGISTER MAPS

3.1.1 Introd uct i on

The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.

Briefly, Program space contains user program
code in OTP and user vectors; Data space con­tains user data in RAM and in OTP, and Stack
space accommodat es six levels of stack for sub­routine and interrupt service routine nesting.

Figure 3. Mem ory Addressing Dia gram

PROGRAM SPACE

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

RAM

X REGISTER
Y REGISTER
V REGISTER

W REGISTER

000h

03Fh
040h

07Fh
080h
081h
082h
083h
084h

0C0h

0FFh

DATA SPACE

000h

0FF0h

0FFFh

MEMORY

MEMORY WINDOW

DATA READ-ONLY

RESERVED

HARDWARE

CONTROL

REGISTERS

0BFh

(see Table 2)

(see Figure 4

on page 10)

1

ST6215C/ST6225C

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MEMORY MAP (Cont’d)
Figure 4. Program Memory Map

RESERVED

*

RESERVED

*

0000h

07FFh
0800h

087Fh

NOT IMPLEMENTED

RESERVED

*

USER

PROGRAM MEMORY

1824 BYTES

0880h

0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh

RESERVED

*

INTE RR U PT VECTOR S

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

0000h

07Fh

USER

PROGRAM ME M OR Y

3872 BYTES

080h

0F9Fh
0FA0h

0FEFh

0FF0h
0FF7h

0FF8h
0FFBh
0FFCh
0FFDh
0FFEh

0FFFh

RESERVED

*

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

RESERVED

*

ST6215C ST6225C

1

ST6215C/ST6225C

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MEMORY MAP (Cont’d)

3.1.2 Program Space

Program Space comprises the instructions to b e
executed, the data required for immediate ad­dressing mode instructions, the reserved factory
test area and the user v ectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register). Thus, the MCU is capable of ad­dressing 4K bytes of memory directly.

3.1.3 Readout Protection

The Program Mem ory i n O TP or E P ROM devices
can be protected against external readout of mem­ory by setting the Readout Protection bit in the op­ti on byte (Section 3.3 on page 16).

In the EPROM parts, Readout Protection option
can be desactivated only by U.V. erasure that also
results in the whole EPROM context being erased.

Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts can therefore not be accepted if the Readout
Protection bit is set.

3.1.4 Data Space

Data Space accommodates all the data necessary
for processing the user program. This space com­prises the RAM resource, the proc essor core an d
peripheral registers, as well as read-only data

such as constants and look-up tables in OTP/
EPROM.

3.1.4.1 Data ROM

All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program m emory consequently con­tains the program code to be executed, as well as
the constants and look-up tables required by t he
application.

The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to acc ess the
read-only data stored in OTP/EPROM.

3.1.4.2 Data RAM

The data space includes the user RAM area, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis­ters, the peripheral data and control registers, the
interrupt option register and the Data ROM Win­dow register (DRWR register).

3.1.5 Stack Space

Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.

1

ST6215C/ST6225C

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MEMORY MAP (Cont’d)
Table 2. Hardware Register Map

Legend:

x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.

Notes:

1. The contents of the I/O p ort D R registers are read able only in output configuration. In i nput c onfigura­tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always be kept at their reset value.

3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 8 "I/O PORTS" on page 38 for more details).

Address Block

Register

Label

Register Name

Reset

Status

Remarks

080h

to 083h

CPU X,Y,V,W

X,Y index registers
V,W short direct registers

xxh R/W

0C0h
0C1h
0C2h

I/O Ports

DRA

1) 2) 3)

DRB

1) 2) 3)

DRC

1) 2) 3)

Port A Data Register
Port B Data Register
Port C Data Register

00h
00h
00h

R/W
R/W

R/W
0C3h Reserved (1 Byte)
0C4h

0C5h
0C6h

I/O Ports

DDRA

2)

DDRB

2)

DDRC

2)

Port A Direction Register
Port B Direction Register
Port C Direction Register

00h
00h
00h

R/W

R/W

R/W
0C7h Reserved (1 Byte)
0C8h CPU IOR Interrupt Option Register xxh Write-only
0C9h ROM DRWR Data ROM Window register xxh Write-only
0CAh

0CBh

Reserved (2 Bytes)

0CCh
0CDh
0CEh

I/O Ports

ORA

2)

ORB

2)

ORC

2)

Port A Option Register
Port B Option Register
Port C Option Register

00h
00h
00h

R/W

R/W

R/W

0CFh Reserved (1 byte)

0D0h
0D1h

ADC

ADR
ADCR

A/D Converter Data Register
A/D Converter Control Register

xxh
40h

Read-only

Ro/Wo
0D2h

0D3h
0D4h

Timer1

PSCR
TCR
TSCR

Timer 1 Prescaler Register
Timer 1 Counter Register
Timer 1 Status Control Register

7Fh

0FFh

00h

R/W

R/W

R/W
0D5h

to 0D7h

Reserved (3 Bytes)

0D8h

Watchdog

Timer

WDGR Watchdog Register 0FEh R/W

0D9h

to 0FEh

Reserved (38 Bytes)

0FFh CPU A Accumulator xxh R/W

1

ST6215C/ST6225C

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MEMORY MAP (Cont’d)

3.1.6 Data ROM Window Mechanism

The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be­tween address 0000h and 0FFFh.

There are 64 blocks of 64 bytes in a 4K device:
– Block 0 is related to the address range 0000h to

003Fh.

– Block 1 is related to the address range 0040h to

007Fh.
and so on...
All the program memory can therefore be used to

store either instructions or read-only data. The
Data ROM window can be moved in st eps of 64
bytes along the program memory by writing the
appropriate code in the Data ROM Window Regis­ter (DRWR).

Figure 5. Data R OM Window

3.1.6.1 Data ROM Window Register (DRWR)

The DRWR can be a ddressed li ke any RAM loca­tion in the Data Space.

This register is used to sele ct the 64-byt e blo ck of
program memory to be read in the Data ROM win­dow (from address 40h to address 7Fh in Data
space). The DRWR register is not clea red on re­set, therefore it must be written to before access­ing the Data read-on ly memory window area for
the first time .

Address: 0C9h — Write Only
Reset Value = xxh (undefined)

Bits 7:6 = Reserved, must be cleared.

Bits 5:0 = DRWR[5:0]

Data read-only memory

Window Register Bits.

These are the Data read­only memory Window bits that correspond to the
upper bits of the data read-only memory space.

Caution:

This register is undefined on reset, it is
write-only, therefore do not read it nor access it us­ing Read-Modify-Write instructions (SET, RES,
INC and DEC).

0000h

0FFFh

000h

040h

07Fh

0FFh

DATA ROM

WINDOW

DATA SPACE

64-BYTE

ROM

PROGRAM

SPACE

70

- - DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0

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ST6215C/ST6225C

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MEMORY MAP (Cont’d)

3.1.6.2 Data ROM Window memory addressing

In cases where some data (look-up tables for ex­ample) are stored in program memory, reading
these data requires the use of the Data ROM win­dow mechanism. To do this:

1. The DRWR register ha s to be loaded with the
64-byte block number where the data are located
(in program memory). This number also gives the
start address of the block.

2. Then, the offset address of the byte in th e Data
ROM Window (corresponding to the offset in the
64-byte block in program memory) has to be load­ed in a register (A, X,...).

When the above two steps are completed, the
data can be read.

To understand how to determine the DRWR and
the content of th e register, please refer to t he ex­ample shown in Figure 6. I n any c ase t he c alcul a-

tion is automatically hand led by the ST6 deve lop­ment tools.

Please refer to the user manual of the corres pod­ing tool.

3.1.6.3 Recommendations

Care is required when handling the DRWR regis­ter as it is write only. For this reason, the DRWR
contents should not be chan ged while executing
an interrupt service routine, as the service routine
cannot save and then restore the register’s previ­ous contents. If it is imp ossible to avoi d writing to
the DRWR during the interrupt service routine, an
image of the register must be saved in a RAM lo­cation, and each time the program writes to the
DRWR, it must also write to the image register.
The image register must be written first so that, if
an interrupt occurs between the two instructions,
the DRWR is not affected.

Figure 6. Data read-only memory Window Memo ry Add ressi ng

DATA

PROGRAM SPACE

DATA SPACE

0000h

0400h

0421h

07FFh

64 bytes

OFFSET

000h

040h

061h
07Fh

OFFSET
21h

0FFh

DRWR

DATA address in Program memory : 421h
DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h
64-byte window start address : 10h x 3Fh = 400h
Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h

10h

DATA

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3.2 PROGRAMMING MODES

3.2.1 Program Memory

EPROM/OTP programming mode is set by a
+12.5V voltage a pplied to the T EST/V

PP

pin. The
programming flow of the ST62T15C,T25C/E25C is
described in the User Manual of the EPROM Pro­gramming Board.

Table 3. ST6215C Program Memo ry M ap

Table 4. ST6225C Program Memo ry M ap

Note: OTP/EPROM devices can be programm ed

with the development tools available from
STMicroelectronics (please refer to Section 13 on

page 100).

3.2.2 EPROM Erasing

The EPROM devices can be erased by exposure
to Ultra Violet light. The characteristics of the MCU
are such that erasure begins when the memory is
exposed to light with a wave lengths shorter than

approximately 4000Å. It should be noted that sun­light and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.

It is thus recommended that the window of the
MCU packages be covered by an opaque label to
prevent unintentional erasure problems when test­ing the application in such an environment.

The recommended erasure procedure is exposure
to short wave u ltraviolet light whi ch have a wave­length 2537Å. The integrated dose (i.e. U.V. inten­sity x exposure time) for erasure should be a mini­mum of 30W-sec/cm

2

. The erasure time with this
dosage is approximately 30 to 40 minutes using an
ultraviolet lamp with 12000µW/cm

2

power rating.

The EPROM device should be placed within

2.5cm (1inch) of the lamp tubes during erasure.

Device Address Description

0000h-087F h
0880h-0F9F h

0FA0h-0FEF h

0FF0h-0FF7 h

0FF8h-0FFB h

0FFCh-0FFD h

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

Device Address Description

0000h-007F h

0080h-0F9F h

0FA0h-0FEF h

0FF0h-0FF7 h

0FF8h-0FFB h

0FFCh-0FFD h

0FFEh-0FFF h

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

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16/105

3.3 OPTION BYTES

Each device is available for production in user pro­grammable versions (OTP) as well as in factory
coded versions (ROM). O TP d evices are shippe d
to customers with a default content (00h), while
ROM factory coded parts contain the code sup­plied by the customer. This implies that OTP de­vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto­ry-configured.

The two option b ytes allow t he hardware configu­ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST6 program­ming tool).
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see Section

12.6.2 "ROM Versio n" on page 98 ). It is therefore

impossible to read the option bytes.
The option bytes can be only programmed once. It

is not possible to change the selected options after
they have been programmed.

In order to reach the power consumption value in­dicated in Section 11.4, the option byte must be
programmed to its default value. Otherwise, an
over-consumption will occur.

MSB OPTION BY TE

Bits 15:10 = Reserved, must be always cleared.

Bit 9 = EXTCNTL

External STO P MO DE control.

0: EXTCNTL mode not available. STOP mode is

not available with the watchdog active.

1: EXTCNTL mode available. STOP mode is avail-

able with the watchdog active by setting NMI pin
to one.

Bit 8 = LVD

Low Voltage Detector

on/off

.

This option bit enable or disable the Low Voltage
Dete ctor (LVD ) feature.

0: Low Voltage Detector disabled
1: Low Voltage Detector enabled.

LSB OPTION BYTE

Bit 7 = PROTECT

Readout Protection.

This option bit enables or disables external access
to the internal program memory.
0: Program memory not read-out protected
1: Program memory read-out protected

Bit 6 = OSC

Oscillator s elec tion

.
This option bit selects the main oscillator type.
0: Quartz crystal, ceramic resonator or external

clock

1: RC network

Bits 5:4 = Reserved, must be always cleared.

Bit 3 = NMI PULL

NMI Pull-Up

on/off.
This option bit enables or disables the internal pull­up on the NMI pin.
0: Pull-up disabled
1: Pull-up enabled

Bit 2 = TIM PULL

TIMER Pull-Up

on/off.
This option bit enables or disables the internal pull­up on the TIMER pin.
0: Pull-up disabled
1: Pull-up enabled

Bit 1 = WDACT

Hardware or software watchdog.

This option bit selects the watchdog type.
0: Software (watchdog to be enabled by software)
1: Hardware (watchdog always enabled)

Bit 0 = OSGEN

Oscillator Safeguard

on/off.
This option bit enables or disables the oscillator
Safeguard (OSG) feature.
0: Oscillator Safeguard disabled
1: Oscillator Safeguard enabled

MSB OPTION BYTE

15 8

LSB OPTION BYTE

70

Reserved

EXT
CTL

LVD

PRO-

TECT

OSC Res. Res.

NMI

PULL

TIM

PULLWDACT

OSG

EN

Default

Value

XXXXXXXXXXXXX X X X

1

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4 CENTRAL PROCE SSI NG UNIT

4.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the
I/O or Memory conf iguration. As such, it may b e
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe­ripherals via internal address, data, and control
buses.

4.2 MAIN FEATURES

■ 40 basic instructions

■ 9 main addressing modes

■ Two 8-bit index registers

■ Two 8-bit short direct registers

■ Low power modes

■ Maskable hardware interrupts

■ 6-level hardware stack

4.3 CPU REGISTERS

The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal­culations, logical operations, and data manipula-

tions. The accumulator can be addressed i n Data
Space as a RAM lo cation at address FFh. Thus
the ST6 can manipulate the accumulator just like
any other register in Data Space.

Index Registers (X, Y). Th ese two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bi t Direct
addressing modes. They are mapped in Data
Space at addresses 80h (X ) and 81h (Y) an d can
be accessed like any other memory location.

Short Direct Registers (V, W). These two regis­ters are used in Short Direct addressing mode.
This means that the data stored in V or W can be
accessed with a one-byte instruction (four CPU cy­cles). V and W can also be accessed using Di rect
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 82h (V) and
83h (W) and can be accessed like any other mem­ory location.

Note: The X and Y registers can also be used as
Short Direct registers in the same way as V and W.

Program Counter (PC). The program counter is a
12-bit register which cont ains the address of the
next instruction to be executed by the c ore. This
ROM location may be an opc ode, an operand, or
the address of an operand.

Figure 7. CPU Registers

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh

70

70

70

0

11

RESET VALUE = xxh

RESET VALUE = xxh

RESET VALUE = xxh

x = Undefined value

V SHORT INDIRECT

70

RESET VALUE = xxh

W SHORT INDIRECT

70

RESET VALUE = xxh

NORMAL FLAGS

CN ZN

CI ZI

CNMI ZNMI

INTERRUPT FLAGS

NMI FLAGS

SIX LEVEL

STACK

REGISTER

REGISTER

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CPU REGISTERS (Cont’d)
The 12-bit length allows the direct addressing of

4096 bytes in Program Space.
However, if the program space contains more than

4096 bytes, the additional memory in program
space can be addressed by using the Program
ROM Page register.

The PC value is incremented after reading the ad­dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:

– JP (Jump) instruction PC = Jump address
– CALL instruction PC = Call address
– Relative Branch InstructionPC = PC +/- offset
– Interrupt PC = Interrupt vector
– Reset PC = Reset vector
– RET & RETI instructions PC = Pop (stack)
– Normal instruction PC = PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of

flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskabl e
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is u sed
during Normal operation, another pair is used dur­ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt m ode (CNMI, ZN­MI).

The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable I nterrupt) is generated, the ST 6
CPU uses the Interrupt flags (or the NMI flag s) in­stead of the Normal flags. When the RETI instruc­tion is executed, the previously used set of flags is
restored. It should be noted that ea ch flag s et can
only be addressed in its own context (Non Maska­ble Interrupt, Normal Interrupt or Main routine).
The flags are not cleared during context swi tching
and thus retain their status.

C : Carry flag.
This bit is set when a carry or a borrow occurs dur-

ing arithmetic operations; otherwise it is cleared.
The Carry flag is also set to the val ue of the bit
tested in a bit test instruction; it also participates in
the rotate left instruction.
0: No carry has occured
1: A carry has occured

Z : Zero flag
This flag is set if the result of the last arithmetic or
logical operation was equal to zero; otherwise it is
cleared.
0: The result of the last operation is different from

zero

1: The result of the last operation is zero
Switching between the three sets of flags is per-

formed automatically when an NMI, an interrupt or
a RETI instruction occurs. As NMI mode is auto­matically selected after the reset of the MCU, the
ST6 core uses the NMI flags first.

Stack. The ST6 CPU includes a true LIFO (Last In
First Out) hardware stack which eliminates the
need for a stack pointer. The stack consists of six
separate 12-bit RAM locations that do not belong
to the data space RAM area. When a subroutine
call (or interrupt request) oc curs, the contents of
each level are shifted into the next level down,
while the content of the PC is shifted into the first
level (the original contents of the sixth stack level
are lost). When a subroutine or interrupt return oc­curs (RET or RETI instructions), the first level reg­ister is shifted back into the PC and the value of
each level is popped back into the previous level.

Figure 8. Stack manipulation

Since the accumulator, in common with all other
data space registers, is not stored in this stack,
management of these registers should be per­formed within the subroutine.

Caution: The stack will remain in its “deepest” po­sition if more than 6 nested calls or interrupts are
executed, and consequently the last return ad­dress will be lost.

It will also remain in its highest position if the stack
is empty and a RET or RETI is executed. In this
case the nex t in s truc t io n w ill be ex e c ut e d.

LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6

ON
INTERRUPT,
OR
SUBROUTINE
CALL

ON RETURN
FROM
INTERRUPT,
OR
SUBROUTINE

PROGRAM

COUNTER

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5 CLOCKS, SUPPLY AND RESET

5.1 CLOCK SYSTEM

The main oscillator of the MCU can be driven by
any of these cl ock sourc es:

– external clock signal
– external AT-cut parallel-resonant crystal
– external ceramic resonator
– external RC network (R

NET

).

In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up c lock
system or to reduce power consumption.

An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in t he event of m ain oscil­lator failure. It also automatically limits the internal
clock frequency (f

INT

) as a function of VDD, in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and F igure 11.

Table 5 illustrat es var ious poss ible os cillator c on-

figurations using an external crystal or ceramic
resonator, an external clock input, an external re­sistor (R

NET

), or the lowest cost solution using only

the LFAO.
For more details on c onfiguring the c lock options,

refer to the Option Bytes section of this document.
The internal MCU clock frequency (f

INT

) is divided
by 12 to drive the T imer, the Wat chdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.

With an 8 M Hz o s c illat o r, the fastes t CP U cycle is
therefore 1.625µs.

A CPU cycle is the smallest unit of time needed to
execute any operation (f or instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.

Figure 9. Clock Circuit Block Diagram

MAIN

OSCILLATOR

OSG

LFAO

CORE

:

13

:

12

8-BIT TIMER

WATCHDOG

f

INT

OSCOFF BIT

ADC

0

1

filtering

OSCILLATOR SAFEGUA RD (OSG)

OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)

(ADCR REGISTER)

f

OSC

Oscillator
Divider

SPI

: 1

: 3

8-BIT ARTIMER

8-BIT ARTIMER

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CLOCK SYSTEM (Cont’d)

5.1.1 Main Oscillator

The oscillator configuration is specified by select­ing the appropriate option in the option bytes (refer
to the Option Bytes section of this document).
When the CRYSTAL/RESONATOR option is se­lected, it must be used with a quartz crystal, a ce­ramic resonator or an external signal provided on
the OSCin pin. When the RC NETWORK option is
selected, the system clock is generated by an ex­ternal resistor (the capacitor is imple men ted inter­nally).

The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register (not
available on some devices). This will automatically
start the Low Frequency Auxiliary Oscillator
(LFAO).

The main oscillator can be turned off by resetting
the OSCOFF bit of the A/D Converter Control Reg­ister or by resetting the MCU. When the main os­cillator starts there is a delay made up of the oscil­lator start-up delay period plus the duration of the
software instruction at a clock frequency f

LFAO

.

Caution: It should be noted that when t he RC net­work option is selected, the accuracy of the fre­quency is about 20% so it may not be suitable for
some applications (For more details, please refer
to the Electrical Characteristics Section).

Table 5. Oscillator Configurations

Notes:

1. To select the options sho wn in column 1 of the abo ve
table, refer to the Option Byte section.

2.This schematic are given for guidance only and are sub­ject to the schematics given by the crystal or ceramic res­onator manufacturer.

3. For more details, plea se refer to the Electric al Char ac­teristics Section.

Hardware Configuration

Crystal/Resonator Option

1)

Crystal/Resonator Option

1)

RC Network Option

1)

OSG Enabled Option

1)

OSCin OSCout

EXTERNAL

ST6

CLOCK

NC

External Clock

OSCin OSCout

LOAD

CAPACITORS

3)

ST6

C

L2

C

L1

Crystal/Resonator Clock

2)

OSCin OSCout

ST6

R

NET

NC

RC Network

OSCin OSCout

ST6

LFAO

NC

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CLOCK SYSTEM (Cont’d)

5.1.2 Oscillator Safeguard (OSG)

The Oscillator Safeguard (OSG) feature is a
means of dramatically improving the operational
integrity of the MCU. It is available when the OSG
ENABLED option is selected in the option byte (re­fer to the Option Bytes section of this document).

The OSG acts as a filter whose cross-over fre­quency is device dependent and provides three
basic functions:

– F iltering spikes o n the os c illator lines whic h

would result in driving the CPU at excessive fre­quencies

– M anag ement of the Low Frequency Auxiliar y

Oscillator (LFAO), (useable as low cost internal
clock source , backup clock i n ca se of main oscil­lator failure or for low power consumption)

– Automatically limiting the f

INT

clock frequency as
a function of supply voltage, to ensure correct
operation even if the power supply drops.

5.1.2.1 Spike Filtering

Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre­quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure

10). In all cases, when the OSG is active, the max-

imum internal clock frequency, f

INT

, is limited to

f

OSG

, which is supply voltage dependent.

5.1.2.2 Management of Supply Voltage
Variations

Over-frequency, at a given power supp ly level, is
seen by the OSG as spikes; it therefore filte rs out
some cycles in order that the internal clock fre­quency of the device is kept within the range t he
particular device can stand (depending o n V

DD

),

and below f

OSG

: the maximum authorised frequen-

cy with OSG enabled.

5.1.2.3 LFAO Managemen t

When the OSG is enabled, the Low Frequency
Auxiliary Oscillator can be used (see Section

5.1.3).

Note: The OSG should be used wherever possible
as it provides maxim um security for the ap plica­tion. It should be noted however, that it can in­crease power consumption and reduce the maxi­mum operating frequency to f

OSG

(see Electrical

Characteristics section).
Caution: Care has to be taken when using the

OSG, as the internal frequency is defined between
a minimum and a maximum value and may vary
depending on both V

DD

and temperature. For pre­cise timing measurement s, it is not recom men ded
to use the OSG.

Figure 10. OSG Filtering Function

Figure 11. LFAO Oscillato r Function

f

OSC

f

OSG

f

INT

f

OSC<fOSG

f

OSC>fOSG

MAIN OSCILLATOR
STOPS

MAIN OSCILLA T OR

RESTARTS

INTERNAL CLOCK DRIVEN BY LFAO

f

OSC

f

INT

f

LFAO

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CLOCK SYSTEM (Cont’d)

5.1.3 Low Frequency Auxiliary Oscillator
(LFAO)

The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a backup oscillator in case of m ain oscillator fail­ure.

This oscillator is available when the OSG ENA­BLED option is selected in the option byte (refer to
the Option Bytes section of this document). In this
case, it automatically starts one of its periods after
the first missing edge of t he m ain os cillator, what­ever the reason for the failure (main oscillator de­fective, no clock circuit ry prov i ded, m ain o scillat or
switched off...). See Figure 11.

User code, normal interrupts, WAIT and STOP in­structions, are processed as normal, at the re­duced f

LFAO

frequency. The A/D converter accura­cy is decreased, since the internal frequency is be­low 1.2 MHz .

At power on, until the main oscillator starts, the re­set delay counter is driven by the LFAO. If the
main oscillator starts before the 2048 or 32768 cy­cle delay has elapsed, it takes over.

The Low Frequency Auxiliary Oscillator is auto­matically switched off as soon as the main oscilla­tor starts.

5.1.4 Register Description
ADC CONTROL REGISTER (ADCR)

Address: 0D1h — Read/Write
Reset value: 0100 0000 (40h)

Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0]

ADC Control

Register

.

These bits are used to control the A/D converter (if
available on the device) otherwise they are not
used.

Bit 2 = OSCOFF

Main Oscillator Off.

0: Main oscillator enabled
1: Main oscillator disabled

Note: The OSG must be enabled using the OS­GEN option in the Opt ion Byte, otherw ise t he OS­COFF setting has no effect.

70

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

0

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5.2 LOW VOLTAGE DETECTOR (LVD)

The on-chip Low Voltage De tector is enabled by
setting a bit in the option bytes (refer to the Option
Bytes section of this document).

The LVD allows the device to be used without any
external RESET circuitry. In this ca se , th e RESET
pin should be left unconnected.

If the LVD is not used, an external circuit is manda­tory to ensure correct Power On R eset operation,
see figure in the Reset section. For more details,
please refer to the application note AN669.

The LVD generates a static Reset when the supply
voltage is below a reference value. This means
that it secures the power-up as well as the power­down keeping the ST6 in reset.

The V

IT-

reference value for a voltage drop is lower

than the V

IT+

reference value for power-on in order
to avoid a parasitic reset when the MCU starts run­ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry gene rates a reset when
V

DD

is below:

– V

IT+

when VDD is rising

– V

IT-

when VDD is falling
The LVD function is illustrated in Figu re 12.
If the LVD is enabled, the MCU can be in only one

of two states:
– Over the input threshold voltage, it is running un-

der full software control

– Below the input threshold voltage, it is in static

safe reset

In these conditions, secure operation is guaran­teed without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus p ermitting the MCU to reset
other devices.

Figure 12. Low Voltage Detector Reset

V

DD

V

IT+

RESET

V

IT-

V

hyst

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5.3 RESET

5.3.1 Introd uction

The MCU can be reset in three ways:

■ A low pulse input on the RESET pin

■ Internal Watchdog reset

■ Internal Low Voltage Detector (LVD) reset

5.3.2 RESET Sequence

The basic RESET sequence consists of 3 main
phases:

■ Internal (watchdog or LVD) or external Reset

event

■ A delay of 2048 or 32768 clock (f

INT

) cycles

(selected through the option bytes)

■ RESET vector fetch

The reset delay allows the oscillator to stabilise
and ensures that recovery ha s taken place from
the Reset state.

The RESET vector fetch phase duration is 2 clock
cycles.

When a reset occurs:

– The stack is cleared
– The PC is loaded with the address of the Reset

vector. It is located in program ROM starting at
address 0FFEh.

A jump to the beginning of the us er program m ust
be coded at this address.

– The interrupt flag is automatically set, so that the

CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in­terrupted. The initialization routine should there­fore be terminated by a RETI instruction, in order
to go back to normal mode.

Figure 13. RESET Sequence

V

DD

RESET PIN

WATCHDOG

V

IT+

V

IT-

WATCHDOG UNDERFLOW

RESET

2048 CLOCK CYCLE (f

INT

) DELAY

LVD

RESET

INTERNAL

RUN

RESET

RUN RUN RUN

RESET RESET

RESET

1

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RESET (Cont’d)

5.3.3 RESET

Pin

The RESET

pin may be co nnecte d to a device on
the application board in order to reset the MCU if
required. The RESET

pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the internal state of the MCU and en­sure it starts-up correctly. The pin, which i s con­nected to an internal pull-up, is active low and fea­tures a Schmitt trigger input. A delay (2048 clock
cycles) added to the external signal ensures that
even short pulses on the RESET

pin are accepted

as valid, provided V

DD

has completed its rising
phase and that the oscillator is running correctly
(normal RUN or WAIT modes). The MCU is kept in
the Reset state as long a s the RESET

pin is held

low.

If the RESET

pin is grounded while the MCU is in
RUN or WAIT modes, processing of the user pro­gram is stopped (RUN mode only), the I/O ports
are configured as inputs with pull-up resistors and
the main oscillator is restarted. When the level on
the RESET

pin then goes high, the initialization se­quence is executed at the end of the internal delay
period.

If the RESET

pin is grounded while the MCU is in
STOP mode, the oscillator starts up and all the I/O
ports are configured as inputs with pull-up resis­tors. When the RESET

pin level then go es high,
the initialization sequence is executed at th e end
of the internal delay period.

A simple external RESET circuitry is shown in Fig-

ure 15. For more details, please refer to the appli-

cation note AN669.

Figure 14. Reset Block Diagram

f

IN T

COUNTER

RESET

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

R

ESD

1)

1) Resistive ESD protection.

V

DD

R

PU

2048 or 32768

clock cycles

2)

2) The reset delay value is selected through the option bytes.

1

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RESET (Cont’d)

5.3.4 Watchdog Reset

The MCU provides a Wat chdog timer function in
order to be able to recover from software hang­ups. If the Watchdog register is not refreshed be­fore an end-of-count condition is reached, a
Watchdog reset is generated.

After a Watchdo g reset, the MCU resta rts in the
same way as if a Reset was generated by the RE­SET pin.

Note: When a watchdog reset occurs, the RESET
pin is tied low for very short time period, to flag the
reset phase. This time is n ot long enough to reset
external circuits.

For more details refer to the Watchdog Timer
chapter.

5.3.5 LVD Reset

Two different RESET sequences caused by the in­ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

During an LVD reset, the RESET

pin is pulled low

when V

DD

<V

IT+

(rising edge) or VDD<V

IT-

(falling

edge).
For more details, refer to the LVD chapter.
Caution: Do not externally connect directly the

RESET

pin to VDD, this may cause damage to the
component in case of internal RESET (Watchdog
or LVD).

Figure 15. Simple External Reset Circuitry

Figure 16. Reset Processing

ST62xx

RESET

V

DD

V

DD

R

C

Typical: R = 10K

C = 10nF

R > 4.7 K

INT LATCH CLEARED

NMI MASK SET

(IF PRESENT)

SELECT

NMI MODE FLA G S

IS RESET STILL

PRESENT?

YES

PUT FFEh

ON ADDRESS BUS

FROM RESET LOCATIONS

FFEh/FFFh

NO

FETCH INSTRUCTION

LOAD PC

INTERNAL

RESET

RESET

2048 OR 327 68
CLOCK CYC LE

DELAY

1

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6 INTE RRUPTS

The ST6 core may be interrupted by four maska­ble interrupt sources, in addition to a Non Maska­ble Interrupt (NMI) source. The interrupt process­ing flowchart is shown in Figure 18.

Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0 ), interrupt events
are latched and may be processed as soon as the
GEN bit is set.

Each source is associated with a specific Interrupt
Vector, located in Program space (see Interrupt

Mapping table). In the vector location, the user

must write a Jump instruction to the associated in­terrupt service routine.

When an interrupt source generates an i nterrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jum p
to the relevant interrupt service routine, thus serv­icing the int e r ru pt.

Interrupts are triggered by events either on exter­nal pins, or from the on-chip periphe rals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter­mine which event triggered the interrupt.

1

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Figure 17. Interrupts Block Diagram

NMI

ESB BIT

V

DD

LATCH

CLEARED BY H/W

AT START OF VECTOR #0 ROUTINE

VECTOR #0

LES BIT

1

0

LATCH

CLEARED BY H/W
AT START OF

VECTOR #1

VECTOR #2

VECTOR #3

VECTOR #4

LATCH

CLEARED
BY H/W AT START OF
VECTOR #2 ROUTINE

I/O PORT REGISTER

CONFIGURATION

“INPUT WITH INTER RUP T”

I/O PORT REGISTER
CONFIGURATION

“INPUT WITH INTER RUP T”

EXIT FROM
STOP/WAIT

VECTOR # 1 ROUTINE

TIMER

A/D CONVERTER

TMZ BIT

ETI BIT

EAI BIT

EOC BIT

GEN BIT

PB0..PB7

PA0..PA7

(TSCR REGISTER)

(ADCR REG I ST ER)

(IOR REGISTER)

(IOR REGISTER)

(IOR REGISTER)

PC4..PC7

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6.1 INTERRUPT RULES AND PRIORITY
MANAGEMENT

■ A Reset can interrupt the NMI and peripheral

interrupt routines

■ The Non Maskable Interrupt request has the

highest priority and can interrupt any peripheral
interrupt routine at any time but cannot interrupt
another NMI interrupt.

■ No peripheral interrupt can in terrupt another. If

more than one interrupt request is pending,
these are processed by the processor core
according to their priority level: vector #1 has the
highest priority while vector #4 the lowest. The
priority of each interrupt source is fixed by
hardware (see Interrupt Mapping table).

6.2 INTERRUPTS AND LOW POWER MODES

All interrupts cause the processor to exit from
WAIT mode. Only the external and som e specific
interrupts from the on-chip peripherals cause the
processor to exit from STOP mode (refer to the

“Exit from STOP“ column in the Interrupt Mapping
Table).

6.3 NON MASKABLE INTERRUPT

This interrupt is t riggered when a fallin g edge oc­curs on the NMI pin regardless of the state of the
GEN bit in the IOR register. An interrupt request
on NMI vector #0 is latched by a flip flop which is
automatically reset by the core at the beginning of
the NMI service routine.

6.4 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the peripheral
control registers are able to cause an interrupt
when they are active if both:

– The GEN bit of the IOR register is set
– The corresponding enable bit is set in the periph-

eral control register.

Peripheral interrupts are linked to vectors #3 and
#4. Interrupt requests are flagged by a bit in their
corresponding control register. This means that a
request cannot be lost, because the flag bit m ust
be cleared by user software.

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6.5 EXTERNAL INTERRUPTS (I/O Ports)

External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the GEN bit is set. These interrupts
allow the processor to exit from STOP mode.

The external interrupt polarity is selected t hrough
the IOR register.

External interrupts are linked to vectors #1 and #

2.
Interrupt requests on vector #1 can be configu red

either as edge or le vel-s ensitive us in g t he LES bit
in the IOR Register.

Interrupt requests from vector #2 are always edge
sensitive. The edge polarity can be configured us­ing the ESB bit in the IOR Register.

In edge-sensitive mode, a latch is set when a edge
occurs on the interrupt source li ne and is cleared
when the associated interrupt routine is started.
So, an interrupt request can be stored until com­pletion of the currently executing interrupt routine,
before being processed. If several interrupt re­quests occurs before comp let ion o f the cu rrent in­terrupt routine, only the first request is stored.

Storing of interrupt requests is not possible i n level
sensitive mode. To be taken into account, the lo w
level must be present on the interrupt pin when the
MCU samples the line after instruction execution.

6.5.1 Notes on using External Interrupts
ESB bit Spuri ous Interrupt on Ve c tor # 2

If a pin associated with interrupt vector #2 is con­figured as interrupt with pull-up, whenever vector
#2 is configured to be rising edge sensitive (by set­ting th e ESB b it in the I OR register ), a n interrupt i s
latched although a rising edge may not have oc­cured on the associated pin.

This is due to the vector #2 circuitry.The worka­round is to discard this first interrupt request in the
routine (using a flag for example).

Masking of One Interrupt by Another on Vector
#2.

When two or more port pins (associated with inter­rupt vector #2) are configured together as input
with int errupt (falling edge sensitive ), as long as
one pin is stuck at ’0’, the other pin can never gen­erate an interrupt even if an act ive edge occurs at
this pin. The same thin g occurs when one pin is
stuck at ’1’ and interrupt vector #2 is configured as
rising edge sensitive.

To avoid this the f irst pin must input a signal that
goes back up to ’1’ right after the falling edge. Oth­erwise, in the interrupt rou tine for the first pin, de-

activate the “input with interrupt” mode using the
port control registers (DDR, OR, DR). An active
edge on another pin can then be latched.

I/O port Configuration Spurious Interrupt on

Vector #2

If a pin associated with interrupt vector #2 is in ‘in­put with pull-up’ st ate, a ‘0’ level is present on t he
pin and the ESB bit = 0, when the I/O pin is config­ured as interrupt with pull-up by writing to the
DDRx, ORx and DRx register bits, an interrupt is
latched although a falling edge may not have oc­curred on the associated pin.

In the opposite case, if the pin is in interrupt with
pull-up state , a 0 level is present on the pin and
the ESB bit =1, when the I/O po rt is con figured as
input with pull-up by writing to the DDRx, ORx and
DRx bits, an interrupt is latched although a rising
edge may not have occurred on the associated
pin.

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