SGS Thomson Microelectronics PSD834F2V Datasheet

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PRELIMINARY DATA

February 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PSD834F2V

Flash PSD, 3.3V Supply, for 8-bit MCUs

2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

FEATURES SUMMARY

■ Flash In-System Programmable (ISP)

Peripheral for 8-bit MCUs

■ 3.3 V±10% Single Supply Vo ltage

■ 2 Mbit of Primary Flash Memory (8 uniform

sectors, 32K x 8)

■ 256 Kbit Secondary Flash Memory (4 uniform

sectors)

■ 64 Kbit of battery-backed SRAM

■ Over 3,000 Gates of PLD: DPLD and CPLD

■ 27 Reconfigurable I/O ports

■ Enhanced JTAG Serial Port

■ Programmable power management

■ High Endurance:

– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD

Figure 1. Packages

PLCC52 (K)

PQFP52 (T)

PSD834F2V

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TABLE OF CONTENTS

Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Primary Flash Memory and Secondary Flash m emo ry Description. . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory Block Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Programming Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3

Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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PSD834F2V

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

MCU I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Input Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PSD834F2V

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Reset Timing and Device Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Warm Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0

I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Reset of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Programming In-Circuit using the JTAG Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Security and Flash memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

AC/DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table: CPLD Combinatorial Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table: CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table: CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table: Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table: Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table: Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table: Program, Write and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table: Port A Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table: Port A Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table: Reset (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table: VSTBYON Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table: ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table: Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table: PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular. . . . . . . . . . . . . . . . . . . . . . . . 83

Table: Pin Assignments – PLCC52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table: PQFP52 - 52 lead Plastic Quad Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table: Pin Assignments – PQFP52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table: Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

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PSD834F2V

SUMMARY DESCRIPTION

The PSD family of memory systems for microcon­trollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em­bedded designs. PSD dev ices combine many of
the peripheral functions found in MCU based ap­plications.

The CPLD in the PSD devices features an opti­mized macrocell logic architecture. The PSD mac­rocell was created to address the unique
requirements of embedded system designs. It al­lows direct connection between the system ad­dress/data bus, and the internal PSD registers, to
simplify communication between the MCU and
other supporting devices.

The PSD device includes a JTAG Serial Program­ming interface, to allow In-System Programming
(ISP) of the

entire device

. This feature reduces de­velopment time, simplifies the manufacturing flow,
and dramatically lowers the cost of field upgrades.

Using ST’s special Fast-JTAG programming, a de­sign can be rapidly programmed into the PSD in as
little as seven seconds.

The innovative PSD family solves key problems
faced by designers when managing discrete Flash
memory devices, such as:

– First-time In-System Programming (ISP)
– Complex address decoding
– Simulataneou s read and write to the device.
The JTAG Serial Interface block allows In-System

Programming (ISP), and e liminates the need for
an external Boot EPROM, or an external program­mer. To simplify Flash memory updates, program
execution is performed from a secondary Flash
memory while the primary Flash memory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im­plement IAP.

ST makes available a software devel opment tool,
PSDsoft Express, that generates ANSI -C compli­ant code for use with your target M CU. T his c ode
allows you to manipulate the non-v olatile me mory
(NVM) within the PSD. Code exam ples are also
provided for:

– Flash memory IAP via the UART of the host

MCU

– Memory paging to execute code across several

PSD memory pages

– Loading, reading, and manipulation of PSD

macrocells by the MCU.

PSD834F2V

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KEY FEATURES

■ A simple interface to 8-bit microcontrollers that

use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a read or write is performed. A partial list of the
MCU families supported include:

– Intel 8031, 80196, 80186, 80C251, and

80386EX

– Motorola 68HC11, 68HC16, 68HC12, and

683XX
– Philips 8031 and 8051XA
– Zilog Z80 and Z8

■ Internal 2 Mbit Flash memory. This is the main

Flash memory. It is divided into 8 equal-sized
blocks that can b e accessed with user-specifi ed
addresses.

■ Internal secondary 256 Kbit Flash boot memory.

It is divided into 4 equal-sized blocks that can be
accessed with user-specified addresses. This
secondary memory brings the ability to execute
code and update the main Flash

concurrently

.

■ Intern al 64 Kbit SRAM. The SRAM’s conte n ts

can be protected from a power failure by
connecting an external battery.

■ CPLD with 16 Output macrocells (OMCs) and

24 Input macrocells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.

■ Decode PLD (DPLD) that decodes address for

selection of internal memory blocks.

■ 27 individually configurable I/O port pins that

can be used for the following functions:
– MCU I/Os
–PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as

open-drain outputs.

■ Standby current as low as 25 µA.

■ Built-in JTAG compliant serial port allows full-

chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.

■ Internal page register that can be used to

expand the microcontroller address space by a
factor of 256.

■ Internal programmable Power Management

Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD into Power-down
mode.

■ Erase/Write cycles:

– Flash memory – 100,000 minimum
– PLD – 1,000 minimum
– Data Retention: 15 year minimum (for Main

Flash memory, Boot , PLD a nd Configurat ion
bits)

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PSD834F2V

Figure 2. PSD B l ock Di a gra m

PROG.

MCU BUS

INTRF.

ADIO

PORT

CNTL0,

CNTL1,

CNTL2

AD0 – AD15

CLKIN

(PD1)

CLKIN

CLKIN

PLD

INPUT

BUS

PROG.

PORT

PORT

A

PROG.

PORT

PORT

B

POWER

MANGMT

UNIT

2 MBIT PRIMARY

FLASH MEMORY

8 SECTORS

VSTDBY

PA0 – PA7

PB0 – PB7

PROG.

PORT

PORT

C

PROG.

PORT

PORT

D

PC0 – PC7

PD0 – PD2

ADDRESS/DATA/CONTROL BUS

PORT A ,B & C

3 EXT CS TO PORT D

24 INPUT MACROCELLS

PORT A ,B & C

73

73

256 KBIT SECONDARY

NON-VOLATILE MEMORY

(BOOT OR DATA)

4 SECTORS

64 KBIT BATTERY

BACKUP SRAM

RUNTIME CONTROL

AND I/O REGISTERS

SRAM SELECT

PERIP I/O MODE SELECTS

MACROCELL FEEDBACK OR PORT INPUT

CSIOP

FLASH ISP CPLD

(CPLD)

16 OUTPUT MACROCELLS

FLASH DECODE

PLD

(

DPLD

)

PLD, CONFIGURATION

& FLASH MEMORY

LOADER

JTAG

SERIAL

CHANNEL

(

PC2

)

PAGE

REGISTER

EMBEDDED

ALGORITHM

SECTOR

SELECTS

SECTOR

SELECTS

GLOBAL

CONFIG. &

SECURITY

AI05793

8

PSD834F2V

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PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional
blocks. Figur e 2 shows the architect ure of the PSD
device family. The functions of each block are de­scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.

Memory

Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus-

sion can be found in the section entitled “Memory
Blocks“ on page 15.

The 2 Mbit (256K x 8) Flash m emory is the primary
memory of the PSD. It is divided into 8 equally­sized sectors that are individually selectable.

The 256 Kbit (32K x 8) se condary Flash memory
is divided into 4 equally-sized sectors. Each sector
is individually selectable.

The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (VSTBY, PC2), data is retained
in the event of power failure.

Each sector of mem ory c an be l oc ated in a dif fer­ent address space as defined by the user. The ac­cess times for all memory types includes the
address latching and DPLD decoding time.

Page Re gi st er

The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in­ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different mem­ory spaces for IAP.

PLDs

The device contains tw o PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 1, each op timized for a di fferent fun ction.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.

Table 1. PLD I/O

The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter­nal memory and regis ters. The DPLD has combi­natorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.

The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of product terms, and macrocells.

The PLDs consume minimal power. The speed
and power consumption of the PLD i s controlled
by the Turbo bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga­tion time when invoking the power m anagement
features.

I/O Po r t s

The PSD has 27 individually configurable I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad­dress outputs for MCUs using multiplexed ad­dress/data buses.

The JTAG pins can be enabled on Po rt C for In­System Programming (ISP).

Ports A and B can also be conf igured as a data
port for a non-multiplexed bus.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad­dress/data buses. The device is configured to re­spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see the section entitled “MCU Bus Interface Exam­ples“ on page 39.

Table 2. JTAG SIgnals on Port C

JTAG Port

In-System Programming (ISP) can be pe rformed
through the JTAG signals on Port C. This serial in­terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT

, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 2 indicates the
JTAG pin assignments.

Name Inputs Outputs

Product

Terms

Decode PLD (DPLD) 73 17 42
Complex PLD (CPLD) 73 19 140

Port C Pins JTAG Signal

PC0 TMS
PC1 TCK
PC3 TSTAT
PC4 TERR
PC5 TDI
PC6 TDO

9/89

PSD834F2V

In-System Progr a mming (ISP)

Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased wit hout the
use of the MCU. The primary Flash memory can
also be programmed in-system by the M CU exe­cuting the programming algorithms out of the sec­ondary memory, or SRAM. The secondary

memory can be programmed the same way by ex­ecuting out of the primary Flash memory. The PLD
or other PSD Configuration blocks can be pro­grammed through the J TAG port or a de vice pro­grammer. Table 3 indicates which programming
methods can program different functional blo cks
of the PSD.

Table 3. Methods of Programming Different Functional Blocks of the PSD

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system req uirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.

The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump­tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD l atches its outputs and
goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD t o
reduce power consumption. Please s ee the sec-

tion entitled “Power Management” on page 55 for
more details.

Functional Block JTAG Programming Device Programmer IAP

Primary Flash Memory Yes Yes Yes
Secondary Flash Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No

PSD834F2V

10/89

DEVELOPMENT SYST EM

The PSD family is supported by PSDsoft Express,
a Windows-based software development tool. A
PSD design is quicly and easily produced in a
point and click environment. The designer does
not need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
pin functions and memo ry map information. The
general design flow is shown in Figure 3. PSDsoft
Express is available from our web site (the ad-

dress is given on the back page of this data sheet)
or other distribution channels.

PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by t hid
party device programmers. See our web site for
the current list.

Figure 3. PSDsoft Express Developmen t Tool

PSD Configuration

PSD Fitter

PSD Simulator

PSD Programmer

*.OBJ FILE

PLD DESCRIPTION

CONFIGURE MCU BUS

INTERFACE AND OTHER

PSD ATTRIBUTES

LOGIC SYNTHESIS

AND FITTING

PSDsilos III

DEVICE SIMULATION

(OPTIONAL)

PSDPro, or

FlashLINK (JTAG)

ADDRESS TRANSLATION

AND MEMORY MAPPING

PSDabel

MODIFY ABEL TEMPLATE FILE

OR GENERATE NEW FILE

PSD TOOLS

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

USER'S CHOICE OF

MICROCONTROLLER

COMPILER/LINKER

*.OBJ AND *.SVF

FILES AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

(CONVENTIONAL or

JTAG-ISC)

FIRMWARE

HEX OR S-RECORD

FORMAT

AI04918

11/89

PSD834F2V

PIN DESCRIPTION

Table 4 describes the signal names and signal
functions of the PSD.

Table 4. Pin Description (for the PLCC52 package

1

)

Pin Name Pin Type Description

ADIO0-7 30-37 I/O

This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:

1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.

2. If your MCU does not have a multiplexed address/data bus, or you are using an
80C251 in page mode, connect A0-A7 to this port.

3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.

ADIO8-15 39-46 I/O

This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:

1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.

2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.

3. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks was selected. The addresses on this port are
passed to the PLDs.

CNTL0 47 I

The following control signals can be connected to this port, based on your MCU:

1. WR

– active Low Write Strobe input.

2. R_W

– active High read/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.

CNTL1 50 I

The following control signals can be connected to this port, based on your MCU:

1. RD

– active Low Read Strobe input.

2. E – E clock input.

3. DS

– active Low Data Strobe input.

4. PSEN

– connect PSEN to this port when it is being used as an active Low read signal.

For example, when the 80C251 outputs more than 16 address bits, PSEN

is actually the
read signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.

CNTL2 49 I

This port can be used to input the PSEN

(Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.

Reset

48 I

Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.

PSD834F2V

12/89

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

29
28
27
25
24
23
22
21

I/O

These pins make up Port A. These port pins are configurable and can have the following
functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.

6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

7
6
5
4
3
2
52
51

I/O

These pins make up Port B. These port pins are configurable and can have the following
functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0 20 I/O

PC0 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC0) output.

3. Input to the PLDs.

4. TMS Input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 19 I/O

PC1 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC1) output.

3. Input to the PLDs.

4. TCK Input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC2 18 I/O

PC2 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC2) output.

3. Input to the PLDs.

4. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
This pin can be configured as a CMOS or Open Drain output.

PC3 17 I/O

PC3 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC3) output.

3. Input to the PLDs.

4. TSTAT

output2 for the JTAG Serial Interface.

5. Ready/Busy

output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 14 I/O

PC4 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC4) output.

3. Input to the PLDs.

4. TERR

output2 for the JTAG Serial Interface.

5. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external battery.
This pin can be configured as a CMOS or Open Drain output.

Pin Name Pin Type Description

13/89

PSD834F2V

Note: 1. The pi n numbers in th i s t abl e are for the PLCC package only. See the package inf ormation, on page 83 onwards, for pin nu mb ers

on other package types.

2. These func tions can be multiplexe d wi th other functions.

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al­located by the user to the internal PS D registers.

Table 6 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.

PC5 13 I/O

PC5 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC5) output.

3. Input to the PLDs.

4. TDI input

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6 12 I/O

PC6 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC6) output.

3. Input to the PLDs.

4. TDO output

2

for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC7 11 I/O

PC7 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC7) output.

3. Input to the PLDs.

4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.

PD0 10 I/O

PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input latches address output from the MCU.

2. MCU I/O – write or read from a standard output or input port.

3. Input to the PLDs.

4. CPLD output (External Chip Select).

PD1 9 I/O

PD1 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.

PD2 8 I/O

PD2 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. Input to the PLDs.

3. CPLD output (External Chip Select).

4. PSD Chip Select Input (CSI

). When Low, the MCU can access the PSD memory and I/

O. When High, the PSD memory blocks are disabled to conserve power.

V

CC

15, 38 Supply Voltage

GND

1, 16,
26

Ground pins

Pin Name Pin Type Description

PSD834F2V

14/89

Table 5. I/O Port Latched Address Output Assignments

1

Note: 1. See the section entitled “I /O Ports”, on page 45, on how to enable the Lat ched Addre ss Output fun ct i on.

2. N/A = Not Applicable

Table 6. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

MCU

Port A Port B

Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)

8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A
80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12
All other 8-bit multiplexed Address a3-a0 Address a 7-a4 Address a 3-a0 Address a7-a4
8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4

Register Name Port A Port B Port C Port D

Other

1

Description

Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode
Control 02 03 Selects mode between MCU I/O or Address Out

Data Out 04 05 12 13

Stores data for output to Port pins, MCU I/O output
mode

Direction 06 07 14 15 Configures Port pin as input or output

Drive Select 08 09 16 17

Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.

Input Macrocell 0A 0B 18 Reads Input Macrocells

Enable Out 0C 0D 1A 1B

Reads the status of the output enable to the I/O
Port driver

Output Macrocells
AB

20 20

Read – reads output of macrocells AB
Write – loads macrocell flip-flops

Output Macrocells
BC

21 21

Read – reads output of macrocells BC

Write – loads macrocell flip-flops
Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash

Protection

C0 Read only – Primary Flash Sector Protection

Secondary Flash
memory Protection

C2

Read only – PSD Security and Secondary Flash

memory Secto r Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register

VM E2

Places PSD memory areas in Program and/or

Data space on an individual basis.

15/89

PSD834F2V

DETAILED OPERATION

As shown in Figure 2, the PSD consists of six ma­jor types of functional blocks:

■ Memory Blo c k s

■ PLD Bl o c ks

■ MCU Bus Interface

■ I/O Por ts

■ Power Management Unit (PMU)

■ JTAG In te rfac e

The functions of ea ch block are described i n the
following sections. Many of the blocks perform
multiple functions, and are user configurable.

MEMORY BLOCKS

The PSD has the following memory blocks:

– Primary Flash memory
– Secondary Flash memory
–SRAM
The Memory Select signals for these blocks origi-

nate from the Decode PLD (DPLD) an d are user­defined in PSDsoft Express.

Primary Flash Memory and Secondary Flash
memory Description

The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four e qual sectors. Each sector of
either memory block can be sepa rately protected
from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec­tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.

During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy

(PC3).
This pin is set up using PSDsoft Express Configu­ration.

Memory Block Select Signals

The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs”, on page 27). Each of the eigh t sectors of
the primary Flash memory has a Select signal

(FS0-FS7) which can contain up t o three product
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0­CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ­ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.

Ready/Busy

(PC3 ). This signal can be used to

output the Ready/Busy

status of the PSD. The out-

put on Ready/Busy

(PC3) is a 0 (Busy) when Flash

memory is being written to,

or

when Flash memory
is being erased. The output is a 1 (Ready) when
no Write or Erase cycle is in progress.

Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac­cess these memories in one of two ways:

■ The MCU can execute a typical bus Write or

Read

operation

just as it would if accessing a

RAM or ROM device using standard bus cycles.

■ The MCU can execute a specific instruction that

consists of several Write and Read operations.
This invo lv es writ in g specific da ta pat t er ns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 7.

Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM de­vice. However, Flash memory can only b e altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di­rectly to Flash memory as it would write a by te to
RAM. To program a byte into F lash memory, t he
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a Read operation or polling
Ready/Busy

(PC3).

Flash memory can also be read by using special
instructions to retrieve particular F lash device in­formation (sector protect status and ID).

PSD834F2V

16/89

Table 7. Instructions

Note: 1. All bus cycles are write bus cycles, except the ones with the “Read” label

2. All value s are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this tab l e, must be even addresses
RA = Address of the memory l ocation to be read
RD = Data read from loca ti on RA during t he Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR

, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programm ed at location PA. Data is la tc hed on the rising edge of Write Strobe (WR

, CNTL0)
SA = Addr ess of t he sect or to be erased or ve rified. Th e Sect or Sel ect (FS0- FS7 o r CSBOOT 0-CSBO OT3) of the se ctor t o be
erased, or verified, must be Active (High).

3. Sector Se l ect (FS0 to FS7 or CSBOOT 0 to CSBOOT3) signals are a ct i ve High, and ar e defined in PSD soft Expre ss .

4. Only address bits A11-A0 are used in instruction decoding.

5. No Unlock or instruction cycles are required when the devic e i s in the Read mode

6. The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection St at us ,
or if the Error Flag (DQ5/DQ13) bit goes High.

7. Additional sectors to be erased must be written a t the end of the Sec tor Erase inst ruction within 80 µs.

8. The data i s 00h for an unp rotected sec tor, and 01h for a protecte d sector. In the fourth cyc le, the Secto r Select is ac tive, and
(A1,A0)= (1,0)

9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10. The Unlock Bypas s R eset Flash i nstruction is requi red to retu rn to reading memory data when the device is in the Unlock Bypass
mode.

11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mo de. The Suspe nd S ector Erase instructi on is valid only during a Sec tor Erase cycl e.

12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13. The MCU can not i nvok e these instru ct ion s whil e execu tin g code fr om th e sam e Flash mem ory as that for whi ch th e ins truc tion is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of th e pr i m ary Flash memory.

Instruction

FS0-FS7 or

CSBOOT0-

CSBOOT3

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

Read

5

1

“Read”
RD @ RA

Read Main
Flash ID

6

1

AAh@
X555h

55h@
XAAAh

90h@
X555h

Read identifier
(A6,A1,A0 = 0,0,1)

Read Sector
Protection

6,8,13

1

AAh@
X555h

55h@
XAAAh

90h@
X555h

Read identifier
(A6,A1,A0 = 0,1,0)

Program a
Flash Byte

13

1

AAh@
X555h

55h@
XAAAh

A0h@
X555h

PD@ PA

Flash Sector
Erase

7,13

1

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ XAAAh

55h@
XAAAh

30h@
SA

30h

7

@

next SA

Flash Bulk
Erase

13

1

AAh@
X555h

55h@
XAAAh

80h@
X555h

AAh@ XAAAh

55h@
XAAAh

10h@
X555h

Suspend
Sector Erase

11

1

B0h@
XXXXh

Resume
Sector Erase

12

1

30h@
XXXXh

Reset

6

1

F0h@
XXXXh

Unlock Bypass 1

AAh@
X555h

55h@
XAAAh

20h@
X555h

Unlock Bypass
Program

9

1

A0h@
XXXXh

PD@ PA

Unlock Bypass
Reset

10

1

90h@
XXXXh

00h@
XXXXh

17/89

PSD834F2V

INSTRUCTIONS

An instruction consists of a sequence of specific
operations. Each received byte is sequentially de­coded by the PSD and not executed as a standard
Write operation. The instruction is e xecuted when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out period. Some instruc­tions are structured to include Read operations af­ter the initial Write operations.

The instruction must be followe d exactly. Any in­valid combination of instruction bytes or time-out
between two consecutive byte s while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).

The PSD supports the instructions sum ma riz ed in
Table 7:

Flash memory:

■ Erase memory by chip or sector

■ Suspend or resume sector erase

■ Program a Byte

■ Reset to Read mode

■ Read primary Flash Identifier value

■ Read Sector Protection Status

■ Bypass

These instructio ns are det ailed i n Table 7. For e f­ficient decoding of the instructions, the first two
bytes of an instruction are the c oded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during the second cy-

cle. Address signals A15-A12 are Don’t Care dur­ing the instruction Write cycles. However, the
appropriate Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT 3 ) must be selected.

The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals deter­mine which Flash memory is to receive and exe­cute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0­CSBOOT3) is High.

Power-do wn Instruction and Power- up Mode
Power-up Mode. The PSD internal logic is reset

upon Power-up to the Read mode. S ector Select
(FS0-FS7 and CSBOOT0-CSBOOT3) must be
held Low, and Write Strobe (WR

, CNTL0) High,
during Power-up for maximum security of the data
contents and to remove the possibility of a byte be­ing written on the first edge of Write Strobe (WR

,

CNTL0). Any Write cycle initiation is locked when
V

CC

is below V

LKO

.

READ

Under typical conditions, the MCU may read t he
primary Flash memory or the secondary Flash
memory using Read operations just as it would a
ROM or RAM device. Alternately, the MCU may
use Read operations to obtain status informat ion
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.

Read Memory Contents. Prima ry Flash memo ry
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 7). The MCU can read
the memory contents of the primary Flash memory
or the secondary Flash memory by using Read op­erations any time the Read operation is not part of
an instruction.

Read Primary Flash Identifier. The primary
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific Write opera­tions and a Read operation (see T able 7). During
the Read operation, address bits A6, A1, and A0
must be 0,0,1, respectively, and the appropriate
Sector Select (FS0-FS 7) m ust be High. The iden­tifier for the device is E7h.

Read Memory Sector Protection Status. The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific Write operations and a Read operation
(see Table 7). During the Read operation, address
bits A6, A1, and A0 must be 0,1,0, respectively,
while Sector Select (FS0-FS7 or CSBOOT0­CSBOOT3) designates the Flash memory sector
whose protection has to be verified. The Read op­eration produces 01h if the Flash memory sector is
protected, or 00h if the sector is not protected.

The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem­ory) can also b e read by the MCU accessing the
Flash Protection registers in PSD I/O space. See
the section entitled “Flash Memory Sector Pro­tect”, on page 22, for register definitions.

Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
MCU to confirm the completion of an Erase or Pro­gram cycle of Flash memory. These status bits
minimize the time that the MCU spends perform­ing these tasks and are defined in Table 8. The
status bits can be read as many times as needed.

For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entit led

PSD834F2V

18/89

“Programming Flash Memory”, on page 19, for de­tails.

Table 8. Status Bit

Note: 1. X = Not guarante ed value, can be read either 1 or 0.

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.

3. FS0-FS7 and CSBOOT 0-CSBOOT 3 are activ e Hi gh.

Data Polling Flag (DQ7). When erasing or pro­gramming in Flash memory, the Data Polling Flag
(DQ7) bit outputs the co mplem ent of the bit bei ng
entered for programming/writing on the DQ7 bit.
Once the Program instruction or the Write opera­tion is completed, the true logic value is read on
the Data Polling Flag (DQ7) bit (in a Read opera­tion) .

■ Data Polling is effective after the fourth Write

pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.

■ During an Erase cycle, the Data Polling Flag

(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bit outputs
the last bit programmed (it is a 1 after erasing).

■ If the byte to be programmed is in a protected

Flash memory sector, the instruction is ignored.

■ If all the Flash memory sectors to be erased are

protected, the Data Polling Flag (DQ7) bit is
reset to 0 for about 100 µs, and then returns to
the previous addressed byte. No erasure is
performed.

Toggle Flag ( DQ6 ). The PSD offers another way
for determining when the Flash memory Program
cycle is completed. During the internal Write oper­ation and when either the FS0-FS7 or CSBOOT0­CSBOOT3 is true, the Toggle Flag (DQ6) bit tog­gles from 0 to 1 and 1 to 0 on subsequent attempts
to read any byte of the memory.

When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed mem ory byte. The device is now
accessible for a new Read or Write operation. The
cycle is finished when two successive Reads yield
the same output data.

■ The Toggle Flag (DQ6) bit is effective after the

fourth Write pulse (for a Program instruction) or
after the sixth Write pulse (for an Erase
instruction).

■ If the byte to be programmed belongs to a

protected Flash memory sector, the instruction
is ignored.

■ If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag (DQ6) bit
toggles to 0 for about 100 µs and then returns to
the previous addressed byte.

Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag (DQ5) bit is to 0. T his
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.

In the case of Flash memory programming, the Er­ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, whi ch is not vali d. The Error
Flag (DQ5) bit may also indicate a Time-out condi­tion while attempting to program a byte.

In case of an error in a Flash memory Sector Erase
or Byte Progra m cycle, the Fl ash memory sector i n
which the error occurred or to which the pro­grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.

Erase Time-out Flag (DQ3). The Erase Time­out Flag (DQ3) bit reflects the time-out period al­lowed between two consecutive Sec tor Erase in­structions. The Erase Time-out Flag (DQ3) bit is
reset to 0 after a Sector Erase cycle for a time pe­riod of 100 µs + 20% unless an additiona l Sector
Erase instruction is decoded. After this time peri­od, or when the additional Sector Erase instruction
is decoded, the E rase Time-out Flag (DQ3) bit is
set to 1.

Functional Block

FS0-FS7/CSBOOT0-

CSBOOT3

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Flash Memory

V

IH

Data

Polling

Toggle

Flag

Error

Flag

X

Erase
Time-

out

XXX

19/89

PSD834F2V

Programming Flash Memory

Flash memory mus t be erased prior to bei ng pro­grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to 0. The MCU may erase Fl ash memory all at
once or by-sector, but not byte-by-byte. Howe ver,
the MCU may program Flash memory byte-by­byte.

The primary and secondary Flash memories re­quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 7).

Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked inside the P S D support sev eral m eans t o
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy

(PC3).

Data Polling. Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a Pro­gram or Erase cycle is in progress or has complet­ed. Figure 4 shows the Data Polling algorithm.

When the MCU issue s a Program ins truction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro­grammed in Flash memory to check status. The
Data Polling Flag (DQ7) bit of this location be­comes the complem ent of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Dat a Polling Fl ag
(DQ7) bit and monitoring the Error Flag (DQ5) bit.
When the Data Polling Flag (DQ7) bit matches b7
of the original data, and the E rror Flag (DQ5) bit
remains 0, the embedded algorithm is complete. If
the Error Flag (DQ5) bit is 1, the MCU should test
the Data Polling Flag (DQ7) bit again since the
Data Polling Flag (DQ7) bit may have changed si­multaneously with the Error Flag (DQ5) bit (see
Figure 4).

The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU a t­tempted to program a 1 to a bit that was not erased
(not erased is logic 0).

It is suggested (as with all Flash memories) to read
the location again after the embedded program­ming algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.

When using the Data Polling method during an
Erase cycle, Figure 4 still applies. However, the
Data Polling Flag (DQ7) bit is 0 until the Erase cy­cle is complete. A 1 on the Error Flag (DQ5) bit in­dicates a time-out condition on the Erase cycle; a
0 indicates no error. The MCU can read any loca-

tion within the sector being erased to get the Data
Polling Flag (DQ7) bit and the Error Flag (DQ5) bit.

PSDsoft Express generates ANSI C code func­tions which implement these Data Polling algo­rithms.

Figure 4. Dat a Po ll i ng F lo wc h a rt

Data Toggle. Checking the Toggle Flag (DQ6) bit

is a method o f det erm ining whether a Pr ogram or
Erase cycle is in progress or has completed. Fig­ure 5 shows the Data Toggle algorithm.

When the MCU issue s a Program ins truction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro­grammed in Flash memory to check status. The
Toggle Flag (DQ6) bit of this location toggles each
time the MCU reads this location until the embed­ded algorithm is complete. The MCU cont inues t o
read this location, checking the Toggle Flag (DQ6)
bit and monitoring the Error Flag (DQ5) bit. When
the Toggle Flag (DQ6) bit stops toggling (two con­secutive reads yield the same value), and the Er­ror Flag (DQ5) bit remains 0, the embedded
algorithm is complete. If the Error Flag (DQ5) bit is
1, the MCU should test the Toggle Flag (DQ6) bit
again, since the Toggle Flag (DQ6) bit may have
changed simultaneously with the Error Flag (DQ5)
bit (see Figure 5).

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369B

DQ7

=

DATA

YES

NO

YES

NO

DQ5

= 1

DQ7

=

DATA

YES

NO

PSD834F2V

20/89

Figure 5. Dat a Toggle Flow cha rt

The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at­tempted to program a 1 to a bit that was not erased
(not erased is logic 0).

It is suggested (as with all Flash memories) to read
the location again after the embedded program­ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.

When using the Data Toggle method after an
Erase cycle, Figure 5 still applies. the Toggle Flag
(DQ6) bit toggles until the Erase cycle is complete.
A 1 on the Error Flag (DQ5) bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er­ror. The MCU can read any location within the sec­tor being erased to get the To ggle Flag (DQ 6) bit
and the Error Flag (DQ5) bit.

PSDsoft Express generates ANSI C code func­tions which implement these Data T oggling algo­rithms.

Unlock Bypass. The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unloc k Bypass mode is ent ered
by first initiati ng two Unlo ck cycles. T his is fol lowed
by a third Write cycle cont aining the Unlock By­pass code, 20h (as shown in Table 7).

The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in­struction is all that is required t o program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec­ond cycle contains the program address and data.
Additional data is programmed in t he same man­ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro­gram instruction, resulting in faster total Flash
memory programming.

During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.

To exit th e Un l o ck Bypass mode, the system must
issue the t wo-cycl e Unl ock Bypass Reset Fl ash i n­struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are

Don’t Care for both cycles. The Flash memory
then returns to Read mode.

Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruc-

tion uses six Write operat ion s followed by a Read
operation of the status register, as described in
Table 7. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Flash memory status.

During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bi t, and the Dat a Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro­gramming Flash Memory”, on page 19. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).

It is not necessary to program the memory with
00h because the PSD automatically does this be­fore erasing to 0FFh.

During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.

Flash Sector Erase. The Sector Erase instruc­tion uses six Write operations, as described in Ta­ble 7. Additional Flash Sector Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec­tors in parallel, without further coded cycles, if the
additional bytes are transm itted in a shorter time
than the time-out period of about 100 µs. The input
of a new Sector Erase code restarts the time-out
period.

The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out period is counting. If the Er ase Time­out Flag (DQ3) bit is 1, the time-out period has ex­pired and the PSD is busy erasing the Flash mem-

READ

DQ5 & DQ6

START

READ DQ6

FAIL PASS

AI01370B

DQ6

=

TOGGLE

NO

NO

YES

YES

DQ5

= 1

NO

YES

DQ6

=

TOGGLE

21/89

PSD834F2V

ory sector(s). Before and d uring Erase time-out,
any instruction other than Suspend S ector Erase
and Resume Sector Erase instructions abort the
cycle that is currently in progress, and reset the
device to Read mode. It is not necessary to pro­gram the Flash memory sector with 00h as the
PSD does this automatically before erasing
(byte=FFh).

During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bi t, and the Dat a Polling Flag

(DQ7) bit, as detailed in the section entitled “Pro­gramming Flash Memory”, on page 19.

During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and t hen re­sumed .

Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in­struction can be used to suspend the cycle by writ­ing 0B0h to any address when an appropriate
Sector Se lect (FS0 -FS7 or CSBO OT0-CSBOOT3 )
is High. (See Table 7). This allows reading of data
from another Flash memory sector after the Erase
cycle has been suspended. Suspend Sector
Erase is accepted only during an E rase c ycle and
defaults to Read mode. A Suspe nd Sector Erase
instruction executed during an Erase time-out pe-

riod, in addition to suspending the Erase cycle, ter­minates the time out period.

The Toggle Flag (DQ6) bit stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag (DQ6) bit stops toggling between 0.1 µs and
15 µs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to Read mode.

If an Suspend Sector Erase instruction was exe­cuted, the following rules apply:

– Attempting to read from a Flash memory sector

that was being erased outputs invalid data.

– Reading from a Flash sector that was

not

being

erased is valid.

– The Flash memory

cannot

be programmed, and
only responds to Resume Sector Erase and Re­set Flash instructions (Read is an operation and
is allowe d) .

– If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased
is invalid .

Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector Eras e instruction consists of
writing 030h to any address w hile an appropriate
Sector Se lect (FS0 -FS7 or CSBO OT0-CSBOOT3 )
is High. (See Table 7.)

PSD834F2V

22/89

Specific Features
Flash Memory Sector Protect. Each primary

and secondary Flash memory sector can be sepa­rately protected against Program and Erase cy­cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.

Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro­gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec-

tors can be unprotected to allow updating of their
contents using the JTAG Port or a Device Pro­grammer. The MCU can read (but cannot change)
the sector protection bits.

Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a read of the protected data.
This allows a guarantee of the retention of the Pro­tection status.

The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Table 9 and Table 10.

Table 9. Sector Protection/Security Bit Definition – Flash Protection Register

Note: 1. Bit Defin it i ons:

Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flas h m em ory or secondary Flash mem ory Sector <i> is not write prot ected.

Table 10. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Note: 1. Bit Defin it i ons:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Securi ty Bit in dev i ce has not been set.

1 = Security Bi t in device has been set.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

23/89

PSD834F2V

Reset Flash. The Reset Flash instruction con-

sists of one Write cycle (see Table 7). It can also
be optionally preceded by the standard two write
decoding cycles (writing AAh to 555h and 55 h to
AAAh). It must be executed after:

– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device

has set the Error Flag (DQ5) bit to 1) during a
Flash memory Program or Erase cycle.

The Reset Flash instruction puts the Flash memo­ry back into normal Read mode. If an Error condi­tion has occurred (and the device has set the Error
Flag (DQ5) bit to 1) the Flash memo ry is put back
into normal Read mode within 25 µ s of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur­ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal Read mode within
25 µs.

Reset (RESET

) Signal. A pulse on Reset (RE-

SET) aborts any cycle that is in progress, and re­sets the Flash memory to the Read mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25 µ s to retur n to
the Read mode. It is recommended that the Reset
(RESET

) pulse (except for Power On Reset, as
described on page 60) be at least 25 µs so that the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cy­cle is complete.

SRAM

The SRAM i s enabled when SR AM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two prod uct terms, allow ing flexible
memory mapping.

The SRAM can be backed up usin g an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PC2). If you have an
external battery connected to the P SD, the con­tents of the SRAM are reta ined in the event of a
power loss. The contents of the SRAM are re­tained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.

PC4 can be configured as an output that indicates
when power is being drawn from the external ba t-

tery. Battery-on Indicator (VBATON, PC4) is High
with the supply voltage falls below the battery volt­age and the battery on Voltage Stand-by (VSTBY,
PC2) is supplying power to the internal SRAM.

SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Configu­ration.

Sector Select and SRAM Select

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDabel. The f oll owing rules ap ply t o t he
equations for these signals:

1. Primary Flash memory and secondary Flash
memory Sector Select signals must

not

be larg -

er than the physical sector size.

2. Any primary Flash memory sect or must

not

be
mapped in the same memory space as another
Flash memory sector.

3. A secondary Flash m emory sect or must

not

be
mapped in the same memory space as another
secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not

overlap.

5. A secondary Flash memory sector

may

overlap
a primary Flash memory sector. In case of over­lap, priority is given to the secondary Flash
memory se c tor .

6. SRAM, I/O, and Peripheral I/O spaces

may

overlap any other memory sector. Priority is giv­en to the SRAM, I/O, or Peripheral I/O.

Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000 h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses seco ndary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash me mory seg­ment 0. You can see that half of the primary Flash
memory segment 0 and one-fou rth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also no te that an equation t hat de­fined FS1 to anywhere in the range of 8000h to
BFFFh would

not

be valid.

PSD834F2V

24/89

Figure 6. Priority Level of Memory and I/O
Components

Figure 6 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must

not

overlap. Level one has the highest priority and

level 3 has the lowest.

Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The 8 031

and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA, have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN

,
CNTL2)) and Data memory (selected using Read
Strobe (RD

, CNTL1)). Any of the memories within
the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM
register that resides in the CSIOP space.

The VM register is set using PSDsof t Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.

For example, you may wish to have SRAM and pri­mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later s wap t he primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav­ing the MCU change it when desired.

Table 11 describes the VM Register.

Table 11. VM Register

Level 1

SRAM, I/O, or
Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Highest Priority

Lowest Priority

Level 3

Primary Flash Memory

AI02867D

Bit 7

PIO_EN

Bit 6 Bit 5

Bit 4

Primary

FL_Data

Bit 3

Secondary

EE_Data

Bit 2

Primary

FL_Code

Bit 1

Secondary

EE_Code

Bit 0

SRAM_Code

0 = disable
PIO mode

not used not used

0 = RD

can’t
access
Flash
memory

0 = R

D can’t
access Secondary
Flash memory

0 = PSEN
can’t
access
Flash
memory

0 = PSE

N can’t
access Secondary
Flash memory

0 = PSEN
can’t
access
SRAM

1= enable
PIO mode

not used not used

1 = RD
access
Flash
memory

1 = R

D access
Secondary Flash
memory

1 = PSEN
access
Flash
memory

1 = PSE

N access
Secondary Flash
memory

1 = PSEN
access
SRAM

25/89

PSD834F2V

Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate Space
Modes. Program space is separated from Data

space. For example, Program Select Enable
(PSEN

, CNTL2) is used to access the program

code from the primary Flash memory, while Read
Strobe (RD

, CNTL1) is used to access dat a from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM register
to be set to 0Ch (see Figure 7).

Figure 7. 8031 Memory Modules – Separate Spac e

Combined Space Modes. The Program and

Data spaces are combined into one memory
space that allows the primary Flash memory, sec­ondary Flash memory, and SRAM to be accessed
by either Program Select Enable ( PSEN

, CNTL2)

or Read Strobe (RD

, CNTL1). For example, to
configure the primary Flash mem ory in Combi ned
space, bits b2 and b4 of the VM register are set to
1 (see Figure 8).

Figure 8. 8031 Memory Modules – Combine d Space

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-3

FS0-FS7

CS CSCS

OE OE

RD

PSEN

OE

AI02869C

Primary

Flash

Memory

DPLD

Secondary

Flash

Memory

SRAM

RS0

CSBOOT0-3

FS0-FS7

RD

CS CSCS

RD

OE OE

VM REG BIT 2

PSEN

VM REG BIT 0

VM REG BIT 1

VM REG BIT 3

VM REG BIT 4

OE

AI02870C

PSD834F2V

26/89

Page Re gi st er

The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0­PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT 3), and SRAM Select (RS0)
equations.

If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for gen eral
logic. See Application Note

AN1154

.

Figure 9 shows the Page Regist er. The eight flip­flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.

Figure 9. Page Re g ist er

RESET

D0-D7

R/W

D0 Q0

Q1
Q2
Q3
Q4
Q5
Q6
Q7

D1
D2
D3
D4
D5
D6
D7

PAGE

REGISTER

PGR0
PGR1

PGR2
PGR3

DPLD

AND

CPLD

INTERNAL
SELECTS
AND LOGIC

PLD

PGR4
PGR5
PGR6
PGR7

AI02871B

27/89

PSD834F2V

PLDS

The PLDs bring programmable logic f unctionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the dev ice and av ailable
upon Power-up.

Table 12. DPL D a nd CP LD I nputs

Note: 1. The address inpu ts are A19-A4 in 80C51XA mode.

The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next f ew paragraphs,

and in more detail in the sec tion entitled “Dec ode
PLD (DPLD)”, on page 29, and the section entitled
“Complex PLD (CPLD)”, also on page 30. Figure
10 shows the configuration of the PLDs.

The DPLD performs add ress decoding for Sel ect
signals for internal components, such as memory,
registers, and I/O ports.

The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma­chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0­ECS2) signals.

The AND Array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table 12.

The Turbo Bit i n PSD

The PLDs in the PSD c an minimize power con­sumption by switching off when inputs remain un­changed for an extended time of about 70 ns.
Resetting the Turbo bit to 0 (Bit 3 of PMMR0) au­tomatically places the PLDs into standby if no in­puts are changing. Turning the Turbo mode off
increases propagation delays while reducing pow­er consumption. See the section entitled “Power
Management”, on page 55, on how to set the Tur­bo bit.

Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.

Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.

Input Source Input Name

Number

of

Signals

MCU Address Bus

1

A15-A0 16

MCU Control Signals CNTL2-CNTL0 3
Reset RST

1
Power-down PDN 1
Port A Input

Macrocells

PA7-PA0 8

Port B Input
Macrocells

PB7-PB0 8

Port C Input
Macrocells

PC7-PC0 8

Port D Inputs PD2-PD0 3
Page Register PGR7-PGR0 8
Macrocell AB

Feedback

MCELLAB.FB7­FB0

8

Macrocell BC
Feedback

MCELLBC.FB7­FB0

8

Secondary Flash
memory Program
Status Bit

Ready/Busy

1