SGS Thomson Microelectronics PSD511B1, PSD512B1, PSD513B1, PSD501B1, PSD502B1 Datasheet

...

1/3

NOT FOR NEW DESIGN

January 2002

This is information on a product still in production but not recommended for new designs.

PSD5XX

ZPSD5XX

Low Cost Field Programmable Microcontroller Peripherals

FEATURES SUMMARY

■ Single Supply Voltage:

– 5 V±10% for PSD5XX – 2.7 to 5.5 V for PSD5XX-V

■ Up to 1 Mbit of UV EPROM

■ Up to 16 Kbit SRAM

■ Input Latches

■ Programmable I/O ports

■ Page Logic

■ Programmable Security

Figure 1. Packages

PLDCC68 (J)

CLDCC68 (L)

TQFP68 (U)

PSD5XX Family

PSD5XX/ZPSD5XX

Field-Programmable Microcontroller Peripherals

Table of Contents

1 Introduction...........................................................................................................................................................1

2 Key Features ........................................................................................................................................................3

3 Notation ................................................................................................................................................................4

4 ZPSD Background................................................................................................................................................4

5 Integrated Power ManagementTMOperation........................................................................................................6

6 Design Flow..........................................................................................................................................................7

7 PSD5XX Family....................................................................................................................................................8

8 Table 2. PSD5XX Pin Descriptions......................................................................................................................9

9 The PSD5XX Architecture ..................................................................................................................................11

9.1 The ZPLD Block..........................................................................................................................................11

9.1.1 The DPLD.........................................................................................................................................14

9.1.2 The GPLD.........................................................................................................................................14

9.1.2.1 Por A Macrocell Structure..................................................................................................16

9.1.2.2 Port B Macrocell Structure.................................................................................................20

9.1.2.3 Port E Macrocell Structure.................................................................................................23

9.1.3 The PPLD.........................................................................................................................................26

9.1.4 The ZPLD Power Management........................................................................................................26

9.2 Bus Interface...............................................................................................................................................29

9.2.1 Bus Interface Configuration..............................................................................................................29

9.2.2 PSD5XX Interface to a Multiplexed Bus...........................................................................................29

9.2.3 PSD5XX Interface to Non-Multiplexed Bus......................................................................................30

9.2.4 Data Byte Enable..............................................................................................................................30

9.2.5 Optional Features.............................................................................................................................34

9.2.6 Bus Interface Examples....................................................................................................................34

9.3 I/O Ports......................................................................................................................................................39

9.3.1 Standard MCU I/O............................................................................................................................39

9.3.2 PLD I/O ...........................................................................................................................................39

9.3.3 Address Out......................................................................................................................................40

9.3.4 Address In........................................................................................................................................40

9.3.5 Data Port..........................................................................................................................................40

9.3.6 Special Function Out........................................................................................................................40

9.3.7 Alternate Function In........................................................................................................................41

9.3.8 Peripheral I/O...................................................................................................................................41

9.3.9 Open Drain Outputs..........................................................................................................................41

9.3.10 Port Registers...................................................................................................................................42

9.3.11 Port A – Functionality and Structure.................................................................................................45

9.3.12 Port B – Functionality and Structure.................................................................................................45

9.3.13 Port C and Port D – Functionality and Structure ..............................................................................48

9.3.14 Port E – Functionality and Structure.................................................................................................48

9.4 Memory Block.............................................................................................................................................52

9.4.1 EPROM............................................................................................................................................52

9.4.2 SRAM...............................................................................................................................................52

9.4.3 Memory Select Map..........................................................................................................................52

9.4.4 Memory Select Map for 8031 Application.........................................................................................54

9.4.5 Peripheral I/O...................................................................................................................................56

PSD5XX Family

PSD5XX/ZPSD5XX

Field-Programmable Microcontroller Peripherals

Table of Contents

(cont.)

9.5 Power Management Unit ............................................................................................................................58

9.5.1 Standby Mode..................................................................................................................................58

9.5.2 Power Down.....................................................................................................................................58

9.5.3 Sleep Mode......................................................................................................................................58

9.5.4 Other Power Saving Options............................................................................................................61

9.6 PSD5XX Counter/Timer..............................................................................................................................63

9.6.1 Counter/Timer Operation..................................................................................................................66

9.6.2 Counter/Timer Registers..................................................................................................................81

9.7 Interrupt Controller ......................................................................................................................................95

9.7.1 Interrupt Operation...........................................................................................................................95

9.7.2 Input/Output....................................................................................................................................100

9.7.3 PPLD Macrocell..............................................................................................................................100

9.7.4 Interrupt Flowchart..........................................................................................................................100

10.0 Page Register...................................................................................................................................................103

11.0 Security Protection............................................................................................................................................103

12.0 System Configuration .......................................................................................................................................104

12.1 Reset Input ............................................................................................................................................108

12.2 ZPLD and Memory During Reset...........................................................................................................108

12.3 Register Values During and After Reset................................................................................................108

12.4 ZPLD Macrocell Initialization .................................................................................................................108

13.0 Specifications....................................................................................................................................................109

13.1 Absolute Maximum Ratings...................................................................................................................109

13.2 Operating Range ...................................................................................................................................109

13.3 Recommended Operating Conditions....................................................................................................109

13.4 AC/DC Parameters................................................................................................................................110

13.5 Example of PSD5XX Typical Power Calculation at VCC= 5.0 V...........................................................111

13.6 DC Characteristics (5 V ± 10% versions) ..............................................................................................112

13.7 AC/DC Parameters – ZPLD Timing Parameters ...................................................................................113

13.8 Microcontroller Interface – AC/DC Parameters .....................................................................................115

13.9 DC Characteristics (ZPSD5XXV Versions) (3.0 V ± 10% versions)......................................................120

13.10 AC/DC Parameters – ZPLD Timing Parameters (3.0 V ± 10% versions)..............................................121

13.11 Microcontroller Interface – AC/DC Parameters (3.0 V± 10% versions).................................................121

14.0 Timing Diagrams...............................................................................................................................................128

15.0 Pin Capacitance................................................................................................................................................134

16.0 AC Testing........................................................................................................................................................134

17.0 Erasure and Programming................................................................................................................................134

18.0 PSD5XX Pin Assignments................................................................................................................................135

19.0 Package Information.........................................................................................................................................137

20.0 PSD5XX Product Ordering Information............................................................................................................142

20.1 PSD5XX Family – Selector Guide.........................................................................................................142

20.2 Part Number Construction.....................................................................................................................143

20.3 Ordering Information..............................................................................................................................143

21.0 Process Change Notice, October 1, 1998........................................................................................................148

1.0 Introduction

Programmable Peripheral

PSD5XX Family

Field-Programmable Microcontroller Peripherals

The PSD5XX family is a microcontroller peripheral that integrates high-performance and user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The PSD5XX is also loaded with a variety of features, such as Counter/Timers, Interrupt controller, power management, and page logic. The PSD5XX products also provide a powerful microcontroller interface that eliminates the need for external “glue logic”. The no “glue logic” concept provides a user-programmable interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that is easy to use. The part’s integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller.

The PSD5XX provides three Zero-power PLDs (ZPLDs): a Decode PLD (DPLD), a General-purpose PLD (PLD), and a Peripheral PLD (PPLD). The ZPLDs have a total of 61 inputs, 140 product terms, 30 macrocells, and 24 I/O connections. A configuration bit (Turbo) can be set by the MCU, and will automatically place the ZPLDs into standby if no inputs are changing. The ZPLDs are designed to consume minimum power using Zero Power CMOS technology that uses low standby current. Unused product terms are automatically disabled, also reducing power, regardless of the Turbo bit setting.

The main function of the DPLD is to perform address decoding for the internal I/O ports, EPROM, and SRAM. The address decoding can be based on up to 24 bits of address inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports separate program and data spaces (for 8031 compatible MCUs).

The General-purpose PLD (GPLD) can be used to implement various logic defined by the user, such as:

• State machines

• Loadable counters and shift registers

• Inter-processor mailbox

• External control logic (chip selects, output enables, etc.).

The GPLD has access to up to 61 inputs, 118 product terms, 24 macrocells, and 24 I/O pins.

PSD5XX Family

Please refer to the revision block at the end of this document for updated information.

The Peripheral PLD (PPLD) generates outputs to the Counter/Timer unit and the Interrupt Controller. The PPLD outputs to the Counter/Timer enable, disable, or trigger counting or time capture. The PPLD outputs to the Interrupt Controller enables the user to define conditions for interrupt generation.

The Counter/Timer unit provides four 16-bit highly flexible Counter/Timers. Each has five modes of operation: pulse, waveform, event counting, time capture, and watchdog (real-time clock). Each Counter/Timer can be programmed to count up or down. The inputs to the Counter/Timer, which enable/disable counting or trigger an operation, can originate from the PPLD directly or directly from the pins. The maximum operating frequency of each counter is 7.5 MHz. The input clock can be divided (by up to 280) before driving the Counter/Timer unit using the 4 to 280 prescaler.

The Interrupt Controller has eight levels of priority encoding. It accepts four user-defined interrupts and four terminal counts from the Counter/Timer. Each interrupt can be individually masked and configured to be level or edge sensitive. A 3-bit interrupt vector is generated that can be read by the microcontroller. The serviced interrupt will be cleared automatically after the microcontroller has read the interrupt vector.

The PSD5XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be individually configured to provide many functions, including the following:

• MCU I/O

• ZPLD I/O

• Latched address output (for MCUs with multiplexed data bus)

• Special function I/O (Counter/Timer and Interrupts)

• Data bus (for MCUs with non-multiplexed data bus).

The PSD5XX can easily interface with virtually any 8- or 16-bit microcontroller with a multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the ZPLDs, enabling the user to generate signals for external devices. The PSD5XX can generate a reset output based on the RESET input (includes hysteresis).

The PSD5XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four equal-sized blocks. Each block can occupy a different address location, allowing for versatile address mapping. The access time of the EPROM includes the address latching and DPLD decoding.

The PSD5XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a power failure. Therefore, you can place data in the optional SRAM that you want to keep after the power is switched off. Power switch-over to the battery automatically occurs when Vcc drops below Vstby.

A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for microcontrollers with limited address space. The Page Register outputs are connected to the ZPLDs and thus can also be used for external paging schemes.

Introduction

(cont.)

PSD5XX Family

2.0 Key Features

Introduction

(cont.)

The Power Management Unit (PMU) of the PSD5XX enables the user to control the power consumption on selected functional blocks, based on system requirements. For microcontrollers that do not generate a chip select input for the PSD, the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down or Sleep Mode, based on the inactivity of ALE (or AS).

Implementing your design has never been easier than with PSDsoft—WSI’s software development suite. Using PSDsoft, you can do the following:

• Configure your PSD5XX to work with virtually any microcontroller

• Specify what you want implemented in the programmable logic using a design file

• Simulate your design

• Download your design to the part using a programmer.

❏ Single-chip programmable peripheral for microcontroller-based applications ❏ 256K to 1 Mbit of UV EPROM with the following features:

• Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16

• Divided into four equally-sized mappable blocks for optimized address mapping

• As fast as 70 ns access time, which includes address decoding

• Built-in Zero-power technology

❏ 16 Kbits SRAM is configurable as 2K x 8 or 1K x 16. The access time can be

as quick as 70 ns, including address decoding. The contents of the SRAM can be battery-backed by connecting a battery to the Vstby pin. The SRAM was also designed using Zero-power technology

❏ 40 I/O pins (divided into five 8-bit ports) that can be individually configured for:

• Standard MCU I/O

• PLD/macrocell I/O

• Latched address output

• High-order address inputs

• Special function I/O

• Open-drain output

❏ Three Zero-power Programmable Logic Devices (ZPLDs): the Decode PLD (DPLD), the

General-purpose PLD (GPLD), and the Peripheral PLD (PPLD) can be used for:

• Up to 61 input and 140 output product terms

• 24 Macrocells and I/O

• Decode up to 16 MB of address

• State machines and state logic

• Generate external signals (chip selects, bus interface, etc.)

❏ Microcontroller logic that eliminates the need for external “glue logic” has the following

features:

• Ability to interface to multiplexed and non-multiplexed buses

• Built-in address latches for multiplexed address/data bus

• ALE and Reset polarity are programmable

• Multiple configurations are possible for interface to many different microcontrollers

❏ Four 16-bit Counter/Timers that have five modes of operation and can be controlled by

the PPLD macrocells. Modes of operation are: pulse and waveform generation, time capture, event counting, and a watchdog timer (real time clock).

❏ Eight input priority encoded Interrupt Controller. Four interrupts are generated by

the PPLD and are user defined. The other four interrupts are generated by the Counter/Timer’s terminal count flags. Each interrupt can be individually masked and configured as edge or level sensitive.

❏ Page logic is connected to the ZPLDs and expands the MCU address space to up to

16 times

PSD5XX Family

Key Features

(cont.)

❏ Programmable power management allows:

• SRAM, EPROM, and ZPLDs to enter standby mode automatically

• Disabling of the clock input to the ZPLDs

• ZPLDs to enter a special low power mode (Sleep Mode), based on Turbo bit setting

❏ A security bit prevents reading the PSD5XX configuration and the ZPLD contents.

Setting this bit will prevent the device from being copied on a device programmer.

❏ Built-in security enables the user to block read accesses from a device programmer ❏ Package choices include a 68-pin PLCC and CLDCC, and an 80-pin TQFP. ❏ Programmable polarity Reset output (includes hysteresis), based on Reset input ❏ Simple, menu-driven software (PSDsoft) allows configuration and design entry on a PC.

3.0 Notation

Throughout this data sheet, references are made to the PSD5XX. In most cases, these references also cover the ZPSD5XX and ZPSD5XXV products. Exceptions will be noted.

The main difference between the ZPSD5XX and the PSD5XX is the standby current (Isb). The ZPSD5XX devices have been rated for a lower standby current. Also, there is no low-voltage version of the PSD5XX. There is only the low-voltage version of the ZPSD5XX, which has a V suffix.

4.0 ZPSD Background

Portable and battery powered systems have recently become major embedded control application segments. As a result, the demand for electronic components having extremely low power consumption has increased dramatically. Recognizing this need, WSI, Inc. has developed a new Zero-Power technology. ZPSD products virtually eliminate the DC component of power consumption reducing it to standby levels. Eliminating the DC component is the basis for the words “Zero Power”. ZPSD products also minimize the AC power component when the chip is changing states. The result is a programmable microcontroller peripheral family that replaces discrete circuit functions while drawing minimal power.

PSD5XX Family

PROG.

BUS

INTRF

ADIO

PORT

CONTROL

RD, WR

AD0 – AD15

PC0 – PC7

PD0 – PD7

CLKIN

WATCH DOG OUTPUT

INTERRUPT OUTPUT

CLKIN

TERMINAL

COUNTS

PAGE

REG.

ZPLD

INPUT

BUS

GLOBAL

CONFIG.

SECURITY

PROG.

PORT

PROG.

PORT

POWER

MANAGER

UNIT

VSTDBY

PA0 – PA7

PB0 – PB7

PROG.

PORT

PROG.

PORT

PROG.

PORT

PE0 – PE7

ADDRESS/DATA/CONTROL BUS

MACROCELLS2MACROCELLS

8PT

4PT

2PT

PORT A MACROCELLS

PORT B MACROCELLS

PORT E MACROCELLS

27PT

80PT

11PT

CLKIN

FOUR 16-BIT

256K–1M BIT

EPROM

16 K BITS

SRAM

I/O

DECODER

EPROM

SELECT

SRAM

SELECT

PERIPHERAL

SELECTS

MACROCELL FEEDBACK OR PORT INPUT

CSIOP

GENERAL PLD

(GPLD)

PERIPHERAL

PLD (PPLD)

INTERRUPT

CONTROLLER

COUNTER/TIMERS

24 MACROCELLS

DECODE PLD

(DPLD)

Figure 1. PSD5XX Block Diagram

PSD5XX Family

Upon each address or logic input change to the PSD, the device powers up from low power standby for a short time. Then the PSD consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. After the new outputs are stable, the PSD latches them and automatically reverts back to standby mode. The ICCcurrent flowing during standby mode and during DC operation is identical.

The PSD automatically reduces its DC current drain to these low levels and does not require controlling by the CSI (Chip Select) input. Disabling the CSI pin unconditionally forces the PSD to standby mode independent of other input transitions.

The only significant power consumption in the PSD occurs during AC operation. The PSD contains the first architecture to apply Zero-power techniques to memory circuit

blocks as well as logic. Figure 2 compares PSD Zero-power operation to the operation of a discrete solution.

A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and the generation of an address. The PSD detects the address transition and powers up for a short time. The PSD then latches the outputs of the PAD, EPROM and SRAM to the new values. After finishing these operations, the PSD shuts off its internal power, entering standby mode. The time taken for the entire cycle is less than the PSD’s “access time.”

The PSD will stay in standby mode if the inputs do not change between bus cycles. In an alternate system implementation using discrete EPROM, SRAM and other discrete components, the system will consume operating power during the entire bus cycle. This is because the chip select inputs on the memory devices are usually active throughout the entire cycle. The AC power consumption of the PSD may be calculated using the composite frequency of the MCU address and control inputs, as well as any other logic inputs to the ZPLD.

NOTE: The ZPSD5XX parts have been rated for a lower standby current (ISB) than the PSD5XX parts.

5.0 Integrated Power Management

Operation

ALE

DISCRETE EPROM, SRAM & LOGIC

ADDRESS

EPROM

ACCESS

SRAM

ACCESS

EPROM

ACCESS

ZPSD

TIME

Figure 2. ZPSD Power Operation vs. Discrete Implementation

PSD5XX Family

Figure 3. PSDsoft Development Tools

PSDsilos III™

SILOSIII

CHIP SIMULATION

PSD Programmer

PSDpro/MagicPro

CHIP PROGRAMMING

PSD Compiler

(ZPLD FITTING, ADDRESS TRANSLATION)

PSDabel™

ZPLD DESCRIPTION

(STATE MACHINE, DECODING)

PSDsoft

Development Software

PSD Configuration

CHIP CONFIGURATION

THIRD PARTY PROGRAMMERS

CODE FILE

Shown in Figure 3 (below) is the software design flow for a PSD5XX device. PSDsoft—WSI’s software development suite—is used throughout the design phase. You start with a design file that is written in PSDabel-a high-level hardware description language (HDL). Before you compile your design, you must also configure the PSD5XX so it knows what signals to expect from your microprocessor and what pre-runtime options should be set (such as the security bit).

Once you have a design file and have configured the device, you are ready to run the Fitter and Address Translator. The Fitter accepts input from PSDabel and PSD Configuration, synthesizes this user logic and configuration, and fits the design to the PSD silicon. The Address Translator process allows the user to map the MCU firmware from a cross-compiler (in Intel HEX or S-Record format) into the NVM memory blocks within the PSD. As a result, the MCU firmware is merged with the logic and configuration definition of the PSD.

The output of the Address Translator and the Fitter is the required object file that is used by a programmer to program the PSD device. The object file includes chip configuration, the PLD fusemap, and MCU firmware information.

PSDsilosIII is an optional program that provides functional chip-level simulation of the PSD5XX. PSDsoft automatically creates files for input to the simulator. These files convey relevant design information to the simulator. As a result, the user only has to create a stimulus file since all of the signals and node names are taken from the design file.

6.0 Design Flow

PSD5XX Family

7.0 PSD5XX Family

There are 7 unique devices in the PSD5XX family. The part classifications are based on EPROM size and data bus width. The features of each part are listed in Table 1.

Part Bus

DPLD + GPLD + PPLD

I/O Timers Inter. WD*PMU EPROM SRAM

# Bit

Inputs Product Registered

Pins Contr. K bit K bit

Terms Macrocells

501B1 x8/x16 61 140 30 40 4 *16 8 1 *16 Yes 256 16 511B1 x8 61 140 30 40 4

16 8 1 *16 Yes 256 16

502B1 x8/x16 61 140 30 40 4

16 8 1 *16 Yes 512 16

512B0 x8 61 140 30 40 4

16 8 1 *16 Yes 512 –

512B1 x8 61 140 30 40 4

16 8 1 *16 Yes 512 16

503B1 x8/x16 61 140 30 40 4

16 8 1 *16 Yes 1024 16

513B1 x8 61 140 30 40 4

16 8 1 *16 Yes 1024 16

Table 1. PSD5XX Product Matrix

WD = WatchDog Timer. PMU = Power Management Unit.

*One of the four 16-Bit Timers.

PSD5XX Family

8.0 Table 2. PSD5XX Pin Descriptions

Pin Name Pin Function Type Function Descriptions

ADIO0 – ADIO15 Address/ data bus I/O 1. Address/data bus, multiplexed

bus mode

2. Address bus, non-multiplexed bus mode

RD Multiple Names I Multiple functions

1. Read 1. Read signal

2. E 2. E signal (Clock)

3. DS 3. Data strobe signal

4. LDS 4. Low byte data strobe

WR Multiple Names I Multiple functions

1. WR 1. Write signal

2. R/W 2. Read-write signal

3. WRL 3. Low byte write signal

CSI Chip Select Input I Active low, select PSD5XX.

standby mode if high.

RESET Reset Input I Reset I/O ports, ZPLD/macrocells,

Timers and Configuration Registers. Active low.

CLKIN Input clock I Clock input to Timers, ZPLD

macrocells, ZPLD array, and APD counter; connect to ground if clock input not used.

PA0 – PA7 I/O Port A I/O Multiple functions

1. I/O port

2. ZPLD/macrocell I/O port

3. Latched address outputs (PA0–PA7) → (A0–A7)

4. High address inputs (A16 – A23)

5. Timer outputs (PA0 – PA3)

PB0 – PB7 I/O Port B I/O Multiple functions

1. I/O port

2. ZPLD/macrocell I/O port

3. Latched address outputs (PB0–PB7) → (A0–A7) or (A8–A15)

4. Timer outputs (PB0-PB3)

PC0 – PC7 I/O Port C I/O Multiple functions

CMOS 1. I/O port

or 2. ZPLD input port

OD 3. Latched address outputs

(PC0 – PC7) → (A0–A7)

4. Data Port (D0 – D7, non-multiplexed bus)

PD0 – PD7 I/O Port D I/O Multiple functions

CMOS 1. I/O port

or 2. ZPLD input port

OD 3. Latched address outputs

(PD0–PD7) → (A0–A7) or (A8–A15)

4. Data Port (D8-D15, non-multiplexed bus)

The following table describes the pin names and pin functions of the PSD5XX. Pins that have multiple names and/or functions are defined by user configuration.

Pin Name Pin Function Type Function Descriptions

PE0 Port PE, pin 0 I/O Multiple functions

1. BHE 1. High byte enable, 16 bit data

2. PSEN 2. Read program memory, 8031 signal

3. WRH write high data byte

4. UDS 4. Upper Data Strobe

5. SIZ0 5. Byte enable, 68300 signal

6. PE0 6. I/O pin

7. PE0 7. ZPLD I/O pin

8. PE0 8. Latched Address Out – A0

PE1 Port PE, pin 1 I/O Multiple functions

1. ALE 1. Address strobe

2. PE1 2. I/O pin

3. PE1 3. ZPLD I/O pin

4. PE1 4. Latched Address Out – A1

PE2 Port PE, pin 2 Multiple functions

1. Intr Out 1. Interrupt Controller Output

2. PE2 I/O 2. I/O pin

3. PE2 3. ZPLD I/O pin

4. PE2 4. Latched Address Out – A2

PE3 Port PE, pin 3 Multiple functions

1. Timer0-In 1. Timer0 control input

2. PE3 I/O 2. I/O pin

3. PE3 3. ZPLD I/O pin

4. PE3 4. Latched Address Out – A3

PE4 Port PE, pin 4 Multiple functions

1. Timer1-In 1. Timer1 control input

2. PE4 I/O 2. I/O pin

3. PE4 3. ZPLD I/O pin

4. PE4 4. Latched Address Out – A4

5. TC0 5. Timer0 Terminal Count

PE5 Port PE, pin 5 Multiple functions

1. Timer2-In 1. Timer2 control input

2. PE5 I/O 2. I/O pin

3. PE5 3. ZPLD I/O pin

4. PE5 4. Latched Address Out – A5

5. TC1 5. Timer1 Terminal Count

PE6 Port PE, pin 6 Multiple functions

1. Timer3-In 1. Timer3 control input

2. PE6 I/O 2. I/O pin

3. PE6 3. ZPLD I/O pin

4. PE6 4. Latched Address Out – A6

5. TC2 5. Timer2 Terminal Count

PE7 Port PE, pin 7 Multiple functions

1. APD CLK 1. Automatic Power Down Clock Input

2. PE7 I/O 2. I/O pin

3. PE7 3. ZPLD I/O pin

4. PE7 4. Latched Address Out – A7

5. TC3 5. Timer3 Terminal Count

VSTBY VSTBY

SRAM power pin for standby operation (battery backup)

I Chip VCCpower pin

GND GND I Chip ground pin

PSD5XX Family

Table 2. PSD5XX Pin Descriptions

(Cont.)

PSD5XX Family

9.0 The PSD5XX Architecture

PSD5XX consists of seven major functional blocks:

❏

ZPLD Blocks

❏

Bus Interface

❏

I/O Ports

❏

Memory Block

❏

Power Management Unit

❏

Counter/Timer

❏

Interrupt Controller

The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. The chip configurations are specified by the user in the PSDsoft Development Software; some are specified by setting up the appropriate bits in the configuration registers during run time.

9.1 ZPLD Block

Key Features

❏ 3 Embedded ZPLD devices ❏ Maximum 30 macrocells ❏ Combinatorial/registered outputs ❏ Maximum 140 product terms ❏ Programmable output polarity ❏ User configured register clear/preset ❏ User configured register clock input ❏ 61 Inputs ❏ Accessible via 24 I/O pins ❏ Power Saving Mode ❏ UV-Erasable ❏ Generate user defined interrupts to Interrupt Controller

and controls to Counter/Timer

General Description

The ZPLD block has 3 embedded PLD devices:

❏

DPLD

The Address Decoding PLD, generating select signals to internal I/O or memory blocks.

❏

GPLD

The General Purpose PLD provides 24 programmable macrocells for general or complex logic implementation; dedicated to user application.

❏

PPLD

The Peripheral PLD, includes 6 programmable macrocells. The PPLD provides control to the operation of the Counter/Timer and Interrupt Controller.

Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same input bus. The true or complement of the 61 input signals are fed to the programmable AND-ARRAY. Names and source of the input signals are shown in Table 3. The PA, PB, PE signals, depending on user configuration, can either be macrocell feedbacks or inputs from Port A, B or E.

PSD5XX Family

Figure 4. ZPLD Block Diagram

PAGE

REG.

ADIO

PORT

PROG.

PORT

PROG.

PORT

PMU

CSI

RD/E/DS

WR/R_W

RESET

CLKIN

PGR0 – 3

A8 – A15

A0, A1

PC0 – PC7

PD0 – PD7

INTR2PLD

AND

ARRAY

AND

ARRAY

AND

ARRAY

AND

ARRAY

AND

ARRAY

DPLD

ES0 – ES3

RS0

CSIOP

PSEL0 – PSEL1

8 I/O

MACROCELLS

8 I/O

MACROCELLS

8 I/O

MACROCELLS

4 OUTPUT4 OUTPUT

MACROCELLS

2 OUTPUT

MACROCELLS

27 PT

80 PT

11 PT

8 PT

4 PT

2 PT

PT2INT4 – 5

MC2INT6 – 7

MC2TMR0 – 3

PE0 – PE7

PB0 – PB7

PA0 – PA7

PROG.

PORT

PROG.

PORT

PROG.

PORT

TIMERS

INTR.

CTRL

DPLD

GPLD

PPLD

ZPLD INPUT

BUS

(DECODING PLD)

(GENERAL

PURPOSE PLD)

(PERIPHERAL PLD)

WDOG2PLD

The PSD5XX Architecture

PSD5XX Family

Signal Name From

PA0 – PA7 Port A inputs or Macrocell PA feedback PB0 – PB7 Port B inputs or Macrocell PB feedback PE0 – PE7 Port E inputs or Macrocell PE feedback PC0 – PC7 Port C inputs PD0 - PD7 Port D inputs PGR0 – PGR3 Page Mode Register WDOG2PLD Counter/Timer INTR2PLD Interrupt Controller A8 – A15, A0, A1 MCU Address Lines RD/E/DS MCU bus signal WR/R_W MCU bus signal CLKIN Input Clock RESET Reset input CSI CSI input (ORed with power down from PMU)

Table 3. ZPLD Input Signals

The PSD5XX Architecture

(cont.)

PSD5XX Family

9.1.1 The DPLD

The DPLD is used for internal address decoding generating the following eight chip select signals:

❏

ES0 – ES3

EPROM selects, block 0 to block 3

❏

RS0

SRAM block select

❏

CSIOP

I/O Decoder chip select

❏

PSEL0 – PSEL1

Peripheral I/O mode select signals

The I/O Decoder enabled by the CSIOP generates chip selects for on-chip registers or I/O ports based on address inputs A[7:0].

As shown in Figure 5, the DPLD consists of a large programmable AND ARRAY. There are a total of 61 inputs and 8 outputs. Each output consists of a single product term. Although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and Page Register inputs. The select signals, which are active High, are defined by the user in the ABEL file (PSDabel).

The address line inputs to the DPLD include A0, A1 and A8 – A15. If more address lines are needed, the user can bring in the lines through Port A to the DPLD.

9.1.2 The GPLD

The structure of the General Purpose PLD consists of a programmable AND ARRAY and 3 sets of I/O Macrocells. The ARRAY has 61 input signals, same as the DPLD. From these inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells connected to Port A are named PA Macrocells. The 3 sets of macrocells, PA, PB and PE, are similar in structure and function.

Figure 6 shows the output/input path of a GPLD macrocell to the Port pin with which it is associated. If the Port pin is specified as a GPLD output pin in PSDsoft, the MUX in the I/O Port Cell selects the GPLD macrocell as an output of the Port pin. The output enable signal to the buffer in the I/O cell can be controlled by a product term from the AND ARRAY.

If the Port pin is specified as a ZPLD input pin, the MUX in the GPLD macrocell selects the Port input signal to be one of the 61 signals in the ZPLD Input Bus.

The PSD5XX Architecture

PSD5XX Family

Figure 5. DPLD Logic Array

PA0 – PA7

(8)

(4)

(10)

(2)

(3)

(1)

(INPUTS)

PB0 – PB7

PE0 – PE7

PC0 – PC7

PD0 – PD7

PGR0 – PGR3

A8 – A15, A0, A1

WDOG2PLD

INTR2PLD

CSI, CLKIN

RESET

RD/E/DS

WR/R_W

ES0

ES1

ES2

ES3

RS0

CSIOP

PSEL0

PSEL1

4 EPROM

BLOCK

SELECTS

RAM SELECT

I/O DECODER

SELECT

PERIPHERAL

I/O SELECTS

DPLD INPUTS : 61

DPLD OUTPUTS : 8

The PSD5XX Architecture

(cont.)

PSD5XX Family

The PSD5XX Architecture

(cont.)

9.1.2.1 Port A Macrocell Structure

Figure 6a shows the PA Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port A. There are 3 user programmable global product terms output from the GPLD’s AND ARRAY which are shared by all the macrocells in Port A:

❏ PA.OE

Enable or tri-state Port A output pins

❏ PA.PR

Preset D flip flop in the macrocells

❏ PA.RE

Reset/Clear D flip flop in the macrocells

Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable.

The circuit of a Port A Macrocell is shown in Figure 7. There are 6 product terms from the GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as:

❏ Registered Output

Select output from D flip flop

❏ Combinatorial Output

Select output from OR gate

❏ GPLD Input

Use Port A pin as dedicated input

❏ GPLD Output

Use Port A pin as dedicated output

❏ GPLD I/O

Use Port A pin as bidirectional pin

❏ Macrocell Feedback

Register feedback for state machine implementations or expander feedback from the combinatorial output, to expand the number of product terms available to another macrocell.

In case of "Buried Feedback", where the output of the macrocell is not connected to a Port A pin, Port A can be configured to perform other user defined I/O functions.

The two global product terms assigned for asynchronous clear (PA.RE) and preset (PA.PR) are mainly for proper Port A Macrocell initialization. The macrocell flip-flop can also be cleared during reset by MACRO-RST, if such an option is chosen. The clock source is always the input clock CLKIN.

PSD5XX Family

FIGURE 5

AND

ARRAY

POLARITY

SELECT

CONTROL

CLK

SELECT

MUX

PT CLOCK

PT OUTPUT ENABLE (OE)

PT RESET

GPLD MACROCELL I/O PORT CELL

PT CLEAR

CLKIN

MACRO_RST

GLOBAL

CLOCK

PORT

COMB./REG.

SELECT

GPLD

MACROCELL

OUTPUT

INTERNAL

ADDRESS/DATA/CONTROL

BUS

ZPLD

INPUT

BUS

MUX

PCR

DIRECTION

ALE

PDR

PORT INPUT

INPUT

OUTPUT

ADDRESS

A[0-7]

A[8-15]

GPLD

OUTPUT

SPECIAL

FUNCTION

PTs

LATCH

ALE

= LATCH ONLY

ON PORT A

Figure 6. GPLD Macrocell Input/Output Port

The PSD5XX Architecture

(cont.)

AND ARRAY

MC0 PA0

MC1 PA1

MC7 PA7

MACRO. OUT

PA0–INPUT

MACRO. OUT

PA1–INPUT

MACRO. OUT

PA7–INPUT

[

2:0

]

PA0

[

2:0

]

PA1

[

2:0

]

PA7

PA.PR

PA.RE

PA.OE

CLKIN

MACRO–RST

PORT A I/O CELLS

PA MACROCELL

PSD5XX Family

Figure 6a. PA Macrocell Block Diagram

The PSD5XX Architecture

(cont.)

PSD5XX Family

AND

ARRAY

POLARITY

SELECT

PLD–IN

SELECT

MUX

PA.OE

PA.PR

PT0

PT1

PT2

PA.RE

PAi

MACRO–RST

NOTE: i = 7 TO 0

CLKIN

MACRO.OUT

I/O PIN

PAi

PORT A

COMB/REG

SELECT

INTERNAL

ADDRESS/DATA

BUS

PAi–INPUT

ZPLD

BUS

Figure 7. PA Macrocell

The PSD5XX Architecture

(cont.)

PSD5XX Family

9.1.2.2 Port B Macrocell Structure

Figure 8 shows the PB Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin except it is user configurable.

The circuit of a PB Macrocell is shown in Figure 9. There are 10 product terms from the GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output, and configure the macrocell to operate as:

❏ Registered Output

Select output from D flip flop.

❏ Combinatorial Output

Select output from OR gate.

❏ GPLD Input

Use Port B pin as dedicated input.

❏ GPLD Output

Use Port B pin as dedicated output.

❏ GPLD I/O

Use Port B pin as bidirectional pin.

❏ Macrocell Feedback

Register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell.

In case of "Buried Feedback", where the output of the macrocell is not connected to a Port B pin, Port B can be configured to perform other user defined I/O functions.

Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. The signals are defined as follow:

❏ PRESET

Active only if defined by a product term (PBx.PR)

❏ CLEAR

Two selectable inputs: Reset input or user defined product term (PBx.RE)

❏ CLK

Two selectable inputs – CLKIN input or user defined product term (PBx.CLK). The macrocell is operated in Synchronous Mode if the clock input is CLKIN, and is in Asynchronous Mode if the clock is a product-term clock defined by the user.

The PSD5XX Architecture

(cont.)

PSD5XX Family

AND ARRAY

MACRO .OUT

PB0 .OE

PB0 – INPUT

MACRO .OUT

PB1 .OE

PB1–INPUT

MACRO .OUT

PB7 .OE

PB7– INPUT

PTB0 –

[

0 . . 5

]

PB0 .PR

PB0 .RE

PB0 .OE

PB0 .CLK

PB0

PTB1 –

[

0 . . 5

]

PB1 .PR

PB1 .RE

PB1 .OE

PB1 .CLK

PB1

PTB7 –

[

0 . . 5

]

PB7 .PR

PB7 .RE

PB7 .OE

PB7 .CLK

PB7

CLKIN

MACRO – RST

PORT B I/O CELLS

PB MACROCELL

MC0

MC1

MC7

PB0

PB1

PB7

Figure 8. PB Macrocell Block Diagram

The PSD5XX Architecture

(cont.)

PSD5XX Family

PTPTPTPTPTPTPT

AND

ARRAY

POLARITY

SELECT

COMB/REG

SELECT

MUX

PLD–IN

SELECT

MUX

CLK

SELECT

MUX

PBi

PBi .OE

PBi .PR

PT0

PT1

PT2

PT3

PT4

PT5

PBi .CLK

PBi .RE

MACRO–RST

CLKIN

MACRO . OUT

I/O PIN

PBi

PORT B

INTERNAL

ADDRESS/DATA

BUS

PBi– INPUT

NOTE: i = 7 TO 0

ZPLD

BUS

Figure 9. PB Macrocell

The PSD5XX Architecture

(cont.)

PSD5XX Family

The PSD5XX Architecture

(cont.)

9.1.2.3 Port E Macrocell Structure

Figure 10 shows the PE Macrocell block, which consists of 8 identical macrocells. Each macrocell output can be connected to its own I/O pin on Port E. There are 3 user programmable global product terms output from the GPLD’s AND ARRAY which are shared by all the macrocells in Port E:

❏ PE.OE

Enable or tri-state Port PE output pins

❏ PE.PR

Preset D flip flop in the macrocells

❏ PE.RE

Reset/Clear D flip flop in the macrocells

The circuit of a PE Macrocell is shown in Figure 11. There are 4 product terms from the GPLD’s AND ARRAY as input to the macrocell. Users can select the polarity of the output and configure the macrocell to operate as:

❏ Registered Output

Select output from D flip flop

❏ Combinatorial Output

Select output from OR gate

❏ GPLD Input

Use Port E pin as dedicated input

❏ GPLD Output

Use Port E pin as dedicated output

❏ GPLD I/O

Use Port E pin as bidirectional pin

❏ Macrocell Feedback

Register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell.

In case of "Buried Feedback", where the output of the macrocell is not connected to Port E pin, Port E can be configured to perform other user defined I/O functions. If pins PE0 and PE1 are used as bus control signal inputs (ALE, PSEN/BHE), the corresponding macrocells' feedbacks are disabled. The bus control signals are connected to the ZPLD Input Bus.

The two global product terms assigned for asynchronous clear (PE.RE) and preset (PE.PR) are mainly for proper PE Macrocell initialization.

The macrocell flip-flop can also be cleared during reset by MACRO-RST, if such an option is chosen. The clock source is always the input clock CLKIN.

PSD5XX Family

Figure 10. PE Macrocell Block Diagram

AND ARRAY

MC0 PE0

MC1 PE1

MC7 PE 7

MACRO .OUT

PE0 – INPUT

MACRO .OUT

PE1 – INPUT

MACRO .OUT

PE7– INPUT

PE0PTPE1

PE7

PE .PR

PE .RE

PE .OE

CLKIN

MACRO – RST

PORT E I/O CELLS

PE MACROCELL

The PSD5XX Architecture

(cont.)

PSD5XX Family

Figure 11. PE Macrocell

AND

ARRAY

POLARITY

SELECT

PLD–IN

SELECT

MUX

PE .OE

PE .PR

PE .RE

PEi

MACRO–RST

NOTE: i = 7 to 0

CLKIN

MACRO .OUT

I/O PIN

PEi

PORT E

INTERNAL

ADDRESS/DATA

BUS

PEi–INPUT

COMB/REG

SELECT

ZPLD

BUS

The PSD5XX Architecture

(cont.)

PSD5XX Family

9.1.3 The PPLD

The Peripheral Programmable Logic Device (PPLD) provides a powerful mechanism for the user to control the operations of the Counter/Timer and Interrupt Controller. Figure 12 is the PPLD block diagram. There are six Peripheral Macrocells, four are dedicated to the Counter/Timer, and two to the Interrupt Controller.

The outputs from the four Peripheral Macrocells, MC2TMR[3:0], are used as load/store/enable inputs to the Counter/Timer (multiplexed with pin inputs TIMER[3:0]_IN). The remaining two macrocell outputs (MC2INT[6:7]), together with two other product terms (PT2INT4, PT2INT5), can generate up to 4 user defined interrupts to the Interrupt Controller. The watch-dog output of the Timer (WDOG2PLD) and Interrupt Controller (INTR2PLD) are available as inputs to the ZPLD’s AND ARRAY.

The structure of a Peripheral Macrocell is shown in Figure 13. The cell has two product term inputs from the AND ARRAY. The user can select the registered or combinatorial output of the macrocell, as well as the output polarity. The registers are clocked by the CLKIN clock, and are cleared by the RESET input during power up.

9.1.4 The ZPLD Power Management

The ZPLD implements a Zero Power Mode, which provides considerable power savings for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the Power Management Mode Register 0 (PMMR0) has to be turned off.

If none of the 61 inputs to the ZPLD are switching for a time period of 70ns, the ZPLD puts itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume normal operation as soon as one or more of the inputs change state.

Two other features of the ZPLD provide additional power savings:

1. Clock Disable:

Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC power consumption.

2. Product Term Disable:

Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically for further power savings.

The ZPLD power configuration is described in the Power Management Unit section.

The PSD5XX Architecture

(cont.)

PSD5XX Family

Figure 12. PPLD Block Diagram

PORT

MACROCELLS

(4)

MACROCELLS

(2)

COUNTER/

TIMER

INTERRUPT

CONTROLLER

AND ARRAY

TIMER

[

3 : 0

]

–IN

[

3 : 0

]

[

3 : 0

]

MC2TMR

[

3 : 0

]

WDOG2PLD

INTR2PLD

PT2INT4

PT2INT5

MC2INT6

MC2INT7

PT (8)

PT (4 )

MUX

The PSD5XX Architecture

(cont.)

+ 123 hidden pages