SGS Thomson Microelectronics M48Z35AY, M48Z35AV Datasheet

M48Z35AY
M48Z35AV

256 Kbit (32Kb x 8) ZEROP OWER® SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and
BATTERY

■ READ CYCLE TIME EQUALS WRITE CYCLE

TIME

■ BATTERY LOW FLAG (BOK)

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

= Power-fail Deselect Voltage):

(V

PFD

– M48Z35AY: 4.20V ≤ V
– M48Z35AV: 2.7V ≤ V

■ SELF-CONTAINED BATTERY in the CAPHAT

PFD

PFD

≤ 4.50V

≤ 3.0V

DIP PACKAGE

■ PACKAGING INCLUDES a 28-LEAD SOIC and

SNAPHAT

®

TOP

(to be Ordered Separately)

■ SOIC PACKAGE PROVIDES D IREC T

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x8 SRAMs

SNAPHAT (SH)

Battery

28

28

1

SOH28 (MH)

Figure 1. Logic Diagram

V

CC

1

PCDIP28 (PC)

Battery CAPHAT

DESCRIPTION

®

The M48Z35AY/35AV ZEROP OWER

RAM is a
32 Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithi c chip is avail­able in two special packages to provide a highly in­tegrated battery backed-up memory solution.

Table 1. Signal Names

A0-A14 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E
G
W
V
V

CC

SS

Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground

A0-A14

W

15

M48Z35AY
M48Z35AV

E

G

V

SS

8

DQ0-DQ7

AI02781B

1/16April 2000

M48Z35AY, M48Z35AV

Figure 2A. DIP Pin Connections

A14 V

1

A12

2
3

A7

4

A6

5

A5

6

A4

7

A3
A2
A1
A0

DQ0

M48Z35AY
M48Z35AV

8
9
10
11
12
13

DQ2

14

SS

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or a ny other conditions above those indicat ed in the operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin whil e i n th e Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Ambient Operating Temperature Grade 1

Storage Temperature (VCC Off) SNAPHAT

Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V

Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI02782B

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

(1)

Grade 6

SOIC

Figure 2B. SOIC Pin Connections

A14 V
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

1
2
3
4
5
6
7

M48Z35AY
M48Z35AV

8
9
10
11
12

DQ2

SS

13
14

0 to 70

–40 to 85
–40 to 85

–55 to 125

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI02783

CC

W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

°C

°C

2/16

M48Z35AY, M48Z35AV

V

PFD

≤ V

CC

or

SO

(1)

(min)

(2)

E G W DQ0-DQ7 Power

V

IH

V

IL

V

IL

V

IL

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Table 3. Operating Modes

Mode

Deselect
Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.

2. See T able 7 for deta ils .

4.5V to 5.5V

3.0V to 3.6V

V

to V

SO

Figure 3. Block Diagram

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

X X High Z Standby
X

V

IL

V

IH

POWER

V

PFD

V

IL

V

IH

V

IH

32K x 8

SRAM ARRAY

D

IN

D

OUT

High Z Active

Active
Active

A0-A14

DQ0-DQ7

E

W

V

CC

The M48Z35AY/35AV is a non-volatile pin and
function equivalent to any JEDEC standard 32K x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number o f writes
that can be performed. The 28 pin 600mil DIP

CAPHAT™ houses the M48Z35AY/35AV silicon
with a long life lithium button cell in a single pa ck­age.

G

V

SS

AI01619B

The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con­nection to a separate SNAPHAT housing cont ain­ing the battery. The unique design allows the
SNAPHAT battery p acka ge t o b e m ount ed o n t op
of the SOIC package after the c ompletion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPH AT housing
is keyed to prevent reverse insertion.

3/16

M48Z35AY, M48Z35AV

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer
driven.

The SOIC and battery packages are shipped sep­arately in plastic anti-static tubes or in Tape & Reel
form.

For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".

The M48Z35AY/35AV also has its own Power-fail
Detect circuit. The control circuitry constantly mon­itors the single 5V supply for an out of tolerance
condition. When V

is out of tolerance, the circuit

CC

write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ys­tem operation brought on by low V

CC

. As V

CC

falls
below approximately 3V, the control circuitry con­nects the battery which maintains data until valid
power returns.

READ MODE

The M48Z35AY/35AV i s in th e Read M ode when­ever W

(Write Enable) is high, E (Ch ip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 264,144 locat ions in
the static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t

) after the last

AVQV

address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G

access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
(t

GLQV

) or Output Enable Access time

ELQV

).

The state of the eight three-s tate Da ta I/O si gnals
is controlled by E

and G. If the outputs are activat-

Figure 4. AC Testing Load Circuit

DEVICE
UNDER

TEST

CL includes JIG capacitance

ed before t

, the data lines will be driven to an

AVQV

indeterminate state until t
puts are changed while E

645Ω

CL = 100pF or
5pF

. If the Ad dres s In-

AVQV

and G remain active,

1.75V

AI03211

output dat a will rem ain v alid for Outp ut Dat a Hold
time (t

) but will go indeterminate until the next

AXQX

Addr e ss Access.

WRITE MODE

The M48Z35AY/35A V is in the Write Mode when­ever W
enced from the latter occurring falling edge of W
E
of W
throughout the cycle. E
a minimum of t

and E are low. The start of a write is refer-

or

. A write is terminated by the earlier rising edge

or E. The addresses must be held valid

or W must return high for

from Chip Enable or t

EHAX

WHAX

from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid t
prior to the end of write and remain valid for t

DVWH
WHDX

afterward. G should be kept hig h during write cy­cles to avoid bus contention; although, if the output
bus has been activated by a low on E

will disable the outputs t

on W

WLQZ

and G, a low

after W falls.

4/16

M48Z35AY, M48Z35AV

Table 5. Capacitance

(T

= 25 °C)

A

(1, 2)

Symbol Parameter Test Condition Min Max Unit

C

C

IO

Note: 1. Effective capacitan ce measured wi th power su pply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselect ed.

Input Capacitance

IN

(3)

Input / Output Capacitance

V

V

OUT

IN

= 0V

= 0V

10 pF
10 pF

Table 6. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 3.0v to 3.6V)

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I

CC

I

CC1

I

CC2

V

IL

V

IH

V

OL

V

OH

Note: 1. Outputs deselected .

2. Negativ e s p i k e s of –1V allowed for up t o 10 ns once per cycle.

Input Leakage Current

(1)

Output Leakage Current
Supply Current Outputs open 50 mA
Supply Current (Standby) TTL

Supply Current (Standby) CMOS

(2)

Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
Output Low Voltage

Output High Voltage

0V ≤ V

IN

0V ≤ V

OUT

E

= V

E

= VCC – 0.2V

I

= 2.1mA

OL

I

= –1mA

OH

≤ V

≤ V

IH

CC

CC

±1 µA
±5 µA

3mA
3mA

V

+ 0.3

CC

0.4 V

2.4 V

V

Table 7. Power Down/Up Trip Points DC Characteristics

(1)

(TA = 0 to 70 °C or –40 to 85 °C)

Symbol Parameter Min Typ Max Unit

V

PFD

V

PFD

V

SO

V

SO

t

DR

Note: 1. All voltages referenced to VSS.

2. At 25 ° C.

Power-fail Deselect Voltage (M48Z35AY) 4.2 4.35 4.5 V
Power-fail Deselect Voltage (M48Z35AV) 2.7 2.9 3.0 V
Battery Back-up Switchover Voltage (M48Z35AY) 3.0 V

V

Battery Back-up Switchover Voltage (M48Z35AV)

(2)

Expected Data Retention Time 10 YEARS

PFD

– 100mV

V

5/16