INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC P OWER-F AIL CHIP DES ELECT and
WRITE PROTECTION
WRITE PROTECT VOLT AGES
= Power-fail Deselect Voltage):
(V
PFD
– M48Z08: 4.50V ≤ V
– M48Z18: 4.20V ≤ V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28 LEAD SOIC
and SNAPHAT
®
TOP (to be Ordered
Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
PIN and FUNCTION COMPATIBLE with the
DS1225 and JEDEC STANDARD 8K x 8
SRAMs
PFD
PFD
4.75V
≤
4.50V
≤
SNAPHAT (SH)
Battery
28
28
1
SOH28 (MH)
Figure 1. Logic Diagram
M48Z08
M48Z18
1
PCDIP28 (PC)
Battery CAPHAT
DESCRIPTION
The M48Z08/18 ZEROPOWER
®
RAM is an 8K x
V
CC
8 non-volatile static RAM which is pin and functional compatible with the DS1225. The monolithic
chip is available in two special packages to provide
a highly integrated battery backed-up memory so-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indi cat ed in the operati onal
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negat i ve undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes
ModeV
Deselect
WriteV
ReadV
ReadV
DeselectV
Deselect≤ V
Note:
1. X = V
Ambient Operating Temperature–40 to 85 °C
Storage T emper ature (VCC Off)–40 to 85 °C
Lead Solder Temperature for 10 seconds260°C
Input or Output Voltages–0.3 to 7 V
Supply Voltage–0.3 to 7 V
Output Current20mA
Power Dissipation1W
(1)
CC
4.75V to 5.5V
or
4.5V to 5.5V
to V
SO
or VIL; VSO = Battery Back-up Switchover Voltage.
IH
(min)XXXHigh ZCMOS Standby
PFD
SO
EGWDQ0-DQ7Power
V
IH
IL
IL
IL
XXHigh ZStandby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High ZActive
XXXHigh ZBattery Back-up Mode
Active
Active
2/18
Figure 3. Block Diagram
M48Z08, M48Z18
A0-A12
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
CC
DESCRIPTION
(cont’d)
The M48Z08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes t hat
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48Z08/18 silicon with a long life lithium button cell
in a single package.
The 28 pin 330mil SOIC provides s ockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel
form.
POWER
V
PFD
8K x 8
SRAM ARRAY
V
SS
Table 4. AC Measurement Conditions
Input Rise and Fall Times≤ 5ns
Input Pulse Voltages0 to 3V
Input and Output Timing Ref. Voltages1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
CL = 100pF or 30pF
DQ0-DQ7
E
W
G
AI01394
OUT
AI01398
3/18
M48Z08, M48Z18
(1, 2)
T ab le 5. Capacitance
= 25 °C)
(T
A
SymbolParameterT est ConditionMinMaxUnit
C
IN
(3)
C
IO
Notes:
1. Effective capacitance measured with power supply at 5V .
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Input Leakage Current0V ≤ VIN ≤ V
Output Leakage Current0V ≤ V
Supply Current (Standby) TTLE = V
Supply Current (Standby) CMOSE = VCC – 0.2V3mA
OUT
≤ V
IH
CC
CC
Input Low Voltage–0.30.8V
Input High Voltage2.2VCC + 0.3V
Output Low VoltageIOL = 2.1mA0.4V
Output High VoltageIOH = –1mA2.4V
±1µA
±5µA
3mA
T able 7. Power Down/Up Trip Points DC Characteristics
= 0 to 70°C)
(T
A
(1)
SymbolParameterMinTypMaxUnit
V
PFD
V
PFD
V
SO
t
DR
Note:
1. All voltages referenced to V
DESCRIPTION
Power-fail Deselect Voltage (M48Z08)4.54.64.75V
Power-fail Deselect Voltage (M48Z18)4.24.34.5V
Battery Back-up Switchover Voltage3.0V
Expected Data Retention Time11YEARS
.
SS
(cont’d)
When V
is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of data
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
4/18
security in the midst of unpredictable system op-
eration brought on by low V
. As VCC falls below
CC
approximately 3V , the control circuitry connects the
battery which maintains data until valid power re-
turns.
M48Z08, M48Z18
T able 8. Power Down/Up Mode AC Characteristics
= 0 to 70°C)
(T
A
SymbolParameterMinMaxUnit
Notes
t
PD
(1)
t
F
t
FB
t
R
t
RB
t
REC
:1.V
2. V
(2)
V
E or W at VIH before Power Down0µs
V
(max) to V
PFD
V
(min) to VSO VCC Fall Time10µs
PFD
V
(min) to V
PFD
VSO to V
PFD
(min) VCC Fall Time300µs
PFD
(max) VCC Rise Time0µs
PFD
(min) VCC Rise Time1µs
E or W at VIH after Power Up1ms
(max) to V
PFD
passes V
CC
(min) to VSO fall time of less than tFB may cause corruption of RAM data.
PFD
(min) fall time of less than tF may result in deselection/writ e protection not occ urri ng until 200 µs after
PFD
(min).
PFD
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tF
tDR
tFB
INPUTS
OUTPUTS
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep
may perform inadvertent writ e cyc l es after V
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
VALIDVALID
(PER CONTROL INPUT)
rises above V
CC
(min) but before normal system operations begin. Even though a power on
PFD
DON'T CARE
HIGH-Z
E high as VCC rises past V
tR
NOTE
(PER CONTROL INPUT)
PFD
tRECtPDtRB
RECOGNIZEDRECOGNIZED
AI00606
(min ). Some system s
5/18
M48Z08, M48Z18
T ab le 9. Read Mode AC Characteristics
= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
(T
A
SymbolParameter
Notes:
t
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
AVAV
1. C
2. C
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Read Cycle Time100ns
Address Valid to Output Valid100ns
Chip Enable Low to Output Valid100ns
Output Enable Low to Output Valid50ns
Chip Enable Low to Output Transition10ns
Output Enable Low to Output Transition5ns
Chip Enable High to Output Hi-Z50ns
Output Enable High to Output Hi-Z40ns
Address Transition to Output Transition5ns
= 100pF (see Figure 4).
L
= 30pF (see Figure 4).
L
Figure 6. Read Mode AC Waveforms
M48Z08 / M48Z18
-100
MinMax
Unit
Note:
Write Enable (
A0-A12
E
G
DQ0-DQ7
W) = High.
tAVAV
VALID
tAVQVtAXQX
tELQV
tELQX
tGLQX
tGLQV
tGHQZ
VALID
tEHQZ
AI01385
6/18
Loading...
+ 12 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.