SGS Thomson Microelectronics M29W002BT, M29W002BB Datasheet

Low Voltage Single Supply Flash Memory

■ SINGLE 2.7 to 3.6V SU PPL Y VO LT AG E fo r

PROGRAM, ERAS E and READ O PER AT IONS

■ ACCESS TIME: 55ns

■ PROGRAMMING TIME

– 10µs by Byte typical

■ 7 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 4 Main Blocks

■ PROGRAM/ERA SE CON T ROL LER

– Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ER ASE CYCL ES per

BLOCK

■ 20 YEARS DATA RETENTI ON

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code M29W002BT: 40h – Bottom Device Code M29W002BB: C2h

M29W002BT

M29W002BB

2 Mbit (256Kb x8, Boot Block)

PRELIMINARY DATA

TSOP40 (N)

10 x 20mm

Figure 1. Logic Diagram

A0-A17

M29W002BT M29W002BB

DQ0-DQ7

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

AI02955

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M29W002BT, M29W002BB

Figure 2. TSOP Connections

A16 A15 A14 A13 A12 A11

A9 A8

W RP NC RB NC

A6 A5 A4 A3 A2 A1

M29W002BT

M29W002BB

20 21

AI02956

31 30

A17 V

NC NC A10 DQ7 DQ6 DQ5 DQ4 V

NC DQ3 DQ2A7 DQ1 DQ0 G V

E A0

SUMMARY DESCRIPTION

The M29W002B is a 2 M bit (256Kb x8) n on-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W002B is fully backward compatible with the M29W002.

The memory is divided into blocks that can be erased independently so it is pos sible to pres erve valid data while old data is erased. Each block can

Table 1. Signal Names

A0-A17 Address Inputs DQ0-DQ7 Data Inputs/Outputs E G W RP RB V

NC Not Connected Internally

Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Supply Voltage Ground

be protected independently to prev ent accidental Program or Erase commands from modifying the memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase op eration can be de tected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes h ave been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32 Kbyte is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple conne ction to most m icroprocessors, often without additional logic.

The memory is offered in a TSOP40 (10 x 20mm) package and it is supplied with all the bits eras ed

(set to ’1’).

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M29W002BT, M29W002BB

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

BIAS

STG

(2)

Note: 1. Except for the ratin g "Operati ng Temperature Range" , stresses above those listed i n t he Table "Absolute M aximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Mini m um Voltage may undershoot to –2V duri ng transit i on and for less than 20ns duri ng transitio ns.

Table 3. Top Boot Block Addresses M29W002BT

(Kbytes)

6 16 3C000h-3FFFFh 5 8 3A000h-3BFFFh 4 8 38000h-39FFFh 3 32 30000h-37FFFh 2 64 20000h-2FFFFh 1 64 10000h-1FFFFh 0 64 00000h-0FFFFh

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 4 V Supply Voltage –0.6 to 4 V Identification Voltage –0.6 to 13.5 V

Table 4. Bottom Boot Block Addresses M29W002BB

Size

Address Range

6 64 30000h-3FFFFh 5 64 20000h-2FFFFh 4 64 10000h-1FFFFh 3 32 08000h-0FFFFh 2 8 06000h-07FFFh 1 8 04000h-05FFFh 0 16 00000h-03FFFh

Size

(Kbytes)

Address Range

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M29W002BT, M29W002BB

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Sign al Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A17). The Address Inputs select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interf a c e .

Reset/Block Temporary Unprotect (RP

). The Re-

set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V

. After Reset/Block Temporary Unprotect

PLPX

goes High, V

, the memory will be ready for Bus

Read and Bus Write operations after t t

, whichever occurs last. See the Ready/Busy

RHEL

, for at least

PHEL

Output section, Table 15 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP

at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V t

PHPHH

to VID must be slower than

Ready/Busy Output (RB

). The Ready/Busy pin

is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Tabl e 15 and Figure 10, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, V

. Ready/Busy will remain Low during

Read/Reset commands or Hardw are Resets until the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is less than the L ockout Voltage, V

. This prevents Bus Write operations from ac-

LKO

cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

Ground. The VSS Ground is the reference for

CC3

all voltage measurements.

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M29W002BT, M29W002BB

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Wri te, Output Disable, Standby and Automatic Standby. See Table 5, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enabl e o r Write Enable are ignored by t he mem ory and do not a ffect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will output the

value, see Figure 7, Rea d Mode AC Wav eforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing requirements.

Output Disa bl e . The Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V

Standby. When Chip Enable is High, V

, the

memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-

ance state. To reduce the S upply Current to the Standby Supply Current, I be held within V

± 0.2V. For the Standby current

, Chip Enable should

CC2

level see Table 11, DC Characteristics. During program or erase operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protec tion. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Table 5, Bus Operations.

Block Protectio n and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying P rotection and Unp rotection to M29 Series Flash.

Table 5. Bus Operations

Operation E G W Address Inputs

Bus Read Bus Write Output Disable Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

X X X Hi-Z

Data

Inputs/Outp uts

V V V

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others V A0 = VIH, A1 = VIL, A9 = VID,

Others V

or V

20h

40h (M29W002BT)

C2h (M29W002BB)

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M29W002BT, M29W002BB

COMMAND INTERFACE

All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 6, Commands. Refer to Table 6 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be u sed to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10

µs

to abort. During the abort period no valid data can be read from the mem ory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select comma nd is issued the memory remains in Auto Select mode unt il another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufa cturer

Code for STMicroelectronics is 20h. The Device Code can be read using a B us Read

operation with A0 = V address bits may be set to e ither V

and A1 = VIL. The other

or VIH. The

Device Code for the M29W002B T is 40h and the M29W002 BB is C2h.

The Block Protecti on St at us of e ac h bl ock can be read using a Bus Rea d operation with A0 = V A1 = V

, and A13-A17 specifying the add ress of

the block. The other address bits may be set to either V

or VIH. If the addressed block is protected

then 01h is output on the Data Inputs/Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal

state machine and starts the Program/Erase Controller.

If the address falls in a pro tected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any command to abort or pause the operation. Typical program times are given in Table 7. Bus Read operations during the program o peration will output the Status Register on the Data Inputs/Outputs. See the section on the S tatus Register for more details.

After the program operation has completed the memory will return to the Read mode, unle ss an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are requ ired to issue the Unlock Bypass command.

Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Prog ram comma nd can be used to program one address in memory at a time. The command requires two B us Write operations, the final write operation latches the address and data in the internal stat e machine and starts th e Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Re set command, which l eaves the d evice in Unlo ck Bypass Mode. See the Program command for details on the behavior.

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