The M29KW032E LightFlash™ is a 32 M bit (2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. Read op erations can b e performed using a single low voltage (2.7 to 3.6V)
supply. Program an d Er ase operations require an
additional V
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 16 uniform blocks that
can be erased i ndependently so it is poss ible to
preserve valid data whi le old data is erased (see
Figures 2, Block Address es). Program a nd Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Controller (P/E.C.) simplifies the process of programming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
(11.4 to 12.6) power supply. On
PP
The M29KW032E LightFlash™ features a new
command, Multiple Word Program, used to program large streams of dat a. I t gre atly reduc es t he
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 2s, compared to 9s using the standard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple conne ction to most m icroprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and TFBGA48 (6 x 9mm, 0.8mm pitch) packages.
The memory is supplied with all the bits erased
(set to ’1’).
Figure 2. Logic DiagramTable 1. Signal Names
A0-A20Address Inputs
V
V
21
A0-A20DQ0-DQ15
W
E
G
RP
M29KW032E
V
CC
SS
PP
16
RB
AI04370
DQ0-DQ15Data Inputs/Outputs
E
G
W
RP
RB
V
CC
V
PP
V
SS
NCNot Connected Internally
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Supply Voltage read
Supply Voltage program erase
Ground
4/30
Figure 3. TFBGA Connections (Top view through package)
See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs outputs the data stored at the selected address during a Bus Rea d operation. Du ring
Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ8-DQ15). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading t he Status Register
these bits should be ignored.
Chip Enable (E
). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
Output Enable (G
, all other pins are ignored.
IH
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interf a c e .
Reset (RP
). The Reset pin can be used to apply
a Hardware Reset to the memory.
A Hardware Reset is achieved by holding Reset
Low, V
V
IH
Bus Write operations after t
, fo r at least t
IL
. After Reset goes High,
PLPX
, the memory will be ready for B us Read and
PHEL
or t
RHEL
, which ever occurs last. See the Ready/Busy Output section, Table 16 and Figure 13, Reset AC
Characteristics for more details.
Ready/Busy Output (RB
). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode and Auto
Select mode. After a Hardware Reset, Bus Read
and Bus Write operations cannot begin until
M29KW032E
Ready/Busy becomes high-impedance. See Table
16 and Figure 13, Reset AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, V
Read/Reset commands or Hardw are Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Supply Voltage. The VCC Supply Voltage
V
CC
supplies the power for Read operations.
The Command Interface is disabled when the V
Supply Voltage is less than the L ockout Voltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, I
Program Supply Voltage. VPP is both a
V
PP
power supply and Write Protect pin. The two functions are selected by t he voltage range a pplied t o
the pin. The Supply Voltage V
before the Program Supply Voltage V
If V
PP
power supply pin for program and erase operations. V
algorithm is completed.
If V
PP
V
is seen as a Write Protect pin. In this case a
PP
voltage lower than V
tion against program or erase, while V
range of V
12, DC Characteristics for the relevant values).
Note that V
nected as the device may become unreliable.
Vss Ground. The V
for all voltage measurements.
. Ready/Busy will remain Low during
OL
Supply Voltage pin and the VSS Ground
CC
.
CC3
must be applied
CC
PP
.
is in the range 11.4V to 12.6V it acts as a
must be stable until the Program/Erase
PP
is kept in a low voltage range (0V to 3.6V)
gives an absolute p rotec-
HH
enables these functions (see Ta ble
HH
must not be left floating o r uncon-
PP
Ground is the reference
SS
in the
PP
CC
7/30
M29KW032E
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Output Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Operations, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low sig nal, V
and Output Enable and keeping Write Enable
High, V
. The Data Inputs/Outputs will output the
IH
value, see Figure 10, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 14 and 15, Write AC
, to Chip Enable
IL
, during the whole Bus
Characteristics, for details of the timing requirements.
Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V
Standby. When Chip Enable is High, V
.
IH
, the
IH
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the S upply Current to the
Standby Supply Current, I
be held within V
± 0.2V. For the Standby current
CC
, Chip Enable should
CC2
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC3
til the operation completes.
Automatic Standby. If CMOS levels (V
± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Tables 3, Bus Operations.
Table 3. Bus Operations
V
V
XX
PP
HH
X
XX
XX
OperationEGW
V
IL
V
IH
V
IH
XXXXHi-Z
V
IL
V
IL
or V
HH
V
IL
V
IL
V
IH
V
IL
V
IL
Bus Read
Bus Write
Output DisableX
Standby
Read Manufacturer
Code
Read Device Code
Note: 1. X = VIL or VIH.
2. XX = V
3. Not necessary for A uto Select or Read/Res et command s.
4. When re adi ng the Status Register during Program or Eras e operations, V
, V
IL
IH
V
IH
V
IL
V
IH
V
IH
V
IH
Address Inputs
A0-A20
(4)
Cell AddressData Output
(3)
Command AddressData Input
XHi-Z
A0 = V
Others V
A0 = V
Others V
, A1 = VIL,
IL
or V
IL
IH
, A1 = VIL,
IH
or V
IL
IH
must be kept at VHH.
PP
Data Inputs/Outputs
DQ15-DQ0
0020h
88ACh
8/30
COMMAND INTERFACE
All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the commands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be u sed to issue
the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Res et co mmand is executed
regardless of the value of V
(VIL, VIH or VHH).
PP
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. Three
consecutive Bus Write operations are re quired to
issue the Auto Selec t command. Onc e the Auto
Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is
issued, all other commands are ignored. The Auto
Select command is executed regardless of the value of V
(VIL, VIH or VHH).
PP
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
and A1 = VIL. The other address bits
IL
or VIH.
IL
The Device Code can be read using a B us Read
operation with A0 = V
address bits may be set to either V
and A1 = VIL. The other
IH
or VIH.
IL
Word Progr a m Com m a n d.
The Word Program command can be used to program a Word to the memory array. V
set to V
ther V
during Word Program. If VPP is set to ei-
HH
or VIH the command will be ignored, the
IL
must be
PP
data will remain unchanged and the device will revert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the Program/Erase Controller.
During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the program o peration will output
M29KW032E
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a l arge
number of Words are written to the memory at any
one time. V
Word Progr am. If V
command will be ignored, the data will remain unchanged and the device will revert to Read/Reset
mode.
It has four phases: the Setup P hase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and reprogram if necessary and the Exit Phase.
Setup Phase. The M ultiple Word Program command requires three Bus Write operations to initiate the command (refer to Table 5, Multiple Word
Program Command and Figure 5, Multiple Word
Program Flowchart). The Status Register Toggle
bit (DQ6) should be checked to verify that the operation has started and the Multiple Word Program
bit (DQ0) checked to verify that the P/E.C. is ready
for the first Word.
Program Phase. The Program Phase requires
n+1 cycles, where n is the number of Words, to execute the programming phase (refer to Table 5,
Multiple Word Program Command and Figure 5,
Multiple Word Program Flowchart).
Three successive steps are required to issue and
execute the Program Phase of the command.
1. The fourth Bus Write operation of the command
latches the Start Address and the first Word to
be programmed. The Status Register Multiple
Word Program bit (DQ0) should be read to
check that the P/E.C. is ready for the next Word.
2. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address can remain the Start Address, be
incremented or be any address in the same
block, as the device automatically increments
the address with each sucssesive Bus Write
must be set to VHH during Multiple
PP
is set to e ither V
PP
or VIH the
IL
9/30
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