TheM27C256Bisa256 KbitEPROMofferedin the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for microprocessorsystems and is organizedas 32,768 by
8 bits.
The FDIP28W(window ceramicfrit-seal package)
has a transparent lid which allows the user to
expose the chipto ultravioletlight to erase the bit
pattern. A new pattern can then be written to the
deviceby followingthe programmingprocedure.
Forapplicationswhere the content isprogrammed
only one time and erasure is not required, the
M27C256B is offered in PDIP32, PLCC32 and
TSOP28(8 x 13.4mm) packages.
Table1. Signal Names
A0-A14Address Inputs
Q0-Q7Data Outputs
EChip Enable
GOutput Enable
V
PP
Program Supply
PLCC32 (C)
TSOP28 (N)
8 x 13.4mn
Figure1. Logic Diagram
V
15
A0-A14Q0-Q7
E
G
V
CC
M27C256B
V
PP
SS
8
AI00755B
V
CC
V
SS
July 19981/15
Supply Voltage
Ground
M27C256B
Figure2A. DIPPin Connections
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q2
SS
1
2
3
4
5
6
7
M27C256B
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI00756
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure2B. LCC PinConnections
PP
CC
A13
DU
32
DU
V
Q3
A14
Q4
25
Q5
A8
A9
A11
NC
G
A10
E
Q7
Q6
AI00757
V
A7
A12
A6
A5
A4
A3
A2
9
A1
A0
NC
Q0
Q1
Warning: NC = Not Connected, DU = Dont’t Use.
1
M27C256B
17
Q2
SS
V
Figure2C. TSOPPin Connections
G
A11
A13
A14
V
V
A12
A9
A8
CC
PP
A7
A6
A5
A4
A3
22
28
M27C256B
1
78
21
15
14
AI00614B
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
DEVICEOPERATION
The operating modes of the M27C256B are listed
in the Operating Modes. A single power supply is
requiredinthereadmode. AllinputsareTTLlevels
exceptforV
and12V on A9for ElectronicSigna-
PP
ture.
Read Mode
The M27C256Bhas two control functions,both of
which must be logically active in order to obtain
data at the outputs.Chip Enable (E) is the power
control and should be used for device selection.
OutputEnable(G) is theoutputcontrol and should
be used to gate data to the output pins, independent of device selection. Assuming that the
addresses are stable, the address access time
)isequaltothedelayfromE tooutput(t
(t
AVQV
Datais available at the output after delay of t
ELQV
GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at leastt
AVQV-tGLQV
.
StandbyMode
The M27C256B has a standby mode which reducesthe supplycurrentfrom 30mAto 100µA.The
M27C256Bis placed in the standby mode by applyinga CMOShigh signal to the E input.When in
thestandbymode,theoutputs are ina highimpedance state,independentof theG input.
).
2/15
M27C256B
Table2. AbsoluteMaximum Ratings
(1)
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
V
IO
V
CC
V
A9
V
PP
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
2. Minimum DC voltage on Input or Output is –0.5V withpossible undershoot to –2.0V for a period less than 20ns. Maximum DC
3. Depends on range.
Ambient Operating Temperature
TemperatureUnder Bias–50 to 125
Storage Temperature–65 to 150
(2)
Input or Output Voltages(except A9)–2 to 7V
Supply Voltage–2 to 7V
(2)
A9 Voltage–2 to 13.5V
Program SupplyVoltage–2 to 14V
may cause permanent damage to the device. These are stress ratingsonly and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specificationis not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affectdevice reliability. Refer also tothe STMicroelectronics SURE Program and other
relevant quality documents.
voltage on Output is V
+0.5V with possible overshoot to VCC+2V for a period less than20ns.
CC
(3)
–40 to 125
C
°
C
°
C
°
Table3. Operating Modes
ModeEGA9V
ReadV
Output DisableV
ProgramV
VerifyV
Program InhibitV
StandbyV
Electronic SignatureV
Note:X =VIHor VIL,VID= 12V±0.5V
IL
IL
PulseV
IL
IH
IH
IH
IL
PP
V
IL
V
IH
IH
V
IL
V
IH
XVCCData Out
XVCCHi-Z
XVPPData In
XVPPData Out
XVPPHi-Z
XXVCCHi-Z
V
IL
V
ID
V
CC
Q0 - Q7
Codes
Table4. Electronic Signature
IdentifierA0Q7Q6Q5Q4Q3Q2Q1Q0Hex Data
Manufacturer’s CodeV
Device CodeV
IL
IH
Two Line OutputControl
BecauseEPROMsareusuallyusedin largermemory arrays, this product features a 2 line control
functionwhich accommodatesthe use of multiple
memory connection. The two line control function
allows:
a. the lowest possiblememory power dissipation,
b. complete assurancethat output bus contention
00100000 20h
10001101 8Dh
Forthe mostefficientuse of thesetwocontrollines,
E should be decoded and used as the primary
deviceselectingfunction, whileG shouldbe made
a common connection to all devices in the array
and connected to the READ line from the system
controlbus.Thisensuresthat all deselectedmemory devices are in their low power standby mode
and that the outputpins are only active when data
is desired from a particular memorydevice.
will not occur.
3/15
M27C256B
Table5. AC MeasurementConditions
High SpeedStandard
Input Rise and Fall Times
Input Pulse Voltages0 to 3V0.4V to 2.4V
Input and Output Timing Ref. Voltages1.5V0.8V and2V
≤
10ns
≤
20ns
Figure3. AC TestingInput Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table6. Capacitance
SymbolParameterTest ConditionMinMaxUnit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
(1)
(TA=25°C, f =1 MHz)
Input CapacitanceVIN=0V6pF
Output CapacitanceV
2.0V
0.8V
AI01822
Figure4. AC TestingLoad Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for High Speed
CL= 100pFfor Standard
CLincludes JIG capacitance
=0V12pF
OUT
OUT
AI01823B
SystemConsiderations
The power switching characteristics of Advance
CMOS EPROMsrequire careful decoupling of the
devices. The supply current, I
, has three seg-
CC
ments that are of interest to thesystem designer:
the standby current level, the active current level,
and transient current peaks that are produced by
thefalling and risingedgesof E. Themagnitudeof
this transient current peaks is dependent on the
capacitiveandinductiveloadingofthe deviceat the
output.
4/15
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
andVSS. Thisshould bea highfrequencycapacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
betweenV
and VSSforeveryeight devices.The
CC
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitoris to overcome the voltage drop caused
by the inductiveeffects of PCB traces.
M27C256B
Table7. Read Mode DC Characteristics
(1)
(TA=0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC=5V±5% or 5V± 10%;VPP=VCC)
SymbolParameterTest ConditionMinMaxUnit
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
V
IH
V
OL
V
OH
Notes: 1. VCCmust be applied simultaneouslywith or before VPPand removed simultaneously or after VPP.