SANYO VPC-MZ3EX, VPC-MZ3, VPC-MZ3GX, VAR-G6U, VAR-G6EX CIRCUIT DESCRIPTION

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Page 1

1. OUTLINE OF CIRCUIT DESCRIPTION

1-1. CA1 and A PART OF CA2 CIRCUIT

DESCRIPTIONS Around CCD block

1. IC Configuration

CA1 board

IC901 (ICX274AQ) CCD imager

CA2 board

IC901 (H driver, CDS, AGC and A/D converter)

2. IC901 (CA1) (CCD imager)

[Structure]

Interline type CCD image sensor

Image size Diagonal 8.293 mm (1/1.8 type) Pixels in total 1688 (H) x 1248 (V) Recording pixels 1600 (H) x 1200 (V)

OUT

GND

Vertical register

G B

Horizontal register

GND

(Note) : Photo sensor

Fig. 1-1. CCD Block Diagram

G R G R G R G R

SUB

B G B G B G B G

(Note)

Pin No.

Symbol

Vø

Vø3A

Vø3B

Vø3C

Vø2A

Vø2B

Vø2C

Vø1

GND

OUT

Vertical register transfer clock

GND

Signal output

Pin Description

Table 1-1. CCD Pin Description

3. IC904 (V Driver) and IC901 (CA2 board) (H driver)

An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. IC904 are V driver. In addition the XV1-XV4 signals which are output from IC102 are the vertical transfer clocks, and the XSG signal which is output from IC102 is superimposed onto XV2 and XV3 at IC902 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the electronic shutter. A H driver is inside IC901 (CA2 board), and H1A, H1B, H2A, H2B and RG clock are generated at IC901 (CA2 board).

4. IC901 (CA2 board) (CDS, AGC Circuit and A/D Converter)

The video signal which is output from the CCD is input to Pin (29) of IC901 (CA2 board). There are inside the sampling hold block, AGC block and A/D converter block. The setting of sampling phase and AGC amplifier is carried out by serial data at Pin (37) of IC911. The video signal is carried out A/D converter, and is output by 10-bit.

Pin No.

CCDIN

H1-H4

Symbol

øRG

Hø

Hø1B

GND

øSUB

SUB

Hø1A

Hø2A

CDS

HORIZONTAL

DRIVERS

CLAMP

Circuit power

Reset gate clock

Horizontal register transfer clock

GND

Substrate clock

Substrate bias

Protection transistor bias

Horizontal register transfer clock

PxGA

INTERNAL

PRECISION

GENERATOR

2~36 dB

VGA

CLOCKS

TIMING

CORE

SYNC

Pin Description

VRT

VREF

Fig. 1-2. IC901 Block Diagram

VRB

ADC

CLAMP

INTERNAL

REGISTERS

SCK

SDATA

DOUT

CLPOB

CLPDM

PBLK

CLI

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1-2. CA2 CIRCUIT DESCRIPTION

1. Circuit Description 1-1. Scannning converter (Interlace converter)

This circuit uses the function of a 128-Mbit SDRAMs to convert the non-interlaced signal which is output from the CCD into an interlaced signal for the video monitor.

1-2. Camera signal processor

This comprises circuits such as the digial clamp circuit, white balance circuit, γ circuit, color signal generation circuit, matrix circuit and horizontal aperture circuit.

1. Digital clamp circuit

The optical black section of the CCD extracts 16-pixel averaged values from the subsequent data to make the black level of the CCD output data uniform for each line. The 16-pixel averaged value for each line is taken as the sum of the value for the previous line multiplied by the coefficient k and the value for the current line multiplied by the coefficient 1-k.

2. White balance circuit

This circuit controls the white balance by using the AWB judgement value computed by the CPU to control the gain for each R, G and B pixel based on the CCD data which has been read.

3. γ circuit This circuit performs (gamma) correction in order to maintain a linear relationship between the light input to the camera and the light output from the picture screen.

4. Color generation circuit

This circuit converts the CCD data into RGB signals.

5. Matrix circuit

This circuit generates the Y signals, R-Y signals and B-Y signals from the RGB signals.

6. Horizontal aperture circuit

This circuit is used generate the aperture signal.

1-3. SDRAM controller

This circuit outputs address, RAS, CAS and AS data for controlling the SDRAM. It also refreshes the SDRAM.

1-4. PIO

The expansion parallel port can be used for functions such as stroboscope control and LCD driver control.

1-8. Sound buffer

Audio memory

1-9. LCD driver

The 8-bit digital YUV signals which are input to the LCD driver are converted to RGB signals, and the timing signal which is necessary for LCD monitor display and the RGB signals are then supplied to the LCD monitor.

1-10. LCD monitor

This is the image display device which displays the image signals supplied from the LCD driver.

1-11. Memory card control

This reads data from the memory card and stores it in SDRAM, and writes out the image data stored in SDRAM. In addition, error correction is carried out when the data is read.

1-12. MJPEG compression

Still and continuous frame data is converted to JPEG format, and movie images are compressed and expanded in MJPEG format.

2. Outline of Operation

When the shutter opens, the reset signals, ZTEST0, ZTEST1, ZTEST2 signals and the serial signals (“take a picture” commands) from the 8-bit microprocessor are input and record operation starts. When the TG drives the CCD, picture data passes through the A/D and is then input to the ASIC as 10bit data. This data then passes through the DCLP, AWB, shutter and γ circuit, after which it is input to the SDRAM. The AWB, shutter, γ, and AGC value are computed from this data, and two exposures are made to obtain the optimum picture. The data which has already been stored in the SDRAM is read by the CPU and color generation is carried out. Each pixel is interpolated from the surrounding data as being either R, G or B primary color data to produce R, G and B data. At this time, correction of the lens distortion which is a characteristic of wide-angle lenses is carried out. Aperture correction is carried out, and in case of still picture the data is then compressed by the JPEG method and in case of picture it is compressed by MJPEG method and is written to compact flash card. When the data is to be output to an external device, it is read JPEG picture data from the compact flash card and output to PC via the USB.

1-5. SIO (Serial control)

This is the interface for the 4-bit microprocessor.

1-6. USB control

This is comunicated PC with 12 Mbps.

1-7. TG, SG block

This is the timing generation circuit which generates the clocks (vertical transfer clock and electronic shutter clock) which drive the CCD.

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3. LCD Block

During EE, gamma conversion is carried out for the 10-bit RGB data which is input from the A/D conversion block of the CCD to the ASIC in order that the γ revised can be displayed on the video. The YUV of 640 x 480 is then transferred to the SVRAM. The data which has accumulated in the SDRAM is converted to digital YUV signal in conformity to ITUR-601 inside the ASIC by SDRAM control circuit inside the ASIC, the data is sent to the LCD driver IC and displayed the image to LCD panel. If the shutter button is pressed in this condition, the 10-bit data which is output from the A/D conversion block of the CCD is sent to the SDRAM (DMA transfer), and is displayed on the LCD as a freeze-frame image. During playback, the JPEG image data which has accumulated in the compact flash card is converted to YUV signals. In the same way as for EE, the data is then sent to the SDRAM, converted to digital YUV signal in conformity to ITUR-601 inside the ASIC, the data is sent to the LCD driver IC and displayed the image to LCD panel. The LCD driver is converted digital YUV signals to RGB signals from ASIC, and these RGB signals and the control signal which is output by the LCD driver are used to drive the LCD panel. The RGB signals are 1H transposed so that no DC component is present in the LCD element, and the two horizontal shift register clocks drive the horizontal shift registers inside the LCD panel so that the 1H/1V transposed RGB signals are applied to the LCD panel. Because the LCD closes more as the difference in potential between the VCOM (common polar voltage: AC drive) and the R, G and B signals becomes greater, the display becomes darker; if the difference in potential is smaller, the element opens and the LCD become brighter. In addition, the brightness and contrast settings for the LCD can be varied by means of the serial data from the ASIC.

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1-3. PW1 POWER CIRCUIT and LENS DRIVE BLOCK DESCRIPTION

1. Outline

This is the main power circuit, and is comprised of the following blocks. Switching power controller (IC501) Analog and LCD system power output (Q5001, T5001) Digital 1.85 V power output (Q5009, L5008) Digital 3.35 V power output (Q5010, L5009) Digital 3.35 V step-up power output (Q5011, L5010) LED backlight power output (Q5012, L5011) 5 V system power output (Q5015, L5012)

2. Switching Controller

This is the basic circuit which is necessary for controlling the power supply for a PWM-type switching regulator, and is provided with six built-in channels, only CH1 (analog and LCD system power output), CH2 (digital 1.85 V system power output), CH3 (digital 3.35 V system power output), CH4 (digital

3.35 V step-up power output), CH5 (LED back light power output) and CH6 (5 V system power output) are used. Feedback from 15.0 V (A) (CH1), 1.85 V (D) (CH2), 3.35 V (D) (CH3), 4.7 V (L) (CH4), LED backlight output (CH5) and 5 V (CH6) power supply outputs are received, and the PWM duty is varied so that each one is maintained at the correct voltage setting level.

2-1. Short-circuit Protection

If output is short-circuited for the length of time determined by the condenser which is connected to Pin (37) of IC501, all output is turned off. The control signal (P ON) are recontrolled to restore output.

3. Analog and LCD System Power Output

15.0 V (A), -7.5 V (A) and 9.6 V (L) are output. Feedback for the 15.0 V (A) is provided to the switching controller (Pin (40) of IC501) so that PWM control can be carried out.

7. LED Backlight Power Output

A constant current flows to the backlight LEDs. Feedback for the voltage of R5098 is provided to the power controller (Pin (2) of IC501) so that PWM control can be carried out.

8. 5 V System Power Output

5 V is output. Feedback for the 5 V is provided to the swiching controller (Pin (4) of IC501) so that PWM control can be carried out.

9. Lens drive block

9-1. Iris drive

When the drive signals (IRIS_A, IRIS_/A, IRIS_B and IRIS_/ B) which are output from the ASIC, the stepping motor is driven by the driver (IC951), and are then used to drive the iris steps.

9-2. Focus drive

When the drive signals (FRSTB, FCW, FOEB and FCLK) which are output from the ASIC, the focus stepping motor is sinewave driven by the micro-step motor driver (IC953). Detection of the standard focusing positions is carried out by means of the photointerruptor (FOCUS PI) inside the lens block.

9-3. Iris drive

The zoom DC motor drive signals (ZOOM_A and ZOOM_/A) which are output from the ASIC are used to drive by the motor driver (IC951). Detection of the zoom positions is carried out by means of photointerruptor (ZOOM PI) inside the lens block.

9-4. Shutter drive

When the shutter drive signals (SHUT_A and SHUT_/A) which are output from the ASIC, it is driven regular current by the motor driver IC (IC951).

4. Digital 1.85 V Power Output

1.85 V (D) is output. Feedback for the 1.85 V (D) is provided to the switching controller (Pins (43) of IC501) so that PWM control can be carried out.

5. Digital 3.35 V Power Output

3.35 V (D) is output. Feedback for the 3.35 V (D) is provided to the swiching controller (Pin (45) of IC501) so that PWM control can be carried out.

6. Digital 3.35 V Step-up Power Output

4.7 V is output. Feedback for the 4.7 V is provided to the swiching controller (Pin (47) of IC501) so that PWM control can be carried out.

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