SANYO LC75811W, LC75811E Datasheet

Ordering number : EN5915A

N1098RM (OT) No. 5915-1/27

LC75811E, 75811W

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

1/8 to 1/10 Duty Dot Matrix LCD Display Controller/Driver

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

Overview

The LC75811E and LC75811W are 1/8 to 1/10 duty dot
matrix LCD display controller/drivers that supports the
display of characters, numbers, and symbols. In addition to
generating dot matrix LCD drive signals based on data
transferred serially from a microcontroller, the LC75811E
and LC75811W also provide on-chip character display ROM
and RAM to allow display systems to be implemented easily.

Features

• Controls and drives a 5 ×7, 5 × 8, or 5 × 9 dot matrix LCD.

• Supports accessory display segment drive (up to 60
segments)

• Display technique: 1/8 duty 1/4 bias drive (5 × 7 dots)

1/9 duty 1/4 bias drive (5 × 8 dots)
1/10 duty 1/4 bias drive (5 × 9 dots)

• Display digits: 12 digits ×1 line (5 × 7 dots),

11 digits × 1 line (5 × 8 or 5 × 9 dots)

• Display control memory
CGROM: 240 characters (5 × 7, 5 × 8, or 5 × 9 dots)
CGRAM: 16 characters (5 × 7, 5 × 8, or 5 × 9 dots)
ADRAM: 12 × 5 bits
DCRAM: 48 × 8 bits

• Instruction function
Display on/off control
Display shift function

• Provides a backup function based on low power modes.

• Serial data input supports CCB format communication
with the system controller.

• Independent LCD drive block power supply VLCD

• Provides a RES pin for LSI internal initialization

• RC oscillator circuit

Package Dimensions

unit: mm

3174-QFP80E

unit: mm

3220-SQFP80

SANYO: QFP80E

[LC75811E]

SANYO: SQFP80

[LC75811W]

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LC75811E, 75811W

Pin Assignments (Top View)

LC75811E

LC75811W

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LC75811E, 75811W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

V

DD

max V

DD

–0.3 to +7.0 V

V

LCD

max V

LCD

–0.3 to +11.0 V

V

IN

1 CE, CL, DI, RES –0.3 to +7.0 V

Input voltage V

IN

2 OSCI –0.3 to VDD+ 0.3 V

V

IN

3 V

LCD

1, V

LCD

2, V

LCD

3 –0.3 to V

LCD

+ 0.3 V

Output voltage

V

OUT

1 OSCO –0.3 to VDD+ 0.3 V

V

OUT

2 S1 to S60, COM1 to COM10 –0.3 to V

LCD

+ 0.3 V

Output current

I

OUT

1 S1 to S60 300 µA

I

OUT

2 COM1 to COM10 3 mA
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

V

DD

V

DD

2.7 6.0 V

V

LCDVLCD

4.5 10.0 V

V

LCD

1 V

LCD

1 3/4 V

LCD

V

LCD

V

Input voltage V

LCD

2 V

LCD

2 2/4 V

LCD

V

LCD

V

V

LCD

3 V

LCD

3 1/4 V

LCD

V

LCD

V

Input high level voltage

V

IH

1 CE, CL, DI, RES 0.8 V

DD

6.0 V

V

IH

2 OSCI 0.7 V

DD

V

DD

V

Input low level voltage

V

IL

1 CE, CL, DI, RES 0 0.2 V

DD

V

V

IL

2 OSCI 0 0.3 V

DD

V

Recommended external resistance R

OSC

OSCI, OSCO 33 kΩ

Recommended external capacitance C

OSC

OSCI, OSCO 220 pF

Guaranteed oscillation range f

OSC

OSC 150 300 600 kHz

Data setup time t

ds

CL, DI: Figure 2 160 ns

Data hold time t

dh

CL, DI: Figure 2 160 ns

CE wait time t

cp

CE, CL: Figure 2 160 ns

CE setup time t

cs

CE, CL: Figure 2 160 ns

CE hold time t

ch

CE, CL: Figure 2 160 ns
High level clock pulse width tøH CL: Figure 2 160 ns
Low level clock pulse width tøL CL: Figure 2 160 ns
Minimum reset pulse width t

WRES

RES: Figure 3 1 µs

Allowable Operating Ranges at Ta = –40 to 85°C, VSS= 0 V

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Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

H

CE, CL, DI, RES 0.1 V

DD

V

Input high level current I

IH

CE, CL, DI, RES, OSCI: VI= 6.0 V 5.0 µA

Input low level current I

IL

CE, CL, DI, RES, OSCI: VI= 0 V –5.0 µA

V

OH

1 S1 to S60: IO= –20 µA V

LCD

– 0.6 V

Output high level voltage V

OH

2 COM1 to COM10: IO= –100 µA V

LCD

– 0.6 V

V

OH

3 OSCO: IO= –500 µA VDD– 1.0 V

V

OL

1 S1 to S60: IO= 20 µA 0.6 V

Output low level voltage V

OL

2 COM1 to COM10: IO= 100 µA 0.6 V

V

OL

3 OSCO: IO= 500 µA 1.0 V

V

MID

1 S1 to S60: IO±20 µA

2/4 V

LCD

– 0.6 2/4 V

LCD

+ 0.6

V

Output middle level voltage*1 V

MID

2 COM1 to COM10: IO= ±100 µA

3/4 V

LCD

– 0.6 3/4 V

LCD

+ 0.6

V

V

MID

3 COM1 to COM10: IO= ±100 µA

1/4 V

LCD

– 0.6 1/4 V

LCD

+ 0.6

V

Oscillator frequency f

OSC

OSCI, OSCO: R

OSC

= 33 kΩ, C

OSC

= 220 pF 210 300 390 kHz

I

DD

1 VDD: power saving mode 5 µA

Current drain

I

DD

2 VDD: VDD= 6.0 V, output open, f

OSC

= 300 kHz 450 900 µA

I

LCD

1 V

LCD

: power saving mode 5 µA

I

LCD

2 V

LCD

: V

LCD

= 10.0 V, output open, f

OSC

= 300 kHz 200 400 µA

Electrical Characteristics in the Allowable Operating Ranges

Note *1: Excluding the bias voltage generation divider resistor built into the V

LCD

1, V

LCD

2, and V

LCD

3. (See figure 1.)

Excluding these resistors

To the common and segment drivers

Figure 1

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• When CL is stopped at the low level

• When CL is stopped at the high level

Block Diagram

Figure 2

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Pin Functions

Pin

Pin No.

Function Active I/O Handling when unused

LC75811E LC75811W

Segment driver outputs.
The S59/COM10 and S60/COM9 pins can be used as common
driver outputs under the “set display technique” instruction.

OPEN— O

S1 to S58

S59/COM10

S60/COM9

1 to 58

59
60

79, 80

1 to 56

57
58

Common driver outputs. OPEN— OCOM1 to COM8 68 to 61 66 to 59

Oscillator connections. An oscillator circuit is formed by
connecting an external resistor and capacitor at these pins.

GND— IOSCI 76 74

Serial data transfer inputs. These pins are connected to the
microcontroller.

CE: Chip enable
CL: Synchronization clock
DI: Transfer data

GND

H ICE 78 76

ICL 79 77

— IDI 80 78

OPEN— OOSCO 75 73

Reset signal input.

• When RES is low (V

SS

):

• Display off
S1 to S58 = “L” (V

SS

).

S59/COM10 and S60/COM9 = “L” (V

SS

).

COM1 to COM8 = “L” (V

SS

).

• Serial data transfer is disabled.

• The OSCI/OSCO pin oscillator is stopped.

• When RES is high (V

DD

):

• Display on after a “display on/off control” (display on
state setting) instruction is executed.

• Serial data transfers are enabled.

• The OSCI/OSCO pin oscillator operates.

GNDL IRES 77 75

Used for applying the LCD drive 3/4 bias voltage externally. OPEN— I

V

LCD

1

71 69

Used for applying the LCD drive 2/4 bias voltage externally. OPEN— I

V

LCD

2

72 70

Used for applying the LCD drive 1/4 bias voltage externally. OPEN— I

V

LCD

3

73 71

Logic block power supply connection. Provide a voltage of
between 2.7 and 6.0 V.

—— —

V

DD

69 67

LCD driver block power supply connection. Provide a voltage of
between 4.5 and 10.0 V.

—— —

V

LCD

70 68

Power supply connection. Connect to ground. —— —

V

SS

74 72

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Block Functions

• AC (address counter)
AC is a counter that provides the addresses used for DCRAM and ADRAM.
The address is automatically modified internally, and the LCD display state is retained.

• DCRAM (data control RAM)
DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are
converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of
48 × 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address
loaded into AC and the display position on the LCD panel.

• When the DCRAM address loaded into AC is 00H.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
DCRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B

However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below.

Note:*2. The DCRAM addresses are expressed in hexadecimal.

Example: When the DCRAM address is 2EH.

Note:*3. 5 × 7 dots ... 12-digit display 5 × 7 dots

5 × 8 dots ... 12-digit display 4 × 8 dots
5 × 9 dots ... 12-digit display 3 × 9 dots

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
DCRAM address (hexadecimal) 01 02 03 04 05 06 07 08 09 0A 0B 0C

(Left shift)

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
DCRAM address (hexadecimal) 2F 00 01 02 03 04 05 06 07 08 09 0A

DCRAM address DA0 DA1 DA2 DA3 DA4 DA5

(Right shift)

LSB

DA0 DA1 DA2 DA3 DA4 DA5

0 1 1 1 0 1

MSB

Least significant bit Most significant bit

HexadecimalHexadecimal

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• ADRAM (Additional data RAM)
ADRAM is RAM used to store the ADATA display data. ADRAM has a capacity of 12 × 5 bits, and the stored display
data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between
the 4-bit ADRAM address loaded into AC and the display position on the LCD panel.

• When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12)

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
ADRAM address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 A B

However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below.

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
ADRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 A B 0

(Left shift)

Display digit 1 2 3 4 5 6 7 8 9 10 11 12
ADRAM address (hexadecimal) B 0 1 2 3 4 5 6 7 8 9 A

(Right shift)

Note: *4. The ADRAM addresses are expressed in hexadecimal.

Example: When the ADRAM address is A

H

Note: *5. 5 × 7 dots ... 12-digit display 5 dots

5 × 8 dots ... 12-digit display 4 dots
5 × 9 dots ... 12-digit display 3 dots

• CGROM (Character generator ROM)
CGROM is ROM used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the 8-bit
character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the character
pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to
the DCRAM address loaded into AC.

• CGRAM (Character generator RAM)
CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8,
or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits.

ADRAM address RA0 RA1 RA2 RA3

LSB

RA0 RA1 RA2 RA3

0 1 0 1

MSB

Least significant bit Most significant bit

Hexadecimal

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Reset Function

The LC75811E and LC75811W are reset when a low level is applied to the RES pin at power on and, in normal mode.
On a reset the LC75811E and LC75811W create a display with all LCD panels turned off. However, after a reset
applications must set the contents of DCRAM, ADRAM, and CGRAM before turning on display with a “display on/off
control” instruction since the contents of these memories are undefined. That is, applications must execute the following
instructions.

• Set display technique

• DCRAM data write

• ADRAM data write (If ADRAM is used.)

• CGRAM data write (If CGRAM is used.)

• Set AC address

After executing the above instructions, applications must turn on the display with a “display on/off control” instruction.
Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off
control” instruction. (See the detailed instruction descriptions.)

Serial Data Transfer Format

• When CL is stopped at the low level

Instruction data

Up to 64 bits

• When CL is stopped at the high level

• CCB address: 47H

• D0 to D63: Instruction data

The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When
transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set
of instruction data until the next instruction data transfer is significantly longer than the instruction execution time.

CCB address

8 bits

CCB address

8 bits

Instruction data

Up to 64 bits