Sanyo LC72720Y Specifications

Ordering number : ENN6488

CMOS IC

LC72720Y, 72720YV

Single-Chip RDS

Signal-Processing System IC

Overview

The LC72720Y and LC72720YV are single-chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique.

Functions

•Band-pass filter: Switched capacitor filter (SCF)

•Demodulator: RDS data clock regeneration and demodulated data reliability information

•Synchronization: Block synchronization detection (with variable backward and forward protection conditions)

•Error correction: Soft-decision/hard-decision error correction

•Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory

•Data I/O: CCB interface (power on reset)

Features

•Error correction capability improved by soft-decision error correction.

•The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM.

•Two synchronization detection circuits provide continuous and stable detection of the synchronization timing.

•Data can be read out starting with the backwardprotection block data after a synchronization reset.

•Fully adjustment free.

•Low voltage (supply voltage: 3.0 V min) type.

•Operating power-supply voltage: 3.0 to 3.6 V

•Operating temperature: –40 to +85°C

•Package: DIP24S, SSOP30

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

42800TN (OT) No. 6488-1/14

LC72720Y, 72720YV

Package Dimensions

unit: mm

unit: mm

3067A-DIP24S						3191A-SSOP30
		[LC72720Y]					[LC72720YV]
		21.0				30	16
	24		13
			7.62	6.4	0.25				5.6	7.6
	1		12							0.5
	0.9					1	15		1.5max	0.15
			(3.25)	3.9max				(1.3)
							9.75
(0.71)	1.78	0.48	0.51min	3.3		0.22	0.65	0.1
			0.95					(0.33)
				SANYO: DIP24S					SANYO: SSOP30

Pin Assignment

VREF	1		24	SYR	VREF	1		30	SYR
MPXIN	2		23	CE	MPXIN	2		29	CE
Vdda	3		22	DI	Vdda	3		28	DI
Vssa	4		21	CL	NC	4		27	NC
FLOUT	5		20	DO	Vssa	5		26	CL
CIN	6	LC72720Y	19	RDS-ID	FLOUT	6		25	DO
T1	7		18	SYNC	CIN	7		24	RDS-ID
T2	8		17	T7(CORREC/ARI-ID/BEO)	NC	8	LC72720YV	23	NC
T3(RDCL)	9		16	T6(ERROR/57K/BE1)	T1	9		22	SYNC
T4(RDDA)	10		15	Vssd	T2	10		21	T7(CORREC/ARI-ID/BEO)
									T6(ERROR/57K/BE1)
T5(RSFT)	11		14	Vddd	T3(RDCL)	11		20
XOUT	12		13	XIN	NC	12		19	NC
					T4(RDDA)	13		18	Vssd
		Top view
					T5(RSFT)				Vddd
				A13195		14		17
					XOUT	15		16	XIN

Top view

A13196

Block Diagram

	+3.3V		VREF	FLOUT	CIN				+3.3V
	Vdda				+		CLOCK		Vddd
						PLL
		REFERENCE					RECOVERY
					–	(57kHz)
							(1187.5Hz)
		VOLTAGE
	Vssa								Vssd
					VREF
			57kHz
	MPXIN	ANTIALIASING	BPF	SMOOTHING			DATA
			(SCF)						RDS-ID
		FILTER		FILTER			DECODER
	DO		RAM		ERROR CORRECTION				SYNC
	CL	CCB					SYNC/EC CONTROLLER
			(24 BLOCK DATA)		(SOFT DECISION)				SYR
	DI
	CE
	T1		MEMORY CONTROL		CLK(4.332MHz)
							SYNC	SYNC
	T2	TEST
							DETECT-1	DETECT-2
	T3 to T7				OSC/DIVIDER
					XIN	XOUT
									A13197

No. 6488-2/14

			LC72720Y, 72720YV
Pin Functions
Pin No.		Pin name	Function	I/O	Pin circuit
						Vdda
	1	VREF	Reference voltage output (Vdda/2)	Output
						Vssa
						A13198
						Vdda
	2	MPXIN	Baseband (multiplexed) signal input	Input
						Vssa A13199
5	/ 6	FLOUT	Subcarrier output (filter output)	Output	–
					+		A13200
						Vdda
6	/ 7	CIN	Subcarrier input (comparator input)	Input		+
					Vssa	–
						VREF	A13201
	3	Vdda	Analog system power supply (+3.3 V)	—		—
4	/ 5	Vssa	Analog system ground	—		—
						Vddd
12	/ 15	XOUT	Crystal oscillator output (4.332/8.664 MHz)	Output	XIN
13	/ 16	XIN	Crystal oscillator input (external reference signal input)		XOUT	Vssd
							A13202
7	/ 9	T1	Test input (This pin must always be connected to ground.)	Input		S
8 / 10		T2	Test input (standby control)			Vssd
			0: Normal operation, 1: Standby state (crystal oscillator stopped)				A13203
9 / 11		T3 (RDCL)	Test I/O (RDS clock output)
10	/ 13	T4 (RDDA)	Test I/O (RDS data output)
11	/ 14	T5 (RSFT)	Test I/O (soft-decision control data output)
16	/ 20	T6 (ERROR/57K/BE1)	Test I/O (error status output, regenerated carrier output, error block count	I/O*
			output)		Vssd
							A13204
17	/ 21 T7 (CORREC/ARI-ID/BE0)		Test I/O (Error correction status output, SK detection output, error block count
			output)
18	/ 22	SYNC	Block synchronization detection output
19	/ 24	RDS-ID	RDS detection output	Output
20	/ 25	DO	Data output			Vssd A13205
21	/ 26	CL	Clock input
			Serial data interface (CCB)			S
22	/ 28	DI	Data input	Input
23	/ 29	CE	Chip enable
						Vssd A13206
24	/ 30	SYR	Synchronization and RAM address reset (active high)
14	/ 17	Vddd	Digital system power supply (+3.3 V)	—		—
15	/ 18	Vssd	Digital system ground	—		—
Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
	Pins 4, 8, 12, 19, 23, 27 are NC (NO CONNECT) Pins for the SSOP package version.
						No. 6488-3/14

LC72720Y, 72720YV

Specifications

Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0 V

	Parameter	Symbol	Conditions		Ratings	Unit
	Maximum supply voltage	VDD max	Vddd, Vdda		–0.3 to +7.0	V
		VIN1 max	CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC		–0.3 to +7.0	V
	Maximum input voltage	VIN2 max	XIN		–0.3 to Vddd +0.3	V
		VIN3 max	MPXIN, CIN		–0.3 to Vdda +0.3	V
		VO1 max	DO, SYNC, RDS-ID, T3, T4, T5, T6, T7		–0.3 to +7.0	V
	Maximum output voltage	VO2 max	XOUT		–0.3 to Vddd +0.3	V
		VO3 max	FLOUT		–0.3 to Vdda +0.3	V
		IO1 max	DO, T3, T4, T5, T6, T7		6.0	mA
	Maximum output current	IO2 max	XOUT, FLOUT		3.0	mA
		IO3 max	SYNC, RDS-ID		20.0	mA
	Allowable power dissipation	Pd max	Ta ≤ 85°C	DIP24S:	350	mW
				SSOP30:	150	mW
	Operating temperature	Topr			–40 to +85	°C
	Storage temperature	Tstg			–55 to +125	°C

Allowable Operating Ranges at Ta = –40 to +85°C, Vssd = Vssa = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	Supply voltage	VDD1	Vddd, Vdda	3.0		3.6	V
		VDD2	Vddd: Serial data hold voltage	2.0			V
	Input high-level voltage	VIH	CL, DI, CE, SYR, T1, T2	0.7 Vddd		6.5	V
	Input low-level voltage	VIL	CL, DI, CE, SYR, T1, T2	0		0.3 Vddd	V
	Output voltage	VO	DO, SYNC, RDS-ID, T3, T4, T5, T6, T7			6.5	V
		VIN1	MPXIN : f = 57 ±2 kHz			50	mVrms
	Input amplitude	VIN2	MPXIN : 100% modulation composite	100			mVrms
		VXIN	XIN	400		1500	mVrms
	Guaranteed crystal oscillator frequencies	Xtal	XIN, XOUT : CI ≤ 120 Ω (XS = 0)		4.332		MHz
			XIN, XOUT : CI ≤ 70 Ω (XS = 1)		8.664		MHz
	Crystal oscillator frequency deviation	TXtal	XIN, XOUT : fO = 4.332 MHz, 8.664 MHz			±100	ppm
	Data setup time	tSU	DI, CL	0.75			µs
	Data hold time	tHD	DI, CL	0.75			µs
	Clock low-level time	tCL	CL	0.75			µs
	Clock high-level time	tCH	CL	0.75			µs
	CE wait time	tEL	CE, CL	0.75			µs
	CE setup time	tES	CE, CL	0.75			µs
	CE hold time	tEH	CE, CL	0.75			µs
	CE high-level time	tCE	CE			20	ms
	Data latch change time	tLC				1.15	µs
		tDC	DO, CL: Differs depending on the value of the			0.46	µs
	Data output time		pull-up resistor used.
		tDH	DO, CE: Differs depending on the value of the			0.46	µs
			pull-up resistor used.
	Electrical Characteristics at Ta = –40 to +85°C, Vssd = Vssa = 0 V
	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	Input resistance	Rmpxin	MPXIN–Vssa : f = 57 kHz		23		kΩ
	Internal feedback resistance	Rf	XIN		1.5		MΩ
	Center frequency	fc	FLOUT	56.5	57.0	57.5	kHz
	–3 dB bandwidth	BW – 3 dB	FLOUT	2.5	3.0	3.5	kHz
	Gain	Gain	MPXIN–FLOOUT : f = 57 kHz	28	31	34	dB
		Att1	FLOUT : f = ±7 kHz	30			dB
	Stop band attenuation	Att2	FLOUT : f < 45 kHz, f > 70 kHz	40			dB
		Att3	FLOUT : f < 20 kHz	50			dB

Continued on next page.

No. 6488-4/14

LC72720Y, 72720YV

Continued from preceding page.

Parameter	Symbol		Conditions		Ratings		Unit
				min	typ	max
Group delay deviation	G-Delay	FLOUT: f = 57 ±	1.2 kHz			± 2.0	µs
Reference voltage output	Vref	VREF : Vdda = 3.3 V			1.65		V
Hysteresis	VHIS	CL, DI, CE, SYR, T1, T2			0.1 Vddd		V
Output low-level voltage	VOL1	DO, T3, T4, T5, T6, T7 : I = 2 mA				0.5	V
	VOL2	SYNC, RDS-ID : I = 8 mA				0.5	V
Input high-level current	IIH1	CL, DI, CE, SYR, T1, T2 : VI = Vddd				5.0	µA
	IIH2	XIN : VI = Vddd		0.9		4.0	µA
Input low-level current	IIL1	CL, DI, CE, SYR, T1, T2 : VI = 0 V				5.0	µA
	IIL2	XIN : VI = 0 V		0.9		4.0	µA
Output off leakage current	IOFF	DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :				5.0	µA
		VO = 6.5 V
Current drain	IDD	Vddd + Vdda, Vddd = Vdda = 3.3 V			6		mA

CCB Output Data Format

•Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.

•Any number of 32-bit output data blocks can be output consecutively.

•When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data consecutively.

•If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted. However, if only the last bit is remaining to be read, it will not be possible to reread that whole block.

•The check bits (10 bits) are not output.

•The data valid / invalid decision is made by referencing the error information flag (E0 to E2) but the offset word detection flag (OWD) must not be referred to.

•When the first leading bits are not “1010”, the read in data is invalid, and the read operation is cancelled.

DI

DO

CCB address 6C

B0 B1 B2 B3 A0 A1 A2 A3

0

0

1

1

0

1

1

0

Output data/first bit

Last bit

1 0 1 0

OWD B2 B1 B0

RE RF1 RF0 ARI

SYC E2 E1 E0

D15 D14 D13 D12

D11 D10 D9 D8

D7 D6 D5 D4

D3 D2 D1 D0

(8)

RDS data

(7)

Error information flags

(6)

Synchronization established flag

(5)

ARI (SK) detection flag

(4)

RAM data remaining flags

(3)

Consecutive RAM read out possible flag

(2)

Offset word information flags

(1)

Offset word detection flag

Fixed pattern (1010)

A13207

(1) Offset word detection flag (1 bit): OWD

OWD	Offset word detection
1	Detected
0	Not detected (protection function operating)

No. 6488-5/14