SANYO LC72720, LC72720M Datasheet

CMOS LSI

Ordering number : EN *5602

N2897HA (OT) No. 5602-1/14

Preliminary

LC72720, 72720M

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

Overview

The LC72720 and LC72720M are single-chip system LSIs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These LSIs include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique.

Functions

• Band-pass filter: Switched capacitor filter (SCF)

• Demodulator: RDS data clock regeneration and demodulated data reliability information

• Synchronization: Block synchronization detection (with variable backward and forward protection conditions)

• Error correction: Soft-decision/hard-decision error correction

• Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory

• Data I/O: CCB interface (power on reset)

Features

• Error correction capability improved by soft-decision error correction

• The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM.

• Two synchronization detection circuits provide continuous and stable detection of the synchronization timing.

• Data can be read out starting with the backwardprotection block data after a synchronization reset.

• Fully adjustment free

• Operating power-supply voltage: 4.5 to 5.5 V

• Operating temperature: –40 to +85°C

• Package: DIP24S, MFP24

Package Dimensions

unit: mm

3067-DIP24S

unit: mm

3045B-MFP24

SANYO: DIP24S

[LC72720]

SANYO: MFP24

[LC72720M]

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Single-Chip RDS

Signal-Processing System LSI

Pin Assignment

Block Diagram

No. 5602-2/14

LC72720, 72720M

Pin Functions

No. 5602-3/14

LC72720, 72720M

Pin No. Pin name Function I/O Pin circuit

1 VREF Reference voltage output (Vdda/2) Output

2 MPXIN Baseband (multiplexed) signal input Input

5 FLOUT Subcarrier output (filter output) Output

6 CIN Subcarrier input (comparator input) Input

3 Vdda Analog system power supply (+5 V) — — 4 Vssa Analog system ground — —

12 XOUT Crystal oscillator output (4.332/8.664 MHz) Output

13 XIN Crystal oscillator input (external reference signal input)

7 T1 Test input (This pin must always be connected to ground.) Input

8 T2

Test input (standby control) 0: Normal operation, 1: Standby state (crystal oscillator stopped)

9 T3 (RDCL) Test I/O (RDS clock output) 10 T4 (RDDA) Test I/O (RDS data output) 11 T5 (RSFT) Test I/O (soft-decision control data output)

16 T6 (ERROR/57K/BE1)

Test I/O (error status output, regenerated carrier output, error block count

I/O*

output)

17 T7 (CORREC/ARI-ID/BE0)

Test I/O (Error correction status output, SK detection output, error block count output)

18 SYNC Block synchronization detection output 19 RDS-ID RDS detection output

Output

20 DO Data output 21 CL Clock input 22 DI Data input

Input

23 CE Chip enable 24 SYR Synchronization and RAM address reset (active high) 14 Vddd Digital system power supply (+5 V) — — 15 Vssd Digital system ground — —

Note: * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.

Serial data interface (CCB)

No. 5602-4/14

LC72720, 72720M

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max Vddd, Vdda –0.3 to +7.0 V

1 max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC –0.3 to +7.0 V

Maximum input voltage V

2 max XIN –0.3 to Vddd +0.3 V

3 max MPXIN, CIN –0.3 to Vdda +0.3 V

1 max DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 –0.3 to +7.0 V

Maximum output voltage V

2 max XOUT –0.3 to Vddd +0.3 V

3 max FLOUT –0.3 to Vdda +0.3 V

1 max DO, T3, T4, T5, T6, T7 6.0 mA

Maximum output current I

2 max XOUT, FLOUT 3.0 mA

3 max SYNC, RDS-ID 20.0 mA

Allowable power dissipation Pd max Ta ≤ 85°C

DIP24S: 350 mW

MFP24: 300 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

1 Vddd, Vdda 4.5 5.0 5.5 V

2 Vddd: Serial data hold voltage 2.0 V

Input high-level voltage V

CL, DI, CE, SYR, T1, T2 0.7 Vddd 6.5 V

Input low-level voltage V

CL, DI, CE, SYR, T1, T2 0 0.3 Vddd V

Output voltage V

DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 6.5 V

1 MPXIN : f = 57 ±2 kHz 50 mVrms

Input amplitude V

2 MPXIN : 100% modulation composite 100 mVrms

XIN

XIN 400 1500 mVrms

Guaranteed crystal oscillator frequencies Xtal

XIN, XOUT : CI ≤ 120 Ω (XS = 0) 4.332 MHz XIN, XOUT : CI ≤ 70 Ω (XS = 1) 8.664 MHz

Crystal oscillator frequency deviation TXtal XIN, XOUT : f

= 4.322 MHz, 8.664 MHz ±100 ppm

Data setup time t

DI, CL 0.75 µs

Data hold time t

DI, CL 0.75 µs

Clock low-level time t

CL 0.75 µs

Clock high-level time t

CL 0.75 µs

CE wait time t

CE, CL 0.75 µs

CE setup time t

CE, CL 0.75 µs

CE hold time t

CE, CL 0.75 µs

CE high-level time t

CE 20 ms

Data latch change time t

1.15 µs

DO, CL: Differs depending on the value of the

0.46 µs

Data output time

pull-up resistor used.

DO, CE: Differs depending on the value of the

0.46 µs

pull-up resistor used.

Allowable Operating Ranges at Ta = –40 to +85°C, Vssd = Vssa = 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max Input resistance Rmpxin MPXIN–Vssa : f = 57 kHz 23 kΩ Internal feedback resistance Rf XIN 1.0 MΩ Center frequency fc FLOUT 56.5 57.0 57.5 kHz –3 dB bandwidth BW – 3 dB FLOUT 2.5 3.0 3.5 kHz Gain Gain MPXIN–FLOOUT : f = 57 kHz 28 31 34 dB

Att1 FLOUT : ∆f = ±7 kHz 30 dB

Stop band attenuation Att2 FLOUT : f < 45 kHz, f > 70 kHz 40 dB

Att3 FLOUT : f < 20 kHz 50 dB

Electrical Characteristics at Ta = –40 to +85°C, Vssd = Vssa = 0 V

Continued on next page.

No. 5602-5/14

LC72720, 72720M

Parameter Symbol Conditions

Ratings

Unit

min typ max Reference voltage output Vref VREF : Vdda = 5 V 2.5 V Hysteresis V

HIS

CL, DI, CE, SYR, T1, T2 0.1 Vddd V

Output low-level voltage

1 DO, T3, T4, T5, T6, T7 : I = 2 mA 0.4 V

2 SYNC, RDS-ID : I = 8 mA 0.4 V

Input high-level current

1 CL, DI, CE, SYR, T1, T2 : VI= 6.5 V 5.0 µA

2 XIN : VI= Vddd 2.0 11 µA

Input low-level current

1 CL, DI, CE, SYR, T1, T2 : VI= 0 V 5.0 µA

2 XIN : VI= 0 V 2.0 11 µA

Output off leakage current I

OFF

DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :

5.0 µA

= 6.5 V

Current drain Idd Vddd + Vdda 12 mA

Continued from preceding page.

CCB Output Data Format

• Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.

• Any number of 32-bit output data blocks can be output consecutively.

• When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data consecutively.

• If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted. However, if only the last bit remains to be read, it will not be possible to reread that whole block.

• The check bits (10 bits) are not output.

1. Offset word detection flag (1 bit): OWD

2. Offset word information flag (3 bits): B0 to B2

OWD Offset word detection

1 Detected 0 Not detected (protection function operating)

B B B

Offset word

2 1 0 0 0 0 A 0 0 1 B 0 1 0 C 0 1 1 C’ 1 0 0 D 1 0 1 E 1 1 0 Unused 1 1 1 Unused

CCB address 6C

Output data/first bit

Last bit

(8) RDS data (7) Error information flags (6) Synchronization established flag (5) ARI (SK) detection flag (4) RAM data remaining flag (3) Consecutive RAM read out possible flag (2) Offset word information flag (1) Offset word detection flag Fixed pattern (1010)

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