Sanyo LC72713W Specifications

Ordering number : ENN6870A

Overview

The LC72713W is data demodulator ICs for receiving FM multiplex broadcasts for mobile reception in the DARC format. This IC includes an on-chip bandpass filter for extracting the DARC signal from the FM baseband signal. It also integrates a decoder circuit that performs the VICS data processing on the same chip and can implement a compact, multifunction VICS reception system. The LC72713W is an improved version of the LC72710W that features circuit improvements that allow a single tuner to receive both the VICS data and the dGPS data supported by the earlier device. Note that a contract with VICS Center is required to evaluate this sample IC and to produce end products that support VICS.

Functions

•Adjustment-free 76 kHz SCF bandpass filter

•Built-in VICS decoder

•MSK delay detection system based on a 1T delay.

•Error correction function based on a 2T delay (in the MSK detection stage)

•Digital PLL based clock regeneration function

•Shift-register 1T and 2T delay circuits

•Block and frame synchronization detection circuits

•Functions for setting the number of allowable BIC errors and the number of synchronization protection operations.

•Error correction using (272, 190) codes

•Built-in layer 4 CRC code checking circuit

•On-chip frame memory and memory control circuit for vertical correction

CMOS IC

LC72713W

Mobile FM Multiplex Broadcast IC

with On-Chip VICS Decoder

•7.2 MHz crystal oscillator circuit

•Two power saving modes: STNBY and EC STOP

•Dedicated frame synchronization circuit for simultaneous reception of dGPS and VICS data

•Applications can use either a parallel CPU interface (DMA) or a CCB serial interface.

•Supply voltage: 4.5 to 5.5 V

Package Dimensions

unit: mm

3190-SQFP64

	[LC72713W]
		12.0
		10.0
1.25	0.5	0.18	1.25	0.15
48				33
49				32
1.25

12.0

10.0

0.5

		64		17
	1.25			1.7max
		1	16
				1
			0.5	0.5

SANYO: SQFP64

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

92001TN (OT) No. 6870-1/29

LC72713W

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

	Parameter	Symbol	Conditions	Ratings	Unit
	Maximum supply voltage	VDD		–0.3 to +7.0	V
	Input voltage	VIN(1)	A0/CL, A1/CE, A2/DI, RST, STNBY	–0.3 to +7.0	V
		VIN(2)	Pins other than VIN(1)	–0.3 to VDD + 0.3	V
	Output voltage	VOUT(1)	DO	–0.3 to +7.0	V
		VOUT(2)	Pins other than VOUT(1)	–0.3 to VDD + 0.3	V
	Output current	IOUT(1)	INT, RDY, DREQ, and D0 to D15	0 to 4.0	mA
		IOUT(2)	Pins other than IOUT(1)	0 to 2.0	mA
	Allowable output current (total)	ITTL	Total for all the output pins	20	mA
	Allowable power dissipation	Pdmax	Ta ≤ 85°C	200	mW
	Operating temperature	Topr		–40 to +85	°C
	Storage temperature	Tstg		–55 to +125	°C

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
Supply voltage		VDD		4.5		5.5	V
High-level input voltage		VIH1	A0/CL, A1/CE, A2/DI, RST, STNBY	0.7 VDD		5.5	V
		VIH2	DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2	0.7 VDD		VDD	V
Low-level input voltage		VIL1	Pins for which VIH1 applies	VSS		0.3 VDD	V
		VIL2	Pins for which VIH2 applies	VSS		0.3 VDD	V
Oscillator frequency		FOSC	This IC operates with a frequency precision of ±250 ppm		7.2		MHz
XIN input sensitivity		VXI	With a sine wave input to XIN, capacitor coupling,	400		1500	mVrms
			VDD = +4.5 to +5.5 V
Input amplitude		VMPX	With a 100% modulated composite signal input to	150		500	mVrms
			MPXIN, VDD = +4.5 to +5.5 V
	Clock low-level period	tCL	A0/CL	0.7			µs
	Clock high-level period	tCH	A0/CL	0.7			µs
	Data setup time	tSU	A0/CL, A2/DI	0.7			µs
I/O	Data hold time	tHD	A0/CL, A2/DI	0.7			µs
	CE wait time	tEL	A0/CL, A1/CE	0.7			µs
Serial
	CE setup time	tES	A0/CL, A1/CE	0.7			µs
	CE hold time	tEH	A0/CL, A1/CE	0.7			µs
	Data latch change time	tLC	A1/CE			0.7	µs
	Data output time	tDDO	DO, A0/CL	277		555	ns
	CRC4 change time	tCRC	CRC4, A0/CL			0.7	µs

No. 6870-2/29

LC72713W

Allowable Operating Ranges: Parallel Interface at Ta = –40 to +85°C, VSS = 0 V

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
	Address to RD setup	tSARD	A0/CL, A1/CE, A2/DI, A3, RD	20			ns
	RD to address hold	tHARD	A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250 ns	–20			ns
	RD low-level width	tWRDL1	RD	250			ns
	RD low-level width (when RDY is used)	tWRDL2	RD	100		250	ns
	RD cycle wait	tCYRD	A0/CL, A1/CE, A2/DI, A3, RD	150			ns
	RDY width (Register read)	tWRDY	RDY	60		210	ns
	RD data hold	tRDH	RD, DATn	0			ns
	Address to WR setup	tSAWR	A0/CL, A1/CE, A2/DI, A3, WR	20			ns
	WR to address hold	tHAWR	A0/CL, A1/CE, A2/DI, A3, WR	20			ns
I/O	WR cycle wait	tCYWR	A0/CL, A1/CE, A2/DI, A3, WR	150			ns
	WR low-level width	tWWRL	WR	200			ns
Parallel
	WR data hold	tWDH	WR, DATn	0			ns
	RDY output delay	tDRDY	RD, RDY	0		30	ns
	Corrected output RD width	tWDRD1	RD (BUSWD = L 8 bits)	300			ns
			RD (BUSWD = H 16 bits)	540			ns
	Corrected output RD width	tWDRD2	RD (BUSWD = L 8 bits)	100		300	ns
	(when RDY is used)		RD (BUSWD = H 16 bits)	300		540	ns
	RDY width (corrected output read)	tWDRDY	RDY (BUSWD = L 8 bits)	60		210	ns
			RDY ((BUSWD = H 16 bits)	300		490	ns
	DACK to DREQ delay	tDREQ	DREQ, DACK			260	ns
	DMA cycle wait	tCYDM	RD, DREQ			420	ns
	RD low-level width (DMA)	tWRDM	RD	300			ns

Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.

When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait time) settings for the CPU bus.

If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250 ns (minimum).

Electrical Characteristics at VDD = +4.5 to +5.5 V, within the allowable operating ranges

	Parameter	Symbol	Conditions		Ratings		Unit
				min	typ	max
		VOH1	Io = 2 mA, BCK, FCK, BLOCK, FLOCK,	VDD – 0.4			V
	High-level output voltage		CRC4, CLK16DATA
		VOH2	Io = 4 mA, INT, RDY, DREQ, D0 to D15	VDD – 0.4			V
		VOL1	Io = 2 mA, Pins for which VOH1 applies			0.4	V
	Low-level output voltage	VOL2	Io = 4 mA, Pins for which VOH2 applies			0.4	V
		VOL3	Io = 2 mA, DO, INT			0.4	V
		IIH1	VIN = 5.5 V, A0/CL, A1/CE, A2/DI, RST,			1.0	µA
	High-level input current		STNBY
		IIH2	VIN = VDDD, All input pins other than IIH1			1.0	µA
	Low-level input current	IIL	VIN = VSSD, All input pins			–1.0	µA
	Input resistance	Rmpx	MPXIN – Vssa f = 100 kHz		50		kΩ
	Reference supply voltage output	Vref	Vref, Vdda = 5 V		2.5		V
	Bandpass filter center frequency	Fc	FLOUT		76.0		kHz
	–3 dB bandwidth	Fbw	FLOUT		19.0		kHz
	Group delay	Dgd	FLOUT	–7.5		+7.5	µs
	Gain	Gain	FLOUT – MPXIN f = 76 kHz		20		dB
		ATT1	FLOUT f = 50 kHz	25			dB
	Stop band attenuation	ATT2	FLOUT f = 100 kHz	15			dB
		ATT3	FLOUT f = 30 kHz	50			dB
		ATT4	FLOUT f = 150 kHz	50			dB
	Output off leakage current	IOFF	V0 = VDDD, DO			5.0	µA
	Hysteresis voltage	VHIS	A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,		0.1 VDDD		V
			DACK, IOCNT1, IOCNT2, RST, STNBY
	Internal feedback resistor	Rf	XIN, XOUT		1.0		MΩ
	Current drain	IDD			18	25	mA

No. 6870-3/29

LC72713W

Block Diagram

CLK16

DATA

BLOCK

FLOCK BCK FCK

Vddd

LPF

Vssd

1T delay

Clock

Synchronization

Timing

Error correction:

STNBY

2T delay

regeneration

regeneration

control

layer 2 CRC

RST

7.2MHz

XOUT

LPF

MSK correction

PN decoding

circuit

Data

XIN

Vref

Address

MPXIN

Anti-aliasing

76kHz

VICS processing

filter

BPF

(SCF)

Memory array

Output control (CPU interface) and

Vdda

Vref

layer 4 CRC detection circuit

Vssa

VREF

FLOUT

CIN

CRC4 IOCNT1

IOCNT2

DREQ DACK CS

RD WR

RDY

INT D0 to D15 A0/CL A1/CE

A2/DI

A3 DO

SP

BUSWD

TIN

Pin Assignment

BUSWD

SP

RST

STNBY

CS

A3

A2/DI

A1/CE

A0/CL

RD

WR

NC

DO

Vssd

Vddd

INT

49

32

TIN

D15

NC

D14

Vssa

D13

Vref

D12

MPXIN

D11

Vdda

D10

FLOUT

D9

CIN

LC72713W

D8

NC

D7

TPC1

D6

TPC2

D5

TEST

D4

TOSEL1

D3

TOSEL2

D2

Vssd

D1

XIN

D0

64

1

16

XOUT

Vddd

IOCNT1

IOCNT2

CLK16

DATA

FLOCK

BLOCK

FCK

BCK

CRC4

DREQ

DACK

Vssd

Vddd

RDY

(Top view)

No. 6870-4/29

LC72713W

Pin Functions

Pin No.

Pin

Function

I/O

Pin circuit

3

IOCNT1

Data bus I/O control 1 (SP = low)*1

4

IOCNT2

Data bus I/O control 2 (SP = low)*1

13

DACK

DMA acknowledge (SP = low)*1

38

WR

Write control signal (SP = low)*1

39

RD

Read control signal (SP = low)*1

40

A0/CL

Address input 0 (SP = low) CCB CL input (SP = low)

Input

41

A1/CE

1 (SP = low) CCB CE input (SP = low)

42

A2/DI

2 (SP = low) CCB DI input (SP = low)

43

A3

3 (SP = low)*1

44

CS

Chip select input (SP = L)*1

46

RST

System reset input (negative logic)

45

STNBY

Standby mode (positive logic)

47

SP

SP = low: parallel, SP = high: serial

48

BUSWD

BUSWD = low: 8 bits, BUSWD = high: 16 bits

60

TEST

The test pin must be connected to the digital system ground (VSS).

58

TPC1

Must be connected to the digital system power supply (VDD) or ground

59

TPC2

(VSS) in normal operation.

Input

As above

61

TOSEL1

As above

62

TOSEL2

As above

49

TIN

As above

5

CLK16

Clock regeneration monitor

6

DATA

Demodulated data monitor

9

FCK

Frame start signal output

10

BCK

Block start signal output

7

FLOCK

Outputs a high level during frame synchronization

Output

8

BLOCK

Outputs a high level during block synchronization

11

CRC4

Level 4 CRC detection result output

33

INT

External CPU interrupt request output

12

DREQ

DMA request signal

16

RDY

Read ready signal

Data bus

17 to 24

D0 to D7

The bus width can be set to be either 8 bits or 16 bits by the BUSWD

I/O

pin (pin 48).

For data input, only the lower 8 bits (D0 to D7) are valid. *3

25 to 32

D8 to D15

Data bus (in 16-bit mode)

Output

These pins are held in the output off state when BUSWD is low.

64	XIN	Connections for the system clock crystal oscillator circuit.	I/O
1	XOUT	The XIN pin can also be used as an external clock signal input.
53	MPXIN	Baseband (multiplex) signal input	Input
55	FLOUT	Subcarrier output (76 kHz bandpass filter output)	Output	+
				–

Continued on next page.

No. 6870-5/29

LC72713W

Continued from preceding page.

Pin No.

Pin

Function

I/O

Pin circuit

				+
56	CIN	Subcarrier input (comparator input)	Input	–

Vref

Vdda

52

VREF

Reference voltage output (Vdda/2)

Output

Vssa

36

DO

CCB serial interface data output

Output

37
50	NC	This pin must be left open
57
54	VDDA	Analog system power supply	—
51	VSSA	Analog system ground	—
2, 15, 34	VDDD	Digital system power supply (+4.5 V to +5.5 V)	—
14, 35, 63	VSSD	Digital system ground	—

Notes: 1. This pin must be connected to VDDD or VSSD if the IC is used in serial interface mode (when SP is high).

2.A capacitor of at least 2000 pF must be inserted between VDDD and VSSD.

3.When used in the SP = high mode (as set by the serial interface), the D0 to D7 data bus lines must be connected to either VDDD or VSSD.

Control Registers

This IC includes both registers that can be read and registers that can be written. These registers can be accessed using either the serial interface (CCB) or the parallel interface. The SP pin switches between these interfaces.

The initial values of the write registers are the data loaded into internal registers when a reset signal (RST) is received. These values are recommended values that do not need to be changed during normal operation.

If the parallel interface is used, applications must hold the address fixed at 00H when reading out data to which error correction has been applied. If the CCB interface is used, the application needs only to specify the CCB address (#FB). The address 00H is an invalid address for writing.

The addresses other than those specified below are control addresses particular to the IC. Applications must not specify those addresses.

Address	Register	Function	R/W	Address	Register	Function	R/W
1	BIC	Number of allowable BIC errors	W	1	STAT	Status register	R
2	SYNCB	Block synchronization: error protection count	W	2	BLNO	Block number register	R
3	SYNCF	Frame synchronization: error protection count	W
4	CTL1	Control register 1	W
5	CTL2	Control register 2	W
6	CRC4	Layer 4 CRC register	W

No. 6870-6/29

LC72713W

Number of Allowable BIC Errors

Address	Register	R/W	Initial value	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
01H	BIC	W	22H		Back protection		(LSB)		Forward protection		(LSB)

The synchronization circuit in this IC operates by recognizing a 16-bit BIC code. The number of allowable errors is the number of incorrect bits allowed in those 16 bits. This data sets up separate values for forward protection mode (when synchronized) and for back protection mode (when not synchronized).

The default value is to allow 2 incorrect bits in both forward and back modes. If the block synchronization discrimination output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend setting the back protection mode BIC allowable error count to 1 or 0.

Block Synchronization: Error Protection Count

Address	Register	R/W	Initial value	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
02H	SYNCB	W	17H		Back protection		(LSB)		Forward protection		(LSB)

The synchronization protection count can be set separately for both forward and back protection. The count conditions for the protection counts are as follows.

•Back protection mode (not synchronized: BLOCK = low)

If the timing of the IC internal synchronization free-running counter matches the timing of the received BIC, the protection count is incremented by 1. Contrarily, if the timings of the IC internal counter and the received BIC do not match, the protection counter is cleared to 0. The timing of the count is the timing of the IC internal counter.

•Forward protection mode (synchronized: BLOCK = high)

In reverse to the back protection mode, if the timing of the IC internal free-running counter does not match the detection timing of the received BIC, the protection counter is incremented, and if the timings match, the protection counter is cleared to 0.

Figure 1 shows the states of the protection counter for the cases where the forward and back protection counts are both 3. This IC defines the value of the protection counter to be 1 at the point that a match or a discrepancy occures between the IC internal timing and the timing of the received BIC. For example, when the value of the back protection count is 2, the IC internal timing and the timing of the received BIC will have matched two times consecutively.

If the protection data is set to new values, for example if the protection counts are set to 3 as assumed in figure 1, applications must send values which are 1 less than the intended value; in this case 22H. Similarly, if the value is set to 00H, the protection counts will, by definition, be set to 1 for both the forward and back directions. However, note that the resulting operation will be equivalent to there being no protection circuit. The default values are 8 for the forward protection count and 2 for the back protection count.

If the block synchronization output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend setting the block synchronization back protection count to a value that is more strict than the default value. (That is, we recommend replacing the default value of 2 with a value of 3 or higher.)

	BIC		0	1	0
Received data	1	2	3

Reset

Synchronization counter BIC position

1 2 3

Block

* Assumes that the forward and back protection counts are 3.

Figure 1 Block Synchronization Protection Operation (Forward → Back → Forward)

No. 6870-7/29

LC72713W

Frame Synchronization: Error Protection Count

Address	Register	R/W	Initial value	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
03H	SYNCF	W	17H		Back protection		(LSB)		Forward protection		(LSB)

This IC detects the BIC characteristic inflection points which occur at four places in a single frame, and increments or decrements a protection counter depending on whether or not they match the IC internal frame synchronization timing counter.

As is the case with the block synchronization error protection value, applications must set these to values one less than the desired protection count. The default values are 8 for the frame synchronization forward protection count and 2 for the back protection count.

Control Register 1

Address	Register	R/W	Initial value	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
04H	CTL1	W	00H	CRC4_RST	DO_MOVE	INT_MOVE	SYNC_RST	EC_STOP	VEC_HALT	*	*

*: BIT0 and BIT1 are unused.

•VEC_HALT

0:Vertical correction and the second horizontal correction processing are performed. (default)

1:Vertical correction and the second horizontal correction processing are not performed.

All IC operations related to vertical correction and the second horizontal correction are stopped by setting this flag. Note that in data output, only data to which the first horizontal correction has been applied will be output.

•EC_STOP

0:All functions operate. (default)

1:Only the MSK detection circuit and the synchronization regeneration circuit operate.

This flag stops all operations relating to error correction (including RAM access), data output, and other operations. While all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input circuit, and the layer 4 CRC circuit continue to operate in this mode.

•SYNC_RST

0:(default)

1:Resets just the synchronization regeneration circuit.

Clears the synchronization status and the synchronization protection status in the synchronization circuit block, and sets the circuit to the unsynchronized state. This allows the circuit to quickly pull in to frame synchronization when the frame synchronization is incorrect for the new reception data following tuning, when the radio has been tuned to a new station. While this flag is used for synchronization related sections of the system, it does not initialize the registers that set the number of allowable BIC errors, the block synchronization forward and back protection counts, and the frame synchronization forward and back protection counts. Also note that during a synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).

This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.

•INT_MOVE

0:Data is only output when error correction has completed, layer 2 CRC has completed, and the data was received with the circuit synchronized. (default)

1:All data is output. (Operation is identical to that of the LC72700E.)

In the default state, this IC only outputs data that has been fully error corrected and that was received in both block and frame synchronization. (This also includes the layer 2 CRC check.)

To acquire all data as provided by the LC72700, applications must set both this flag and the VEC_OUT (BIT2) flag in control register 2 as described below.

•DO_MOVE (Valid only when SP is high.)

0:The high state (high impedance) is held at all times other than when data is being output. (default)

1:Operate identically to the LC72700 when changes are linked to the INT signal, i.e. when both INT_MOVE and VEC_OUT are set to 1.

•CRC4_RST

0:(default)

1:Reset the layer 4 CRC detection circuit.

This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.

No. 6870-8/29

LC72713W

Control Register 2

Address	Register	R/W	Initial value	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
05H	CTL2	W	00H	SUBBLK	BLK_RST	DACK	DREQ	RDY	VEC_OUT	DMA_RD	DMA

•DMA (Valid only when SP is low.)

0:Do not use DMA transfer for readout of post-error correction data. (default)

1:Use DMA transfer for readout of post-error correction data.

•DMA_RD (Valid only when SP is low.)

0:Use the RD signal as the DMA transfer read control signal. (default)

1:Use the DACK signal as the DMA transfer read control signal.

•VEC_OUT

0:Do not perform post-horizontal correction output when vertical correction processing is not performed. (default)

1:Output all data, even when vertical correction processing is not performed. (Operation identical to that of the LC72700)

When this flag is set and a frame of data with absolutely no errors is received, data that is completely identical to the corresponding post-horizontal correction data is output with the timing of the output of post-vertical correction data, even if vertical correction is not performed.

This flag must be set to create interface specifications identical to those of the LC72700.

•RDY (Valid only when SP is low.)

0:The RDY output is issued with timing 1. (default)

1:The RDY output is issued with timing 2.

•DREQ (Valid only when SP is low.)

0:Negative logic is used for the polarity of the DREQ signal. (default)

1:Positive logic is used for the polarity of the DREQ signal.

•DACK (Valid only when SP is low.)

0:Negative logic is used for the polarity of the DACK signal. (default)

1:Positive logic is used for the polarity of the DACK signal.

•BLK_RST

0:(default)

1:Resets the block synchronization circuit only.

Sets the block synchronization status to unsynchronized and clears the block synchronization protection counter. However, note that this has no effect on the frame synchronization functions. Also note that during a synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).

This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.

•SUBBLK

0:Normal status. (default)

1:Set to 1 when a substation (for example a dGPS station during VICS reception) is temporarily received.

The SUBBLK and BLK_RST flags are mainly used when receiving and processing VICS data and dGPS data at the same time. (See page 28.)

	RD
	DATn	Valid
		output

RDY

Timing1

RDY

Timing2

RDY Signal Output Timing

No. 6870-9/29