SANYO LC72705E Datasheet

Overview

The LC72705E is a data demodulation IC for receiving
FM multiplex broadcasts for mobile receivers in the
DARC format. This IC includes a decoder circuit that
performs the required VICS processing, and, in
conjunction with a bandpass filter IC (either the
LV3400M or the LV3403M), can form a compact yet
high-functionality VICS reception system. Note that a
contract with VICS Center is required to evaluate this IC
and to produce end products that support VICS.

Applications

• Receivers for DARC format mobile receiver FM
multiplex broadcasts

Functions

• MSK delay detection circuit based on a 1T delay

• Error correction function based on a 2T delay (in the
MSK detector stage)

• Digital PLL based Clock regeneration circuit

• Shift-register type 1T and 2T delay circuits

• Block and frame synchronization detection circuit

• Function for setting the number of allowable BIC errors,
the number of synchronization protection states

• Error correction using (272, 190) codes

• Layer 4 CRC code checking circuit

• On-chip frame memory and memory control circuit for
vertical correction

• 7.2-MHz crystal oscillator circuit

• VICS decoder circuit

Package Dimensions

unit: mm

3148-QFP44MA

CMOS IC

51198RM (OT) No. 5744-1/14

SANYO: QFP44MA

[LC72705E]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

FM Multiplex Receiver IC for VICS Systems

LC72705E

Ordering number : EN5744

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

No. 5744-2/14

LC72705E

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max –0.3 to +7.0 V

Input voltage

V

IN

1 CE, CL, DI, RST, STNBY –0.3 to +7.0 V

V

IN

2 Pins other than VIN1 –0.3 to VDD+ 0.3 V

Output voltage

V

OUT

1 DO –0.3 to +7.0 V

V

OUT

2 Pins other than V

OUT

1 –0.3 to VDD+ 0.3 V

Output current I

OUT

BLOCK, FLOCK, DO 0 to 4.0 mA
Allowable power dissipation Pd max Ta ≤ 85°C 400 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DD

2.7 5.5 V

Input high-level voltage

V

IH

1 CL, CE, DI, RST, STNBY 0.7 V

DD

5.5 V

V

IH

2 MSK 0.7 V

DD

V

DD

V

Input low-level voltage

V

IL

1 Applies to the same pins as VIH1 V

SS

0.3 V

DD

V

V

IL

2 Applies to the same pins as VIH2 V

SS

0.3 V

DD

V

Oscillator frequency F

OSC

This IC operates at frequencies within a

7.2 MHz

±250 ppm precision.
With a capacitance-coupled sine wave input

V

XI

to X

IN

400 1500 mVrms

Input sensitivity

V

DD

= +4.5 V to +5.5 V

With a capacitance-coupled sine wave input

V

XI

to X

IN

400 900 mVrms

V

DD

= +2.7 V to +3.6 V

[Serial I/O*]

Clock low-level time t

CL

CL 0.7 µs

Clock high-level time t

CH

CL 0.7 µs

Data setup time t

SU

CL, DI 0.7 µs

Data hold time t

HD

CL, DI 0.7 µs

CE wait time t

EL

CL, CE 0.7 µs

CE setup time t

ES

CL, CE 0.7 µs

CE hold time t

EH

CL, CE 0.7 µs

Data latch change time t

LC

CE 0.7 µs

Data output time t

DDO

DO, CL 277 555 ns

Layer 4 CRC change time t

CRC

CRC4, CL 0.7 µs

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

OH

1 IO= 1 mA, FILCK VDD– 1.0 V

Output high-level voltage

V

OH

2

I

O

= 2 mA, BLOCK, FLOCK,

V

DD

– 0.4 V

INT, CLK16, DATA

V

OL

1 IO= 1 mA, applies to the same pins as VOH1 1.0 V

Output low-level voltage V

OL

2 IO= 2 mA, applies to the same pins as VOH2 0.4 V

V

OL

3 IO= 2 mA, DO 0.4 V

Input high-level current

I

IH

1 VIN= 5.5 V, CE, CL, DI, RST, STNBY 1.0 µA

I

IH

2 VIN= VDD, input pins other than IIH1 1.0 µA

V

IN

= VSS, MSK, CL, CE, DI, RST,

Input low-level current I

IL

STNBY, TP0 to TP8, TPC1 to 2 –1 µA
TOSEL1 to 2, TEST

Output off leakage current I

OFFVO

= VDD, DO 5 µA

Hysteresis voltage V

HIS

MSK, CL, CE, DI, RST, STNBY 0.1 V

DD

V

Internal feedback resistor R

f

XIN, X

OUT

1.0 MΩ

Current drain I

DD

16 25 mA

Electrical Characteristics (1) at VDD= +4.5 to +5.5 V, in the allowable operating ranges

Note *: See the serial data timing chart.

No. 5744-3/14

LC72705E

Parameter Symbol Conditions

Ratings

Unit

min typ max

V

OH

1 IO= 0.5 mA, FILCK VDD– 1.0 V

Output high-level voltage

V

OH

2

I

O

= 1 mA, BLOCK, FLOCK,

V

DD

– 0.4 V

INT, CLK16, DATA

V

OL

1 IO= 0.5 mA, applies to the same pins as VOH1 1.0 V

Output low-level voltage V

OL

2 IO= 1 mA, applies to the same pins as VOH2 0.4 V

V

OL

3 IO= 1 mA, DO 0.4 V

Input high-level current

I

IH

1 VIN= 5.5 V, CE, CL, DI, RST, STNBY 1.0 µA

I

IH

2 VIN= VDD, input pins other than IIH1 1.0 µA

V

IN

= VSS, MSK, CL, CE, DI, RST,

Input low-level current I

IL

STNBY, TP0 to TP8, TPC1 to 2 –1 µA
TOSEL1 to 2, TEST

Output off leakage current I

OFFVO

= VDD, DO 1 µA

Hysteresis voltage V

HIS

MSK, CL, CE, DI, RST, STNBY 0.1 V

DD

V

Internal feedback resistor Rf X

IN

, X

OUT

2.5 MΩ

Current drain I

DD

8 12 mA

Electrical Characteristics (2) at VDD= +2.7 to +3.6 V, in the allowable operating ranges

Block Diagram

Pin Assignment

MSK signal input

1T delay

2T delay

Clock

regeneration

MSK

correction

Layer 4 CRC

Output control

(CPU interface)

Synchronization

regeneration

Memory array

PN decoding

VICS processing

Timing
control

Error

correction

Layer 2 CRC

Data

Address

No. 5744-4/14

LC72705E

Pin Functions

Pin No. Pin Function I/O Circuit type

7 MSK 76-kHz MSK signal input (from the LV3400M/03M)

Input

Input

26
27
28

CL
CE

DI

CCB serial interface Clock input

Data control input
Data input

32
30
44

RST

STNBY

TEST

System reset input (active low)
Standby mode (active high)
Test (Must be connected to ground during normal operation.)

9
12
13
14
15
16
17
18
19

6

8
20
21

TP0
TP1
TP2
TP3
TP4
TP5
TP6
TP7

TP8
TPC1
TPC2

TOSEL1
TOSEL2

Must be connected to either V

DD

or VSS.

Output

Output

4 FILCK Reference clock output for the LV3400M/03M

1011CLK16

DATA

Clock regeneration monitor
Demodulated data monitor

23
22
24
25

BLOCK
FLOCK

CRC4

INT

Outputs a high level during block synchronization.
Outputs a high level during frame synchronization.
Layer 4 CRCC check result output
External CPU interrupt signal

34
35
36
37
39
41
42
43

IC0
IC1
IC2
IC3
IC4
IC5
IC6
IC7

Internal connections. These pins must be left open.

29 DO Data output used by the CCB serial interface

Input

Output

1
2

XIN

XOUT

System clock generation crystal oscillator element connections

—
—

5, 31, 38

3, 33,40

V

DD

V

SS

Power supply (+2.7 to 5.5 V)
Ground

Data I/O Techniques
CCB Technique

Sanyo audio ICs input and output data using the Sanyo CCB (computer control bus) standard, which is a serial bus
format. This IC uses an 8-bit address CCB and uses the following addresses.

No. 5744-5/14

LC72705E

I/O mode

Address

Function

B0 B1 B2 B3 A0 A1 A2 A3

Input 0 1 0 1 1 1 1 1 16-bit control data input

Output 1 1 0 1 1 1 1 1 Data output for the input clock (CL)

Input 0 0 1 1 1 1 1 1 Data input (in 8-bit units) for the layer 4 CRC check circuit

Data Input Timing

Note: The DO pin is normally left open.

Since the DO pin is an n-channel open drain pin, the time required for the data to change from the low level to the high level depends on the value of
the pull-up resistor.

Data Output Timing

I/O mode datermined

Internal data latching