SANYO LC72137M Datasheet

CMOS IC

Ordering number : EN5743

70398RM(OT) No. 5743-1/23

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PLL Frequency Synthesizer

for Electronic Tuning

LC72137, 72137M

Overview

The LC72137 and LC72137M are PLL frequency
synthesizers for use in radio/cassette players. They allow
high-performance AM/FM tuners to be implemented
easily.

Features

• High-speed programmable frequency divider

— FMIN: 10 to 160 MHz.....Pulse swallower

(divide-by-two prescaler built in)

— AMIN: 2 to 40 MHz.........Pulse swallower

0.5 to 10 MHz......Direct division

• IF counter

IFIN: 0.4 to 12 MHz................For use as an AM/FM IF

counter

• Reference frequency
— Selectable from one of eight frequencies (crystal

oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz

• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit

• Built-in MOS transistor for forming an active low-pass

filter

• I/O ports
— Dedicated output ports: 4
— I/O ports: 2
— Supports clock time base output

• Serial Data I/O
— Supports CCB format communication with the

system controller.

• Operating ranges
— Supply voltage: 2.5 to 3.6 V
— Operating temperature: –20 to +70°C

• Packages

—DIP22S/MFP20

Package Dimensions

unit: mm

3059-DIP22S

SANYO: DIP22S

[LC72137]

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

unit: mm

3036B-MFP20

SANYO: MFP20

[LC72137M]

No. 5743-2/23

LC72137, 72137M

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +7.0 V

V

IN

1 max CE, CL, DI, AIN –0.3 to +7.0 V

Maximum input voltage V

IN

2 max XIN, FMIN, AMIN, IFIN –0.3 to VDD+ 0.3 V

V

IN

3 max IO1, IO2 –0.3 to +15 V

V

O

1 max DO –0.3 to +7.0 V

Maximum output voltage V

O

2 max XOUT, PD –0.3 to VDD+ 0.3 V

V

O

3 max BO1 to BO5, BOF, IO1, IO2, AOUT –0.3 to +15 V

Maximum output current I

O

max BO1 to BO4, IO1, IO2, DO, AOUT 0 to 6.0 mA

Allowable power dissipation Pd max

Ta ≤ 70°C: LC72136N (DIP22S) 350 mW

Ta ≤ 70°C: LC72136NM (MFP20) 180 mW
Operating temperature Topr –20 to +70 °C
Storage temperature Tstg –40 to +125 °C

Ratings

Parameter Symbol Conditions

min typ max

Unit

Supply voltage V

DD

V

DD

2.5 3.6 V

Input high-level voltage

V

IH

1 CE, CL, DI 0.7 V

DD

6.5 V

V

IH

2 IO1, IO2 0.7 V

DD

13 V

Input low-level voltage V

IL

CE, CL, DI, IO1, IO2 0 0.3 V

DD

V

Output voltage

V

O

1 DO 0 6.5 V

V

O

2 BO1 to BO4, IO1, IO2, AOUT 0 13 V

f

IN

1 XIN: VIN1 75 kHz

f

IN

2 FMIN: VIN2 10 160 MHz

Input frequency f

IN

3 AMIN: VIN3, SNS = 1 2 40 MHz

f

IN

4 AMIN: VIN4, SNS = 0 0.5 10 MHz

f

IN

5 IFIN: VIN5 0.4 12 MHz

V

IN

1 XIN: fIN1 200 800 mVrms

V

IN

2-1 FMIN: f = 10 to 130 MHz 20 800 mVrms

V

IN

2-2 FMIN: f = 130 to 160 MHz 40 800 mVrms

Input amplitude V

IN

3 AMIN: fIN3, SNS = 1 40 800 mVrms

V

IN

4 AMIN: fIN4, SNS = 0 40 800 mVrms

V

IN

5-1 IFIN: fIN5, IFS = 1 40 800 mVrms

V

IN

5-2 IFIN: fIN6, IFS = 0 70 800 mVrms

Guaranteed crystal

Xtal XIN, XOUT * 75 kHz

oscillator frequency

Allowable Operating Ranges at Ta = –20 to +70°C, VSS= 0 V

* Note : Recommended crystal oscillator CI value : CI ≤ 35 kΩ

No. 5743-3/23

LC72137, 72137M

Electrical Characteristics within the allowable operating ranges

Ratings

Parameter Symbol Conditions

min typ max

Unit

Rf1 XIN 8.0 MΩ

Internal feedback resistors

Rf2 FMIN 500 kΩ
Rf3 AMIN 500 kΩ
Rf4 IFIN 250 kΩ

Internal pull-down resistors

Rpd1 FMIN 200 kΩ

Rpd2 AMIN 200 kΩ
Internal output resistor Rd XOUT 250 kΩ
Hysteresis V

HIS

CE, CL, DI, IO1, IO2 0.1 V

DD

V

Output high-level voltage V

OH

1 PD: IO= –1 mA VDD– 1.0 V

V

OL

1 PD: IO= 1 mA 1.0 V

V

OL

2

BO1 to BO4, IO1, IO2; I

O

= 1 mA 0.25 V

Output low-level voltage BO1 to BO4, IO1, IO2; I

O

= 5 mA 1.25 V

V

OL

3 DO: IO= 1 mA 0.25 V

V

OL

4 AOUT, AIN= 1.3 V 0.5

I

IH

1 CE, CL, DI: VI= 6.5 V 5.0 µA

I

IH

2 IO1, IO2: VI= 13 V 5.0 µA

Input high-level voltage

I

IH

3 XIN: VI= V

DD

0.16 0.9 µA

I

IH

4 FMIN, AMIN: VI= V

DD

2.5 15 µA

I

IH

5 IFIN: VI= V

DD

5.0 30 µA

I

IH

6 AIN: VI= 6.5 V 200 nA

I

IL

1 CE, CL, DI: VI= 0 V 5.0 µA

I

IL

2 IO1, IO2: VI= 0 V 5.0 µA

Input low-level current

I

IL

3 XIN: VI= 0 V 0.16 0.9 µA

I

IL

4 FMIN, AMIN: VI= 0 V 2.5 15 µA

I

IL

5 IFIN: VI= 0 V 5.0 30 µA

I

IL

6 AIN: VI= 0 V 200 nA

Output off leakage current

I

OFF

1 BO1 to BO4, AOUT, IO1, IO2: VO= 13 V 5.0 µA

I

OFF

2 DO: VO= 6.5 V 5.0 µA

High-level three-state off

I

OFFH

PD: VO= V

DD

0.01 200 nA

leakage current
Low-level three-state off

I

OFFL

PD: VO= 0 V 0.01 200 nA

leakage current
Input capacitance C

IN

FMIN 6 pF

I

DD

1 VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 20 mVrms 2.5 6 mA

Current drain I

DD

2

V

DD

: PLL block stopped (PLL inhibit),

20 mA

Xtal oscillator operating (Xtal = 75 kHz)

I

DD

3 VDD: PLL block stopped, Xtal oscillator stopped 10 µA

No. 5743-4/23

LC72137, 72137M

Pin Assignments

No. 5743-5/23

LC72137, 72137M

Block Diagram

No. 5743-6/23

LC72137, 72137M

Pin Descriptions

Pin No.

Symbol (MFP pin numbers Type Functions Circuit configuration

are in parentheses.)

20 (19)
21 (21)

13 (12)

12 (11)

2 (1)

4 (3)

3 (2)

5 (4)

15 (14)

16 (15)

XIN

XOUT

FMIN

AMIN

CE

CL

DI

DO

V

DD

V

SS

Xtal

Local oscillator
signal input

Local oscillator
signal input

Chip enable

Clock

Input data

Output data

Power supply

Ground

• Crystal oscillator connections (75 kHz)

• FMIN is selected when the serial data input DVS bit is
set to 1.

• The input frequency range is from 10 to 160 MHz.

• The input signal passes through the internal divide-by­two prescaler and is input to the swallow counter.

• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.

• AMIN is selected when the serial data input DVS bit is
set to 0.

• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and

the divisor used will be the value set.

• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable

divider.

— The divisor can be in the range 4 to 4095, and the

divisor used will be the value set.

• Set this pin high when inputting (DI) or outputting (DO)
serial data.

• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.

• Inputs serial data transferred from the controller to the
LC72137.

• Outputs serial data transferred from the LC72137 to the
controller. The data output is determined by the DOC0 to
DOC2 bits in the serial data.

• The LC72137 power supply pin. (V

DD

= 2.5 to 3.6 V)

• The power on reset circuit operates when power is first
applied.

• The LC72137N ground

Continued on next page.

No. 5743-7/23

LC72137, 72137M

Continued from preceding page.

Pin No.

Symbol (MFP pin numbers Type Functions Circuit configuration

are in parentheses.)

6 (5)
7 (6)
8 (7)

14 (13)

9 (8)

10 (9)

17 (16)

18 (17)
19 (18)

10 (9)

BO1
BO2
BO3
BO4

IO1
IO2

PD

AIN

AOUT

NC

Output ports

Input or output
ports

Charge pump
output

LPF amplifier
transistor
connections

IF counter

• Dedicated outputs

• The output states are determined by the BO1 to BO5
bits in the serial data.
Data: 0 = open, 1= low

• A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)

• I/O dual-use pins

• The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port

• When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value

high = 1 data value

• When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low

• These pins function as input pins following a power on
reset.

• PLL charge pump output
When the frequency generated by dividing the local
oscillator signal frequency by N is higher than the
reference frequency, a high level is output from the PD
pin. Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high-impedance state
when the frequencies match.

• The n-channel MOS transistor used for the PLL active
low-pass filter.

• Accepts an input in the frequency range 0.4 to 12 MHz.

• The input signal is directly transmitted to the IF counter.

• The result is output starting the MSB of the IF counter
using the DO pin.

• Four measurement periods are supported: 4, 8, 16, and
32 ms.

IFIN

1 (–)

22 (–)

NC Pin

• No connection