Sanyo LC72135M Specifications

Ordering number : EN5175A

CMOS LSI

LC72135M

PLL Frequency Synthesizer for Electronic

Tuning

Overview

The LC72135M is a PLL frequency synthesizer LSI for tuners in car stereo and similar applications. Highperformance AM/FM tuners can be easily implemented with this product.

Functions

•High-speed programmable dividers

— FMIN: 10 to 160 MHz ..........pulse swallower

(built-in divide-by-two prescaler)

—AMIN: 2 to 40 MHz ..............pulse swallower

0.5to 10 MHz ...........direct division

•IF counter

—HCTR 0.4 to 12 MHz ...........AM/FM IF counter

— LCTR 100 to 500 k Hz.........AM IF counter

•Reference frequencies

—Twelve selectable frequencies (4.5 or 7.2 MHz crystal)

1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz

•Phase comparator

—Dead zone control

—Unlock detection circuit

—Deadlock clear circuit

•Built-in MOS transistor for forming an active low-pass filter

•I/O ports

—Dedicated output ports: 4

—Input or output ports: 1

—Input ports (LCTR) : 1

—Support clock time base output

•Serial data I/O

—Support CCB format communication with the system controller.

•Operating ranges

—Supply voltage........................4.5 to 5.5 V

—Operating temperature............–40 to +85°C

•Package

—MFP20

Package Dimensions

unit: mm

3036B-MFP20

[LC72135M]

SANYO: MFP20

•CCB is a trademark of SANYO ELECTRIC CO., LTD.

•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

83098HA (OT)/22896HA (OT) No. 5175-1/24

LC72135M

Pin Assignment

No. 5175-2/24

LC72135M

Block Diagram

No. 5175-3/24

LC72135M

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter

Symbol

Pins

Ratings

Unit

Maximum supply voltage

VDD max

VDD

–0.3 to +7.0

VIN1 max

CE, CL, DI, AIN

–0.3 to +7.0

Maximum input voltage

VIN2 max

XIN, FMIN, AMIN, HCTR, LCTR/I1

–0.3 to VDD + 0.3

VIN3 max

–0.3 to +15

IO2

VO1 max

–0.3 to +7.0

Maximum output voltage

VO2 max

XOUT, PD

–0.3 to VDD + 0.3

VO3 max

AOUT

–0.3 to +15

BO1

BO4,

IO2,

IO1 max

0 to 3.0

BO1

Maximum output current

IO2 max

AOUT, DO

0 to 6.0

IO3 max

0 to 10.0

BO2

BO4,

IO2

Allowable power dissipation

Pd max

Ta ≤ 85°C

180

Operating temperature

Topr

–40 to +85

°C

Storage temperature

Tstg

–55 to +125

°C

Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

Parameter

Symbol

Pins

Conditions

min

typ

max

Unit

Supply voltage

VDD

4.5

5.5

VIH1

CE, CL, DI

0.7 VDD

6.5

Input high-level voltage

VIH2

LCTR/I1

0.7 VDD

VDD

VIH3

0.7 VDD

IO2

Input low-level voltage

VIL

CE, CL, DI,

, LCTR/I1

0.3 VDD

IO2

Output voltage

VO1

+6.5

VO2

BO1 to BO4, IO2, AOUT

+13

fIN1

XIN

VIN1

MHz

fIN2

FMIN

VIN2

160

MHz

Input frequency

fIN3

AMIN

VIN3, SNS = 1

MHz

fIN4

AMIN

VIN4, SNS = 0

0.5

MHz

fIN5

HCTR

VIN5

0.4

MHz

fIN6

LCTR/I1

VIN6

100

500

kHz

VIN1

XIN

fIN1

400

1500

mVrms

VIN2-1

FMIN

f = 10 to 130 MHz

1500

mVrms

VIN2-2

FMIN

f = 130 to 160 MHz

1500

mVrms

VIN3

AMIN

fIN3, SNS = 1

1500

mVrms

Input amplitude

VIN4

AMIN

fIN4, SNS = 0

1500

mVrms

VIN5-1

HCTR

fIN5, IFS = 1

1500

mVrms

VIN5-2

HCTR

fIN5, IFS = 0

1500

mVrms

VIN6-1

LCTR/I1

fIN6, IFS = 1

1500

mVrms

VIN6-2

LCTR/I1

fIN6, IFS = 0

1500

mVrms

Supported crystals

Xtal

XIN, XOUT

4.0

8.0

MHz

Note: * Recommended crystal oscillator CI values:

CI ≤ 120Ω (For a 4.5 MHz crystal)

CI ≤ 70Ω (For a 7.2 MHz crystal)

Crystal oscillator: HC-49/U (manufactured by Kinseki, Ltd.), CL = 12 pF C1 = C2 = 15 pF

The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we recommend consulting with the manufacturer of the crystal about evaluation and reliability.

No. 5175-4/24

LC72135M

Electrical Characteristics for the Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V

Parameter

Symbol

Pins

Conditions

min

typ

max

Unit

Rf1

XIN

1.0

MΩ

Built-in feedback resistance

Rf2

FMIN

500

kΩ

Rf3

AMIN

500

kΩ

Rf4

HCTR

250

kΩ

Rf5

LCTR/I1

250

kΩ

Built-in pull-down resistor

Rpd1

FMIN

200

kΩ

Rpd2

AMIN

200

kΩ

Hysteresis

VHIS

CE, CL, DI,

IO2,

LCTR/I1

0.1 VDD

Output high-level voltage

VOH1

IO = –1 mA

VDD – 1.0

VOL1

IO = 1 mA

1.0

VOL2

IO = 0.5 mA

0.5

BO1

IO = 1 mA

1.0

VOL3

IO = 1 mA

0.2

Output low-level voltage

IO = 5 mA

1.0

IO = 1 mA

0.2

VOL4

IO = 5 mA

1.0

BO2

BO4,

IO2

IO = 8 mA

1.6

VOL5

AOUT

IO = 1 mA, AIN = 1.3 V

0.5

IIH1

CE, CL, DI

VI = 6.5 V

5.0

IIH2

LCTR/I1

VI = VDD, L/I1 = 0

5.0

µA

IIH3

VI = 13 V

5.0

µA

IO2

Input high-level current

IIH4

XIN

VI = VDD

2.0

µA

IIH5

FMIN, AMIN

VI = VDD

4.0

µA

IIH6

HCTR, LCTR/I1

VI = VDD, L/I1 = 1

8.0

µA

IIH7

AIN

VI = 6.5 V

200

IIL1

CE, CL, DI

VI = 0 V

5.0

µA

IIL2

LCTR/I1

VI = 0 V, L/I1 = 0

5.0

µA

IIL3

VI = 0 V

5.0

µA

Input low-level current

IO2

IIL4

XIN

VI = 0 V

2.0

µA

IIL5

FMIN, AMIN

VI = 0 V

4.0

µA

IIL6

HCTR, LCTR/I1

VI = 0 V, L/I1 = 1

8.0

µA

IIL7

AIN

VI = 0 V

200

AOUT,

IOFF1

BO1

BO4,

VO = 13 V

5.0

µA

Output off leakage current

IO2

IOFF2

VO = 6.5 V

5.0

µA

High-level three-state

IOFFH

VO = VDD

0.01

200

off leakage current

Low-level three-state

IOFFL

VO = 0 V

0.01

200

off leakage current

Input capacitance

CIN

FMIN

Xtal = 7.2 MHz,

IDD1

VDD

fIN2 = 130 MHz,

VIN2 = 40 mVrms

PLL block stopped

Current drain

IDD2

VDD

(PLL INHIBIT),

0.5

Xtal oscillator operating

(Xtal = 7.2 MHz)

IDD3

VDD

PLL block stopped

µA

Xtal oscillator stopped

No. 5175-5/24

LC72135M

Pin Functions

Symbol	Pin No.	Type		Functions	Circuit configuration

XIN	1	Xtal OSC	•	Crystal resonator connection
XOUT	20	Xtal OSC		(4.5/7.2 MHz)
XOUT	20			(4.5/7.2 MHz)

			•	FMIN is selected when the serial data input DVS bit is
				set to 1.
			• The input frequency range is from 10 to 160 MHz.
FMIN	14	Local oscillator	•	The input signal passes through the internal divide-by-
FMIN	14	signal input		two prescaler and is input to the swallow counter.
		signal input		two prescaler and is input to the swallow counter.
			• The divisor can be in the range 272 to 65535. However,
				since the signal has passed through the divide-by-two
				prescaler, the actual divisor is twice the set value.

			•	AMIN is selected when the serial data input DVS bit is
				set to 0.
			•	When the serial data input SNS bit is set to 1:
				— The input frequency range is 2 to 40 MHz.
				— The signal is directly input to the swallow counter.
		Local oscillator		— The divisor can be in the range 272 to 65535, and
AMIN	13	Local oscillator		the divisor used will be the value set.
AMIN	13	signal input		the divisor used will be the value set.
		signal input	•	When the serial data input SNS bit is set to 0:
			•	When the serial data input SNS bit is set to 0:
				— The input frequency range is 0.5 to 10 MHz.
				— The signal is directly input to a 12-bit programmable
				divider.
				— The divisor can be in the range 4 to 4095, and the
				divisor used will be the value set.

CE	2	Chip enable		Set this pin high when inputting (DI) or outputting (DO)
CE	2	Chip enable		serial data.
				serial data.

CL	4	Clock	•	Used as the synchronization clock when inputting (DI) or
CL	4	Clock		outputting (DO) serial data.
				outputting (DO) serial data.

DI	3	Data input	•	Inputs serial data transferred from the controller to the
DI	3	Data input		LC72135M.
				LC72135M.

			•	Outputs serial data transferred from the LC72135M to
DO	5	Data output		the controller.
DO	5	Data output		The content of the output data is determined by the
				The content of the output data is determined by the
				serial data DOC0 to DOC2.

VDD			• The LC72135M power supply pin (VDD = 4.5 to 5.5 V)
VDD	15	Power supply	• The power on reset circuit operates when power is first
				applied.

					Continued on next page.

No. 5175-6/24

LC72135M

Continued from preceding page.

Symbol

Pin No.

Type

Functions

Circuit configuration

VSS

Ground

• The LC72135M ground

—

•

Dedicated output pins

• The output states are determined by BO1 to BO4 bits in

the serial data.

Data: 0 = open, 1 = low

BO1

•

All output ports are set to the open state following a

BO2

Output port

power-on reset.

BO3

• A time base signal (8 Hz) can be output from the BO1

BO4

pin. (When the serial data TBC bit is set to 1.)

•

Care is required when using the

BO1

pin, since it has a

higher on impedance that the other output ports (pins

BO2

BO4)

•

I/O dual-use pins

•

The direction (input or output) is determined by bit IOC2

in the serial data.

Data: 0 = input port, 1 = output port

•

When specified for use as input ports:

The state of the input pin is transmitted to the controller

over the DO pin.

IO2

I/O port

Input state: low = 0 data value

high = 1 data value

•

When specified for use as output ports:

The output states are determined by the IO2 bit in the

serial data.

Data: 0 = open, 1 = low

•

The pin function as input pin following a power-on reset.

• PLL charge pump output

When the frequency generated by dividing the local

Charge pump

oscillator frequency by N is higher than the reference

frequency, a high level is output from the PD pin.

output

Similarly, when that frequency is lower, a low level is

output. The PD pin goes to the high-impedance state

when the frequencies match.

AIN

LPF amplifier

• The n-channel MOS transistor used for the PLL active

AOUT

transistor

low-pass filter.

Continued on next page.

No. 5157-7/24

LC72135M

Continued from preceding page.

Symbol	Pin No.	Type		Functions	Circuit configuration

			•	HCTR is selected when the LCTS bit in the serial data is
				set to 0.
			• Accepts an input in the frequency range 0.4 to 12 MHz.
HCTR	11	IF counter	•	The input signal is directly transmitted to the IF counter.
HCTR	11	IF counter	•	The result is output starting the MSB of the IF counter
			•	The result is output starting the MSB of the IF counter
				using the DO pin.
			• Four measurement periods are supported: 4, 8, 32, and
				64 ms.

		IF counter	•	LCTR is selected when the LCTS bit in the serial data is
				set to 1. (Set the L/I1 bit in the serial data to 1 when
				using the IF counter.)
			• The input frequency range is 100 to 500 kHz.
			•	The signal is directly transmitted to the IF counter.
LCTR/I1	10		•	The result, starting with the MSB of the IF counter, is
LCTR/I1	10			output serially through the DO pin.
			• There are four measurement times: 4, 8, 32, and 64 ms.
		Input port	•	If the L/I1 bit in the serial data is set to 0, the LCTR/I1 pin
				functions as an input port and the state of that input pin is
				transmitted to the controller from the DO pin.
			•	When the input state is low, the data will be 0, and when
				the state is high, the data will be 1.

No. 5175-8/24

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