SANYO LC72122V Datasheet

CMOS IC

Ordering number : ENN6113A

D0199TH (OT) /O3099TH (OT) /D2598RM (OT)No. 6113-1/22

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

PLL Frequency Synthesizer

for Portable Equipment Electronic Tuning

LC72122V

Overview

The LC72122V is a low-voltage (1.8 to 3.6 V) PLL
frequency synthesizer IC that allows portable TV
(VHF)/FM/AM tuners to be constructed easily.

Features

• High-speed programmable frequency divider
— FMIN: 10 to 250 MHz..Pulse swallower

(divide-by-two prescaler built in)

— AMIN: 2 to 40 MHz ......Pulse swallower

0.5 to 10 MHz ...Direct division

• IF counter

— IFIN: 0.4 to 12 MHz......For use as an AM/FM IF

counter

• Reference frequency
— Selectable from one of nine frequencies (crystal

oscillator: 75 kHz)
1, 2.5, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz

• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
— Sub-charge pump for fast frequency locking

• Built-in MOS transistor for forming an active low-pass

filter

• I/O ports
— Dedicated output ports: 3
— I/O ports: 2
— Supports clock time base output

• Serial Data I/O
— Supports CCB format communication with the

system controller.

• Operating ranges
— Supply voltage: 1.8 to 3.6 V
— Operating temperature: –20 to +70°C

• Package

—SSOP20

Package Dimensions

unit: mm

3179A-SSOP20

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

SANYO: SSOP20

[LC72122V]

20

110

6.7

11

4.4

1.6max

0.1

0.650.22 0.43

1.0

6.4

0.5

0.15

No. 6113-2/22

LC72122V

Specifications

Absolute Maximum Ratings at Ta = 25°C, V

SSd

= V

SSa

= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

DD

max V

DD

–0.3 to +4.0 V

V

IN

1 max CE, CL, DI –0.3 to +7.0 V

Maximum input voltage V

IN

2 max XIN, FMIN, AMIN, IFIN, AIN –0.3 to VDD+ 0.3 V

V

IN

3 max IO1, IO2 –0.3 to +8 V

V

O

1 max DO –0.3 to +7.0 V

Maximum output voltage V

O

2 max XOUT, PD –0.3 to VDD+ 0.3 V

V

O

3 max BO1 to BO3,AOUT –0.3 to +15 V

V

O

4 max IO1, IO2 –0.3 to +8 V

Maximum output current I

O

max BO1 to BO3, IO1, IO2, DO, AOUT 0 to 6.0 mA
Allowable power dissipation Pd max Ta ≤ 70°C: SSOP20 150 mW
Operating temperature Topr –20 to +70 °C
Storage temperature Tstg –40 to +125 °C

Ratings

Parameter Symbol Conditions

min typ max

Unit

Supply voltage V

DD

V

DD

1.8 2.2 3.6 V

Input high-level voltage

V

IH

1 CE, CL, DI 0.7 V

DD

6.5 V

V

IH

2 IO1, IO2 0.7 V

DD

7V

Input low-level voltage V

IL

CE, CL, DI, IO1, IO2 0 0.3 V

DD

V

V

O

1 DO 0 6.5 V

Output voltage V

O

2 BO1 to BO3, AOUT 0 13 V

V

O

3 IO1, IO2 0 7 V

f

IN

1 XIN: VIN1 75 kHz

f

IN

2 FMIN: VIN2 10 250 MHz

Input frequency f

IN

3 AMIN: VIN3, SNS = 1 2 40 MHz

f

IN

4 AMIN: VIN4, SNS = 0 0.5 10 MHz

f

IN

5 IFIN: VIN5 0.4 12 MHz

V

IN

1 XIN: fIN1 200 600 mVrms

V

IN

2-1 FMIN: f = 10 to 50 MHz 50 600 mVrms

V

IN

2-2 FMIN: f = 50 to 250 MHz 40 600 mVrms

Input amplitude V

IN

3 AMIN: fIN3, SNS = 1 30 600 mVrms

V

IN

4 AMIN: fIN4, SNS = 0 30 600 mVrms

V

IN

5-1 IFIN: fIN5, IFS = 1 30 600 mVrms

V

IN

5-2 IFIN: fIN5, IFS = 0 70 600 mVrms

Guaranteed crystal

Xtal XIN, XOUT * 75 kHz

oscillator frequency

Allowable Operating Ranges at Ta = –20 to +70°C, V

SSd

= V

SSa

= 0 V

* Note : Recommended crystal oscillator CI value : CI ≤ 35 kΩ (for a 75kHz crystal )

The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed sircuit board pattem, and other items. Therefore we
recommend consulting with the manfacturer of the crystal for evaluation and reliability.
The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.

No. 6113-3/22

LC72122V

Electrical Characteristics within the allowable operating ranges

Ratings

Parameter Symbol Conditions

min typ max

Unit

Rf1 XIN 8.0 MΩ

Internal feedback resistors

Rf2 FMIN 500 kΩ
Rf3 AMIN 500 kΩ
Rf4 IFIN 500 kΩ

Internal pull-down resistors

Rpd1 FMIN 200 kΩ

Rpd2 AMIN 200 kΩ
Internal output resistor Rd XOUT 250 kΩ
Hysteresis V

HIS

CE, CL, DI, IO1, IO2 0.1 V

DD

V

V

OH

1 PD: IO= –1 mA VDD– 0.5 V

Output high-level voltage

V

OH

2

AIN (PDS) : I

O

= – 2 mA (VDD= 1.8 to 2.7 V) VDD– 0.5 V

AIN (PDS) : I

O

= – 4 mA (VDD= 2.7 to 3.6 V) VDD– 0.5 V

V

OL

1 PD: IO= 1 mA 0.5 V

V

OL

2

AIN (PDS) : I

O

= 2 mA (VDD= 1.8 to 2.7 V) 0.5 V

AIN (PDS) : I

O

= 4 mA (VDD= 2.7 to 3.6 V) 0.5 V

BO1 to BO3, IO1, IO2; I

O

= 1 mA 0.2 V

Output low-level voltage V

OL

3 BO1 to BO3, IO1, IO2; IO= 5 mA 1.0 V

BO1 to BO3, IO1, IO2; I

O

= 8 mA 1.6 V

V

OL

4

DO: I

O

= 1 mA 0.2 V

DO: I

O

= 5 mA 1.0 V

V

OL

5 AOUT, IO= 5 mA, AIN= 1.2 V 1.5 V

I

IH

1 CE, CL, DI: VI= 6.5 V 5.0 µA

I

IH

2 IO1, IO2: VI= 7 V 5.0 µA

Input high-level current

I

IH

3 XIN: VI= V

DD

0.11 0.45 1.3 µA

I

IH

4 FMIN, AMIN: VI= V

DD

1.8 7.2 22 µA

I

IH

5 IFIN: VI= V

DD

1.8 7.2 22 µA

I

IH

6 AIN: VI= V

DD

200 nA

I

IL

1 CE, CL, DI: VI= 0 V 5.0 µA

I

IL

2 IO1, IO2: VI= 0 V 5.0 µA

Input low-level current

I

IL

3 XIN: VI= 0 V 0.11 0.45 1.3 µA

I

IL

4 FMIN, AMIN: VI= 0 V 1.8 7.2 22 µA

I

IL

5 IFIN: VI= 0 V 1.8 7.2 22 µA

I

IL

6 AIN: VI= 0 V 200 nA

I

OFF

1 BO1 to BO3, AOUT: VO= 13 V 5.0 µA

Output off leakage current I

OFF

2 IO1, IO2: VO= 7 V 5.0 µA

I

OFF

3 DO: VO= 6.5 V 5.0 µA

High-level three-state off

I

OFFH

PD: VO= V

DD

0.01 200 nA

leakage current
Low-level three-state off

I

OFFL

PD: VO= 0 V 0.01 200 nA

leakage current
Input capacitance C

IN

FMIN 6pF

I

DD

1VDD: Xtal = 75 kHz, fIN2 = 250 MHz, VIN2 = 40 mVrms 4 10 mA

Supply current I

DD

2

V

DD

: PLL block stopped (PLL inhibit),

10 µA

Xtal oscillator operating (Xtal = 75 kHz)

IDD3VDD: PLL block stopped, Xtal oscillator stopped 10 µA

No. 6113-4/22

LC72122V

Pin Assignment

Top view

Block Diagram

No. 6113-5/22

LC72122V

Pin Descriptions

Symbol Pin No. Type Functions Circuit configuration

19
20

12

11

1

3

2

4

13

14

XIN

XOUT

FMIN

AMIN

CE

CL

DI

DO

V

DD

V

SSd

Xtal

Local oscillator
signal input

Local oscillator
signal input

Chip enable

Clock

Input data

Output data

Power supply

Ground

• Crystal oscillator connections (75 kHz)

• FMIN is selected when the serial data input DVS bit is
set to 1.

• The input frequency range is from 10 to 250 MHz.

• The input signal passes through the internal divide-by­two prescaler and is input to the swallow counter.

• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.

• AMIN is selected when the serial data input DVS bit is
set to 0.

• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and

the divisor used will be the value set.

• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable

divider.

— The divisor can be in the range 4 to 4095, and the

divisor used will be the value set.

• Set this pin high when inputting (DI) or outputting (DO)
serial data.

• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).

• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.

• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).

• Inputs serial data transferred from the controller to the
LC72122V.

• Up to 6.5 V may be applied, regardless of the actual
supply voltage (VDD).

• Outputs serial data transferred from the LC72122V to
the controller. The data output is determined by the
DOC0 to DOC2 bits in the serial data.

• The LC72122V power supply pin. (V

DD

= 1.8 to 3.6 V)

• The power on reset circuit operates when power is first
applied.

• The LC72122V ground

Continued on next page.

No. 6113-6/22

LC72122V

Continued from preceding page.

Symbol Pin No. Type Functions Circuit configuration

5
6
7

8
9

15

16
17
18

10

BO1
BO2
BO3

IO1
IO2

PD

AIN

AOUT

Vssa

Output ports

Input or output
ports

Charge pump
output

LPF amplifier
transistor
connections

IF counter

• Dedicated outputs

• The output states are determined by the BO1 to BO3
bits in the serial data.
Data: 0 = open, 1= low

• A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)

• I/O dual-use pins

• The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port

• When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value

high = 1 data value

• When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low

• These pins function as input pins following a power on
reset.

• PLL charge pump output
When the frequency generated by dividing the local
oscillator signal frequency by N is higher than the
reference frequency, a high level is output from the PD
pin. Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high-impedance state
when the frequencies match.

• The n-channel MOS transistor used for the PLL active
low-pass filter.

• The AIN pin is connected internally to a fast locking sub­charge pump circuit (PDS).

• Vssa is special-purpose ground pin.

• Accepts an input in the frequency range 0.4 to 12 MHz.

• The input signal is directly transmitted to the IF counter.

• The result is output starting the MSB of the IF counter
using the DO pin.

• Four measurement periods are supported: 8, 16, 32, and
64 ms.

IFIN

No. 6113-7/22

LC72122V

Serial Data I/O Procedures

The LC72122V inputs and outputs data using the Sanyo CCB (computer control bus) audio IC serial bus format. This IC
adopts an 8-bit address format CCB.

I/O mode

Address

Function

B0 B1 B2 B3 A0 A1 A2 A3

1

2

3

IN1 (82)

IN2 (92)

OUT (A2)

00010100

10010100

01010100

• Control data input mode (serial data input)

• 24 data bits are input.

• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.

• Control data input mode (serial data input)

• 24 data bits are input.

• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.

• Data output mode (serial data output)

• The number of bits output is equal to the number of clock
cycles.

• See the “DO Output Data (Serial Data Output) Structure”
item for details on the meaning of the output data.