SANYO LC66P5316 Datasheet

CMOS LSI

No. 5489

Preriminary

Overview

The LC66P5316 is an on-chip OTP PROM version of the LC6653XX Series CMOS 4-bit single-chip microcontrollers. The LC66P5316 is appropriate for program development and product evaluation since it provides identical functionality and pin compatibility with the LC665316A.

Features and Functions

• On-chip OTP ROM capacity of 16 kilobytes, and an on-

chip RAM capacity of 512 × 4 bits.

• Fully supports the LC66000 Series common instruction set (128 instructions).

• I/O ports: 42 pins

• A sub-oscillator circuit can be used (option) This circuit allows power dissipation to be reduced by operating at lower speeds.

• 8-bit serial interface: two circuits (can be connected in cascade to form a 16-bit interface)

• Instruction cycle time: 0.95 to 10 µs (at 4.0 to 5.5 V)

• Powerful timer functions and prescalers — Time limit timer, event counter, pulse width

measurement, and square wave output using a 12-bit timer.

— Time limit timer, event counter, PWM output, and

square wave output using an 8-bit timer.

— Time base function using a 12-bit prescaler

• Powerful interrupt system with 8 interrupt factors and 8 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 5 factors/5 vector locations

• Flexible I/O functions 16-value comparator inputs, 20-mA drive outputs, inverter circuits, pull-up and open-drain circuits selectable as options.

• Optional runaway detection function (watchdog timer)

• 8-bit I/O functions

• Power saving functions using halt and hold modes.

• Packages: DIP48S, QIP48E (QFP48E)

• Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2

LC66P5316

Four-Bit Single-Chip Microcontroller

with 16 KB of On-Chip OTP PROM

Package Dimensions

unit: mm

3149-DIP48S

[LC66P5316]

2548

15.24

13.8

0.48

unit: mm

3156-QFP48E

1.614.0

17.2

3.0max

46.0

1.05 1.78

[LC66P5316]

17.2

14.0

1.0

1.5 36

1.5

1.0

1.5

112

0.35

0.8

15.6

2.53

1.6

1.5 25

SANYO: QFP48E

5.1max

4.25

3.8

0.51min

SANYO: DIP48S

0.15

0.1

2.70

(STAND OFF)

0.25

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

22897HA (OT) No. 5489-1/28

Series Organization

LC66P5316

Type No.

LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42 LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E

LC665304A/06A/08A/12A/16A 48

LC66E308 42 EPROM 8 KB 512 W LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E408 42 EPROM 8 KB 512 W LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E516 64 EPROM 16 KB 512 W LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E

LC66E2108* 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W

LC66E2516 64 EPROM 16 KB 512 W

LC66E5316 52/48 EPROM 16 KB 512 W LC66P2108* 30 OTPROM 8 KB 384 W DIP30SD MFP30S

LC66P2316* 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E

Note: * Under development

No. of

pins capacity

ROM capacity

4 K/6 K/8 K/12 K/16 KB

RAM

512 W DIP42S QFP48E

512 W DIP48S QFP48E

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC52S QFC48 with window with window

Package Features

Normal versions

4.0 to 6.0 V/0.92 µs

Low-voltage versions

2.2 to 5.5 V/3.92 µs

Low-voltage high-speed versions

3.0 to 5.5 V/0.92 µs

On-chip DTMF generator versions

3.0 to 5.5 V/0.95 µs

Dual oscillator support

3.0 to 5.5 V/0.95 µs

Window and OTP evaluation versions

4.5 to 5.5 V/0.92 µs

Window evaluation versions

4.5 to 5.5 V/0.92 µs

OTP

4.0 to 5.5 V/0.95 µs

No. 5489-2/28

Pin Assignments

LC66P5316

DIP48S

P20/SI0/A0

P21/SO0/A1

P22/SCK0/A2

P23/INT0/A3

P30/INT1/A4 P31/POUT0/A5 P32/POUT1/A6

RES/VPP/OE

TEST/EPMOD

P40/INV0I/A7

P41/INV0O/A8

P42/INV1I/A9

P43/INV1O/A10

OSC1 OSC2

PE0/XT1 PE1/XT2

P33/HOLD

P50/A11 P51/A12 P52/A13

P53/INT2/TA

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2 3 4 5 6 7 8 9

LC66P5316

QFP48E

P13/D7

P12/D6

P11/D5

P10/D4

P03/D3

P02/D2

P01/D1

P00/D0

PD3/AN4/INV4O

PD2/AN3/INV4I

PD1/AN2/INV3O

PD0/AN1/INV3I

PC3/INV2O/DASEC

PC2/INV2I/CE

PC1

PC0

P83

P82

P81/DS1

P80/DS0

P63/PIN1

P62/SCK1

P61/SO1

P60/SI1

P01/D1

P00/D0

PD3/AN4/INV4O

PD2/AN3/INV4I

PD1/AN2/INV3O

PD0/AN1/INV3I

PC3/INV2O/DASEC

PC2/INV2I/CE

PC1

PC0

P83

P82

25 37P02/D2 38P03/D3 23 P80/DS0 39P10/D4 22 P63/PIN1 40P11/D5 21 P62/SCK1 41P12/D6 20 P61/SO1 42P13/D7 19 P60/SI1 43P20/SI0/A0 18 P53/INT2/TA 44P21/SO0/A1 17 P52/A13 45P22/SCK0/A2 16 P51/A12 46P23/INT0/A3 15 P50/A11 47P30/INT1/A4 14 P43/INV1O/A10 48P31/POUT0/A5 13 P42/INV1I/A9

P32/POUT1/A6

LC66P5316

OSC1

OSC2

/OE

PE0/XT1

PE1/XT2

RES/V

TEST/EPMOD

P33/HOLD

P40/INV0I/A7

24 P81/DS1

P41/INV0O/A8

Top view

We recommend the use of reflow soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).

No. 5489-3/28

LC66P5316

Usage Notes

The LC66P5316 was created for program development, product evaluation, and prototype development for products based on the LC6653XX Series microcontrollers. Keep the following points in mind when using this product.

1. After a reset The RES pin must be held low for an additional 3 instruction cycles after the oscillator stabilization period has elapsed. Also, the port output circuit types are set up during the 9 instruction cycles immediately after RES is set high. Only then is the program counter set to 0 and program execution started from that location. (The port output circuits all revert to the open-drain type during periods when RES is low.)

min

OSC

RES

At least 10 ms Oscillator

stabilization 

At least 3  instruction 

Program execution (PC)  

Port output type

Open drain

Option switching period

9 instruction  cycles

Location 0Location 

Option specification

2. Notes on LC6653XX evaluation The high end of the EPROM area (locations 3FF0H to 3FFFH) are the option specification area. Option specification data must be programmed for and loaded into this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the mask ROM.

3. Mounting notes Due to structural considerations, Sanyo is unable to fully test one-time programmable products. Therefore, the user must apply the screening procedure described on page 20 to these products.

4. Use the following procedure when ordering ROM through the Sanyo PROM writing service. (Note that this is a forfee service.)

• If ordering one-time programmable and mask ROM versions at the same time:

The customer must provide the EPROM for the mask ROM version, the order forms for the mask ROM version, and the order forms for the one-time programmable version.

• If ordering only the one-time programmable version:

The customer must provide the EPROM and the order forms for the one-time programmable version. The last section of the EPROM (locations 3FF0H to 3FFFH) is the option specification area, and the option specification data must be written to this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the mask ROM.

5. Differences between this product and the mask ROM version: Carefully read the sections on the following pages that describe these differences.

No. 5489-4/28

LC66P5316

Main differences between the LC66E5316, LC66P5316, and LC6653XX Series

Item LC6653XX Series (mask version) LC66E5316 LC66P5316

Differences in the main characteristics –30 to +70°C +10 to +40°C –30 to +70°C

• Operating temperature range

3.0 to 5.5 V/0.95 to 10 µs 4.5 to 5.5 V/0.95 to 10 µs 4.0 to 5.5 V/0.92 to 10 µs

• Operating supply voltage/operating frequency (cycle time)

• Input high-level current (RES) Maximum: 1 µA (normal operation and halt mode) (normal operation and halt mode)

• Input low-level current (RES) Maximum: 1 µA Typical: 100 µA Typical: 100 µA

• Current drain (Operating at 4 MHz) (Operating at 32 kHz) (Halt mode at 4 MHz) Typical: 10 nA, maximum: 10 µA* Typical: 10 nA, maximum: 10 µA* (Halt mode at 32 kHz) (Hold mode)

Port output types at reset

Package

Note: * Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after

switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also a current of about 100 µA flows from the RES pin when it is low. This increases the hold mode current drain by about 100 µA.

(When the main oscillator is (When the main oscillator is (When the main oscillator is

operating) operating) operating)

3.0 to 5.5 V/25 to 127 µs 4.5 to 5.5 V/25 to 127 µs 4.0 to 5.5 V/25 to 127 µs (When the sub-oscillator is operating) (When the sub-oscillator is operating) (When the sub-oscillator is operating)

Typical: 10 µA Typical: 10 µA

Hold mode: 1 µA maximum Hold mode: 1 µA maximum

Typical: 10 nA, maximum: 10 µA

The output type specified in the options

• DIP48S • DIC52S window package • DIP48S

• QFP48E • QFC48 window package • QFP48E

Larger than that for the mask versions Larger than that for the mask versions

Open-drain outputs Open-drain outputs

See the data sheets for the individual products for details on other differences.

System Block Diagram

RAM STACK

RES

TEST

OSC1 OSC2 HOLD

XT1 XT2

AN1 to 4

SYSTEM

CONTROL

ADC

(512W)

FLAG

SP E A

PRESCALER

D P Y

ALU

MPX TIMER0 SERIAL I/O 0

MPX

INTERRUPT

CONTROL

MPX

TIMER1

P0 P1 P2 P3 P4 P5 P6

SERIAL I/O 1

OTP ROM

(16KB)

POUT0 SI0 SO0

SCK0 INT0

INT1, INT2 SI1

SO1 SCK1 PIN1, POUT1

INV

xO INVxI

DS1 DS0

PROM control

(x=0 to 4)

A0 to A13 D0 to D7

CE DASEC

VPP/OE EPMOD TA

No. 5489-5/28

Pin Function Overview

LC66P5316

Pin I/O Overview Output driver type Options

P00/D0 P01/D1 P02/D2 P03/D3

P10/D4 P11/D5 P12/D6 P13/D7

P20/SI0/A0

P21/SO0/A1

P22/SCK0/

P23/INT0/A3

I/O ports P00 to P03

• Input or output in 4-bit or 1-bit units

• P00 to P03 support the halt mode

I/O

control function (This function can be specified in bit units.)

• Used as data pins in EPROM mode

I/O ports P10 to P13

• Input or output in 4-bit or 1-bit units

I/O

• Used as data pins in EPROM mode

I/O ports P20 to P23

• Input or output in 4-bit or 1-bit units

• P20 is also used as the serial input SI0 pin.

• P21 is also used as the serial output SO0 pin.

• P22 is also used as the serial clock

I/O

SCK0 pin.

• P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input.

• Used as address pins in EPROM mode

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pull-up MOS or

• Output level on

• Pull-up MOS or

• Output level on

CMOS or Nch OD output

Nch OD output

reset

Nch OD output

reset

State after a Standby mode

reset operation

Hold mode:

High or low (option)

Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Output off

P30/INT1/A4 P31/POUT0/

P32/POUT1/

P33/HOLD

P40/INV0I/

P41/INV0O/

P42/INV1I/

P43/INV1O/

A10

I/O ports P30 to P32

• Input or output in 3-bit or 1-bit units

• P30 is also used as the INT1 interrupt request.

• P31 is also used for the square wave output from timer 0.

I/O

• P32 is also used for the square wave and PWM output from timer 1.

• P31 and P32 also support 3-state outputs.

• Used as address pins in EPROM mode

Hold mode control input

• Hold mode is set up by the HOLD instruction when HOLD is low.

• In hold mode, the CPU is restarted by setting HOLD to the high level.

• This pin can be used as input port P33

along with P30 to P32.

• When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied.

I/O ports P40 to P43

• Input or output in 4-bit or 1-bit units

• Input or output in 8-bit units when used in conjunction with P50 to P53.

• Can be used for output of 8-bit ROM

I/O

data when used in conjunction with P50 to P53.

• Dedicated inverter circuit (option)

• Used as address pins in EPROM mode

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pch: Pull-up MOS type

• CMOS type when the inverter circuit option is selected

• Nch: Intermediate sink current type

CMOS or Nch OD output

• Pull-up MOS or Nch OD output

• Output level on reset

• Inverter circuit

• High or low (option)

• Inverter I/O is set to the output off state.

Hold mode: Output off

Halt mode: Output retained

Hold mode: Port output off, inverter output off

Halt mode: Port output retained, inverter output continues

Continued on next page.

No. 5489-6/28

Continued from preceding page.

LC66P5316

Pin I/O Overview Output driver type Options

I/O ports P50 to P53

• Input or output in 4-bit or 1-bit units

• Input or output in 8-bit units when used P50/A11 P51/A12 P52/A13

P53/INT2/TA

in conjunction with P40 to P43.

• Can be used for output of 8-bit ROM

I/O

data when used in conjunction with P40 to P43.

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pull-up MOS or

• Output level on

• P53 is also used as the INT2 interrupt request.

• Used as address pins in EPROM mode

I/O ports P60 to P63

• Input or output in 4-bit or 1-bit units

• P60 is also used as the serial input SI1

P60/SI1

P61/SO1

P62/SCK1

P63/PIN1

pin.

• P61 is also used as the serial output

I/O

SO1 pin.

• P62 is also used as the serial clock

• Pch: CMOS type

• Nch: Intermediate sink current type

• CMOS or Nch OD

SCK1 pin.

• P63 is also used for the event count input to timer 1.

P80/DS0 P81/DS1

P82 P83

Dedicated output ports P80 to P83

• Output in 4-bit or 1-bit units

• The contents of the output latch are

input using input instructions.

• P80 is a data shaper input (options)

• Pch: CMOS type

• Nch: Intermediate sink current type

• CMOS or Nch OD

• Output level at

• Data shaper

• P81 is a data shaper output (options)

Nch OD output

reset

output

reset

circuit

State after a Standby mode

reset operation

Hold mode: Output off

High or low (option)

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode:

Output off High or low (option)

Halt mode: Output retained

PC0 PC1

PC2/INV2I/

PC3/INV2O/

DASEC

I/O ports PC0 to PC3

• Output in 4-bit or 1-bit units

I/O

• Dedicated inverter circuits (option)

• Used as the control CE and DASEC pin in EPROM mode.

• Pch: CMOS type

• Nch: Intermediate sink current type

PD0/AN1/

INV3I

PD1/AN2/

INV3O

PD2/AN3/

INV4I

PD3/AN4/

Dedicated input ports PD0 to PD3

• Can be switched in software to function

as 16-value analog inputs.

• Dedicated inverter circuits (option)

• Only when the inverter circuit option is selected:

• Pch: CMOS type

• Nch: Intermediate sink current type

INV4O

PE0/XT1 PE1/XT2

OSC1

Dedicated input ports and sub-oscillator

connections

System clock oscillator connections When an external clock is used, leave

OSC2

OSC2 open and connect the clock signal to OSC1.

System reset input

• When the P33/HOLD pin is at the high

RES/V

TEST/

EPMOD

V V

DD SS

level, a low level input to the RES pin

will initialize the CPU.

• Used as the V mode.

/OE pin in EPROM

CPU test pin This pin must be connected to V

during normal operation.

Power supply pins

Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.

CMOS output: Complementary output. OD output: Open-drain output.

• CMOS or Nch OD output

• Inverter circuits

Inverter circuits

Sub-oscillator/port PE selection

Ceramic oscillator or external clock selection

Normal input

Option selection

Hold mode: Output off

Halt mode: Output retained

Inverter

• Hold mode: Output off

• Halt mode: Output continues

Hold mode: Oscillator stops

Halt mode: Oscillator continues

No. 5489-7/28

LC66P5316

User Options

1. Port 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the following two options.

Option Conditions and notes

1. Output high at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group

2. Output low at reset The four bits of ports 0, 1, 4, 5, or 8 are set in a group

2. Oscillator circuit options

• Main clock

Option Circuit Conditions and notes

1. External clock

2. Ceramic oscillator

Note: There is no RC oscillator option.

• Sub-clock

Option Circuit Conditions and notes

1. Ports PE0 and PE1

2 Sub-oscillator

(crystal oscillator)

OSC1

Ceramic oscillator

Crystal oscillator

The input has Schmitt characteristics

OSC1

OSC2

DSB

Input data

XT1

XT2

3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option.

4. Port output type options

• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be

Option Circuit Conditions and notes

1. Open-drain output

2. Output with built-in pull-up resistor

Output data

Input data

DSB

Output data

Input data

DSB

The port P2, P3, P5, and P6 inputs have Schmitt characteristics.

The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor.

No. 5489-8/28

LC66P5316



• One of the following two options can be selected for P8, in bit units.

Option Circuit Conditions and notes

1. Open-drain output

DSB

Output data

2. Output with built-in pulldown resistor (CMOS output)

DSB

5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PC2/PC3, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to inputs.)

Option Circuit Conditions and notes

Output data

Input data

DSB

1. Normal port I/O circuit

Output data

Input data

DSB

When the open-drain output type is selected

When the built-in pull-up resistor output type is selected The CMOS outputs (PC) and the pull-up MOS outputs (P4) are distinguished by the drive capacity of the p-channel transistor.

2. Inverter I/O circuit

Output data

high

Input data

DSB

Output data

If this option is selected, the I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected.

high

Input data

DSB

No. 5489-9/28

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