SANYO LC66P2316 Datasheet

CMOS LSI

No. 5487

Preliminary

Overview

The LC66P2316 is an on-chip OTP PROM version of the LC6623XX Series CMOS 4-bit single-chip microcontrollers. The LC66P2316 is appropriate for program development and product evaluation since it provides identical functionality and pin compatibility with the LC662316A.

Features and Functions

• On-chip OTP ROM capacity of 16 kilobytes, and an on-

chip RAM capacity of 512 × 4 bits.

• Fully supports the LC66000 Series common instruction set (128 instructions).

• I/O ports: 36 pins

• DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications.

• 8-bit serial interface: one circuit

• Instruction cycle time: 0.95 to 10 µs (at 4.0 to 5.5 V)

• Powerful timer functions and prescalers — Time limit timer, event counter, pulse width

measurement, and square wave output using a 12-bit timer.

— Time limit timer, event counter, PWM output, and

square wave output using an 8-bit timer.

— Time base function using a 12-bit prescaler.

• Powerful interrupt system with 10 interrupt factors and 7 interrupt vector locations. — External interrupts: 3 factors/3 vector locations — Internal interrupts: 4 factors/4 vector locations

(Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts)

• Flexible I/O functions Selectable options include 20-mA drive outputs, inverter circuits, pull-up and open drain circuits.

• Optional runaway detection function (watchdog timer)

• 8-bit I/O functions

• Power saving functions using halt and hold modes.

• Packages: DIP42S, QIP48E (QFP48E)

• Evaluation LSIs: LC66599 (evaluation chip) + EVA800/850-TB662YXX2

LC66P2316

Four-Bit Single-Chip Microcontroller

with 16 KB of On-Chip OTP PROM

Package Dimensions

unit: mm

3025B-DIP42S

[LC66P2316]

1.78

4.25

0.51

min

1.15

SANYO: DIP42S

1.6

1.5 25

SANYO: QFP48E

13.8

15.24

5.1

max

3.8

0.15

0.1

2.70

(STAND OFF)

unit: mm

3156-QFP48E

1.614.0

17.2

3.0max

37.9

0.95 0.48

[LC66P2316]

17.2

14.0

1.0

1.5 36

1.5

1.0

1.5

112

0.35

0.8

15.6

0.25

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

22897HA (OT) No. 5487-1/27

Series Organization

LC66P2316

Type No.

LC66304A/306A/308A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66404A/406A/408A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66506B/508B/512B/516B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64A LC66354A/356A/358A 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66354S/356S/358S 42 4 K/6 K/8 KB 512 W QFP44M LC66556A/558A/562A/566A 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354B/356B/358B 42 4 K/6 K/8 KB 512 W DIP42S QFP48E LC66556B/558B/562B/566B 64 6 K/8 K/12 K/16 KB 512 W DIP64S QFP64E LC66354C/356C/358C 42 4 K/6 K/8 KB 512 W DIP42S QFP48E 2.5 to 5.5 V/0.92 µs LC662104A/06A/08A 30 4 K/6 K/8 KB 384 W DIP30SD MFP30S LC662304A/06A/08A/12A/16A 42 LC662508A/12A/16A 64 8 K/12 K/16 KB 512 W DIP64S QFP64E

LC665304A/06A/08A/12A/16A 48

LC66E308 42 EPROM 8 KB 512 W LC66P308 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E408 42 EPROM 8 KB 512 W LC66P408 42 OTPROM 8 KB 512 W DIP42S QFP48E

LC66E516 64 EPROM 16 KB 512 W LC66P516 64 OTPROM 16 KB 512 W DIP64S QFP64E

LC66E2108* 30 EPROM 8 KB 384 W LC66E2316 42 EPROM 16 KB 512 W

LC66E2516 64 EPROM 16 KB 512 W

LC66E5316 52/48 EPROM 16 KB 512 W LC66P2108* 30 OTPROM 8 KB 384 W DIP30SD MFP30S

LC66P2316* 42 OTPROM 16 KB 512 W DIP42S QFP48E LC66P2516 64 OTPROM 16 KB 512 W DIP64S QFP64E LC66P5316 48 OTPROM 16 KB 512 W DIP48S QFP48E

Note: * Under development

No. of

pins capacity

ROM capacity

4 K/6 K/8 K/12 K/16 KB

RAM

512 W DIP42S QFP48E

512 W DIP48S QFP48E

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC42S QFC48 with window with window

DIC64S QFC64 with window with window

DIC52S QFC48 with window with window

Package Features

Normal versions

4.0 to 6.0 V/0.92 µs

Low-voltage versions

2.2 to 5.5 V/3.92 µs

Low-voltage high-speed versions

3.0 to 5.5 V/0.92 µs

On-chip DTMF generator versions

3.0 to 5.5 V/0.95 µs

Dual oscillator support

3.0 to 5.5 V/0.95 µs

Window and OTP evaluation versions

4.5 to 5.5 V/0.92 µs

Window evaluation versions

4.5 to 5.5 V/0.92 µs

OTP

4.0 to 5.5 V/0.95 µs

No. 5487-2/27

Pin Assignments

LC66P2316

DIP42S

P20/SI0/A0

43/INV1O/A10

10OSC2 11V 12RES/VPP/OE 13PE0 14PE1 15TEST/EPMOD 16P33/HOLD 17P40/INV0I/A7 18P41/INV0O/A8 19P42/INV1I/A9 20 21P50/A11

1 2P21/SO0/A1 3P22/SCK0/A2 4P23/INT0/A3 5P30/INT1/A4 6P31/POUT0/A5 7P32/POUT1/A6 8V 9OSC1

LC66P2316

QFP48E

42 P13/D7 41 P12/D6 40 P11/D5 39 P10/D4 38 P03/D3 37 P02/D2 36 P01/D1 35 P00/D0 34 PD3/INV3O 33 PD2/INV3I 32 PD1/INV2O 31 PD0/INV2I 30 PC3/DASEC 29 PC2/CE 28 P63/PIN1 27 P62/DT 26 P61 25 P60/ML 24 P53/INT2/TA 23 P52/A13 22 P51/A12

P02/D2

P01/D1

P00/D0

PD3/INV30

PD2/INV31

PD1/INV20

PD0/INV21

PC3/DASEC

PC2/CE

P63/PIN

P62/DT

25 37P03/D3 38P10/D4 23 P60/ML 39P11/D5 22 P53/TA 40P12/D6 21 P52/A13 41P13/D7 20 P51/A12 42NC 19 NC 43NC 18 NC 44P20/SI0/A0 17 P50/A11 45P21/SO0/A1 16 P43/INV10/A10 46P22/SCK0/A2 15 P42/INV11/A9 47P23/INT0/A3 14 P41/INV00/A8 48P30/INT1/A4 13 P40/INV01/A7

P31/POUT0/A5

LC66P2316

P32/POUT1/A6

OSC1

OSC2

/OE

RES/V

PE0

PE1

TEST/EPMOD

24 P61/DP

P33/HOLD

Top view

We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).

No. 5487-3/27

LC66P2316

Usage Notes

The LC66P2316 was created for program development, product evaluation, and prototype development for products based on the LC6623XX Series microcontrollers. Keep the following points in mind when using this product.

1. After a reset The RES pin must be held low for an additional 3 instruction cycles after the oscillator stabilization period has elapsed. Also, the port output circuit types are set up during the 9 instruction cycles immediately after RES is set high. Only then is the program counter set to 0 and program execution started from that location. (The port output circuits all revert to the open-drain type during periods when RES is low.)

min

OSC

RES

At least 10 ms

Oscillator stabilization 

At least 3  instruction 

Program execution (PC)  

Port output type

Open drain

Option switching period

9 instruction  cycles

Location 0Location 

Option specification

2. Notes on LC6623XX evaluation The high end of the EPROM area (locations 3FF0H to 3FFFH) are the option specification area. Option specification data must be programmed for and loaded into this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the mask ROM.

3. Mounting notes Due to structural considerations, Sanyo is unable to fully test one-time programmable products. Therefore, the user must apply the screening procedure described on page 20 to these products.

4. Use the following procedure when ordering ROM through the Sanyo PROM writing service. (Note that this is a forfee service.)

• If ordering one-time programmable and mask ROM versions at the same time:

The customer must provide the EPROM for the mask ROM version, the order forms for the mask ROM version, and the order forms for the one-time programmable version.

• If ordering only the one-time programmable version:

The customer must provide the EPROM and the order forms for the one-time programmable version. The last section of the EPROM (locations 3FF0H to 3FFFH) is the option specification area, and the option specification data must be written to this area. The Sanyo specified cross assembler for this product is the program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the actual capacity of the mask ROM.

5. Differences between this product and the mask ROM version: Carefully read the sections on the following pages that describe these differences.

No. 5487-4/27

LC66P2316

Main differences between the LC66E2316, LC66P2316, and LC6623XX Series

Item LC6623XX Series (mask version) LC66E2316 LC66P2316

Differences in the main characteristics –30 to +70°C +10 to +40°C –30 to +70°C

• Operating temperature range

• Operating supply voltage/operating frequency (cycle time)

• Input high-level current (RES) Maximum: 1 µA (normal operation and halt mode) (normal operation and halt mode)

• Input low-level current (RES) Maximum: 1 µA Typical: 100 µA Typical: 100 µA

• Current drain (Operating at 4 MHz) (Halt mode at 4 MHz) Typical: 10 nA, maximum: 10 µA* Typical: 10 nA, maximum: 10 µA* (Hold mode)

Port output types at reset

Package

Note: * Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after

switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also not that a current of about 100 µA flows from the RES pin when it is low. This increases the hold mode current drain by about 100 µA.

3.5 to 5.5 V/0.95 to 10 µs 4.5 to 5.5 V/0.95 to 10 µs 4.0 to 5.5 V/0.95 to 10 µs Typical: 10 µA Typical: 10 µA

Hold mode: 1 µA maximum Hold mode: 1 µA maximum

Typical: 10 nA, maximum: 10 µA

The output type specified in the options

• DIP42S • DIC42S window package • DIP42S

• QFP48E • QFC48 window package • QFP48E

Larger than that for the mask versions Larger than that for the mask versions

Open-drain outputs Open-drain outputs

See the data sheets for the individual products for details on other differences.

System Block Diagram

RES

TEST OSC1 OSC2 HOLD

ML DT

SYSTEM

CONTROL

DTMF

GEN.

RAM STACK

(512W)

FLAG

SP E A

PRESCALER

D P Y

ALU

MPX TIMER0 SERIAL I/O 0

MPX

INTERRUPT

CONTROL

MPX

TIMER1

P0 P1 P2 P3 P4 P5 P6

OTPROM

16KB

INV

EPROM

control

POUT0 SI0 SO0 SCK0

INT0

INT1. INT2

PIN1. POUT1

xO INVxI

(x=0 to 3)

A0 to A13 D0 to D7

CE DASEC

Vpp/OE EPMOD TA

No. 5487-5/27

Pin Function Overview

LC66P2316

Pin I/O Overview Output driver type Options

P00/D0 P01/D1 P02/D2 P03/D3

P10/D4 P11/D5 P12/D6 P13/D7

P20/SI0/A0 P21/SO0/A1

P22/SCK0/

P23/INT0/A3

P30/INT1/A4 P31/POUT0/

P32/POUT1/

I/O ports P00 to P03

• Input or output in 4-bit or 1-bit units

• P00 to P03 support the halt mode

I/O

control function (This function can be specified in single-bit units.)

• Used as data pins in EPROM mode

I/O ports P10 to P13

• Input or output in 4-bit or 1-bit units

I/O

• Used as data pins in EPROM mode

I/O ports P20 to P23

• Input or output in 4-bit or 1-bit units

• P20 is also used as the serial input SI0 pin.

• P21 is also used as the serial output SO0 pin.

• P22 is also used as the serial clock

I/O

SCK0 pin.

• P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input.

• Used as address pins in EPROM mode

I/O ports P30 to P32

• Input or output in 3-bit or 1-bit units

• P30 is also used as the INT1 interrupt request.

• P31 is also used for the square wave output from timer 0.

I/O

• P32 is also used for the square wave and PWM output from timer 1.

• P31 and P32 also support 3-state outputs.

• Used as address pins in EPROM mode

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pull-up MOS or Nch OD output

• Output level on reset

• Pull-up MOS or Nch OD output

• Output level on reset

CMOS or Nch OD output

State after a Standby mode

reset operation

Hold mode:

High or low (option)

Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output off

Hold mode: Output off

Halt mode: Output retained

P33/HOLD

P40/INV0I/

P41/INV0O/

P42/INV1I/

P43/INV1O/

A10

Hold mode control input

• Hold mode is set up by the HOLD instruction when HOLD is low.

• In hold mode, the CPU is restarted by setting HOLD to the high level.

• This pin can be used as input port P33

along with P30 to P32.

• When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied.

I/O ports P40 to P43

• Input or output in 4-bit or 1-bit units

• Input or output in 8-bit units when used in conjunction with P50 to P53.

• Can be used for output of 8-bit ROM

I/O

data when used in conjunction with P50 to P53.

• Dedicated inverter circuit (option)

• Used as address pins in EPROM mode

• Pch: Pull-up MOS type

• CMOS type when the inverter circuit option is selected

• Nch: Intermediate sink current type

• Pull-up MOS or Nch OD output

• Output level on reset

• Inverter circuit

Hold mode:

• High or low (option)

• Inverter I/O is set to the output off state.

Port output off, inverter output off

Halt mode: Port output retained, inverter output continues

Continued on next page.

No. 5487-6/27

Continued from preceding page.

LC66P2316

Pin I/O Overview Output driver type Options

I/O ports P50 to P53

• Input or output in 4-bit or 1-bit units

P50/A11 P51/A12 P52/A13

P53/INT2/TA

P60/ML

P61

P62/DT

P63/PIN1

PC2/CE

PC3/DASEC

PD0/INV2I

PD1/INV2O

PD2/INV3I

PD3/INV3O

PE0 PE1

OSC1

OSC2

• Input or output in 8-bit units when used in conjunction with P40 to P43.

• Can be used for output of 8-bit ROM

I/O

data when used in conjunction with P40 to P43.

• P53 is also used as the INT2 interrupt request.

• Used as address pins in EPROM mode

I/O ports P60 to P63

• Input or output in 4-bit or 1-bit units

• P60 is also used as the melody output ML pin.

I/O

• P62 is also used as the tone output DT pin.

• P63 is also used for the event count input to timer 1.

I/O ports PC2 to PC3

• Output in 2-bit or 1-bit units

• PC3 is also used as the control CE and DASEC pin in EPROM mode.

Dedicated input ports PD0 to PD3

Dedicated inverter circuits (option)

Dedicated input ports

System clock oscillator connections

When an external clock is used, leave

OSC2 open and connect the clock signal to OSC1.

• Pch: Pull-up MOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pch: CMOS type

• Nch: Intermediate sink current type

• When the inverter circuit option is selected.

• Pch: CMOS type

• Nch: Intermediate sink current type

• Pull-up MOS or Nch OD output

• Output level on reset

CMOS or Nch OD output

Inverter circuits

Ceramic oscillator or external clock selection

State after a Standby mode

reset operation

Hold mode: Output off

High or low (option)

Halt mode: Output retained

Hold mode: Output off

Halt mode: Output retained

Hold mode: Port output off

Halt mode: Port output retained

Normal input Inverter I/O goes to the output off state.

Option selection

Hold mode: Inverter Output off

Halt mode: Inverter output continues

Hold mode: input disabled

Halt mode: inputs accepted

Hold mode: oscillator stops

Halt mode: oscillator continues

System reset input

RES/V

TEST/

EPMOD

Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD.

CMOS output: Complementary output. OD output: Open-drain output.

• When the P33/HOLD pin is at the high level, a low level input to the RES pin

will initialize the CPU.

• This pin is also used as the VPP/OE pin in EPROM mode.

CPU test pin This pin must be connected to V during normal operation. Setting this pin

to +12 V switches the LC66P2316 to EPROM mode.

Power supply pins

No. 5487-7/27

LC66P2316

User Options

1. Port 0, 1, 4, and 5 output level at reset option The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options.

Option Conditions and notes

1. Output high at reset The four bits of ports 0, 1, 4, or 5 are set in a group

2. Output low at reset The four bits of ports 0, 1, 4, or 5 are set in a group

2. Oscillator circuit options

• Main clock

Option Circuit Conditions and notes

1. External clock

2. Ceramic oscillator

Note: There is no RC oscillator option.

OSC1

Ceramic oscillator

The input has Schmitt characteristics

OSC1

OSC2

3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option.

4. Port output type options

• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be

selected individually from the following two options.

Option Circuit Conditions and notes

1. Open-drain output

2. Output with built-in pull-up resistor

Output data

Input data

DSB

Output data

Input data

DSB

The port P2, P3, P5, and P6 inputs have Schmitt characteristics.

The CMOS outputs (ports P2, P3, P6, and PC) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the p-channel transistor.

No. 5487-8/27

LC66P2316



5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PD0/PD1, and PD2/PD3.

Option Circuit Conditions and notes

Output data

1. Normal port I/O circuit

2. Inverter I/O circuit

Input

Output

DSB

Input data

Output data

Input data

Output data

high

Input data

Output data

high

Input data

When the open-drain output type is selected

When the built-in pull-up resistor output type is selected

If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected.

No. 5487-9/27

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