The following figure shows a basic block diagram of the FC3G2 chassis. This
chassis is constructed by the folowing ICs :
AN17820B, IC001, for the audio output circuit
LA76818A, IC201, for the IF, video, chroma de-modulation and deflection circuit
LA7642NM-TLM-E, IC281, for the SECAM decoder circuit.
NJW1142M, IC3701, for audio processor
LA78041, IC501, for the vertical deflection output circuit
LC863448W-52F1-TLM, IC801, for the CPU (system control unit) of FC3G2
AT24C16A-10PI-2.7, IC802, for the control memory IC.
MM1188XS & TC4053BF-TP1, IC1401 & IC 1501, for video selector.
A1901A
RECEIVER
D1910
LED
FRONT
CONTROL
KEYS
SP902
SP901
REAR
MONITOR
TERMINAL
REAR
INPUT
TERMINAL
FRONT
INPUT
TERMINAL
RC
SW1901 ~
SW1906
S-VIDEO IN (FROM S-TERMINAL)
R-OUT
L-OUT
V
L
OUT
R
V
AV1
L
R
V
AV2
L
R
S-TERMINAL
RC-IN
ON-TIMER
POWER
KEY-IN
IC001
AUDIO AMP.
8
12
2
R
6
L
VIDEO MONITOR OUT
AUDIO MONITOR OUT(LEFT)
AUDIO MONITOR OUT(RIGHT)
AV1 L-IN
AV1 R-IN
AV2 L-IN
AV2 R-IN
IC1401
VIDEO
SELECTOR
9
AV1 VIDEO IN
AV2 VIDEO IN
1
C-IN
6
+
Y-IN
7
3
AV2/S-INPUT
28
32
31
IC801
CPU
12
11
5
26
2
29
CONTROL/
SURROUND
3
28
4
AV OUT
8
AV1/AV2
(FROM CPU PIN-25)
C-IN
Y-IN
IC3701
(L-TV-L)1/30
AUDIO
3
4
19
20
21
1/2
24
26
10
21
13/14
SDA/SCL
(FROM CPU)
SDA
5
SCL
6
OSD R-OUT
OSD G-OUT
OSD B-OUT
SDA/SCL
TV/AV OUT
AV1/AV2 OUT
L-OUT
R-OUT
TV-AUDIO
S-INPUT
IC802
EEPROM
OUT (TV)
VIDEO-IN
Y-IN
R-IN
G-IN
B-IN
VIDEO
AV,Y IN
AV IN
TV IN
TV IN
AV-IN
Y-IN
A101
TUNER
SDA/SCL
IC201
IF/VIDEO/
CHROMA
11/12
5/6
14
15
2
1
5
3
13
12
19
16
20
21
23
46
27
42
TV
1
AUDIO
OUT
44
INT.VIDEO IN
(C-IN)
VIDEO MONITOR OUT
IC1501
VIDEO SELECTOR
11
9
10
IF IN
R-OUT
G-OUT
B-OUT
VERT.OUT
HORIZ.OUT
MONITOR
15
OUT
TV/AV OUT
4
Y-OUT
AV-OUT
14
Y-OUT
TV/AV (FROM CPU PIN-24)
X161
SAW
FILTER
Q431
H-DRIVE
CRT UNIT
1
T431
H-DRIVE
TRANS.
IC701
TRIPLE VIDEO
OUTPUT AMP.
R
1
9
G
2
8
B
3
7
IC501
VERT./DEF.
Q432
H-OUT
PCC
CIRCUIT
Q461-Q462
140V
24V
11V
9V
R
G
B
HEATER
POWER SUPPLY CIRCUIT
5
36V
9V
5V
T471
FBT
FBT
HORIZ. DEF.
VERT. DEF.
MAIN SOUND AMP.
IC201, AUDIO CTL.
CPU, EEPROM
FOCUS
SCREEN
TUNER
L902
CRT
HV
DY
HV
Figure of FC3G2 block diagram
3
Training Manual FC3G2 Chassis
Page 4
2. CPU (System Control)
The following firgure shows a block diagram of the CPU peripheral circuit. CPU that
use for FC3G2 is AC5G2 CPU.
TERMINAL ASSIGNMENT (AC5G2 CPU)
LC863448W-52F1-TLM (ROM:48Kbytes)
BUS SDAÅÆ1 P10/SDA0 * P03 36 Å Status input(factory)
Bilingual output Å 16 P30 B 21 Æ OSD Blue signal output
(Low:S-1,High:S-2)
V-sync signal input Æ 17 VS G 20 Æ OSD Green signal output
H-sync signal input Æ 18 HS R 19 Æ OSD Red signal output
NOTE : * N-ch.open drain output (Vout max.+5V)
4
Training Manual FC3G2 Chassis
Page 5
The following table shows pin description of CPU.
Port Description Table
PIN Port
Name
1 SDA0 IIC DATA I/O Nch-OD No Hz BUS IC
2 SCL0 IIC CLOCK O Nch-OD No Hz BUS IC
3 SDA1 BUS DATA I/O Nch-OD No Hz EEPROM
4 SCL1 BUS CLOCK O Nch-OD No Hz EEPROM
5 VSS GND - -
6 XT1 X’tal input I - - 32.768KHz
7 XT2 X’tal output O - -
8 VDD +5V I - -
9 AN4 SECAM Killer input I Nch-OD No - High: SECAM
10 AN5 AFT IN I - No - AFT signal
11 AN6 S-Terminal input I Nch-OD No - Low: S-In
12 AN7 Panel keys input I - No - Panel keys
13 RES RESET I - - Reset:Low
14 FILT FILTER for PLL O - -
15 CVIN CV input I - - (Composite Video)
16 P30 Bilingual output O - yes -
17 VS V-sync signal input I - - Active Low
18 HS H-sync signal input I - - Active Low
19 R OSD Red output O C-MOS L Active High
20 G OSD Green output O C-MOS L Active High
21 B OSD Blue output O C-MOS L Active High
22 BLNK OSD Blanking output O C-MOS L Active High
23 P31 L/R or L/L output O C-MOS Hz Low:L/R
24 P32 TV/AV123 output O C-MOS yes Hz Option TV/AV1/AV2/AV3
25 P70 50/60Hz output O C-MOS No Hz Low:60Hz
26 P71 TV/AV123 output O C-MOS No Hz Option TV/AV1/AV2/AV3
27 P72 Power failure input I Nch-OD No Hz Low:fail
28 P73 Remotecontrol signal I Nch-OD No Hz Active High
29 P14 Sound Mute output O C-MOS No Hz High:Mute on
30 PWM2 Volume PWM output O C-MOS No Hz
31 P16 Power on/off output O C-MOS No Hz High:Power on
32 P17 On timer LED output O C-MOS No Hz Low:timer on
33 P00 VIF-M O C-MOS No Hz High:NTSC
34 P01 Bass expander I/O Nch-OD No Hz High:BASS on
35 P02 ACK O C-MOS No Hz Factory:Low
36 P03 Status input I Nch-OD No Hz Factory:Low
Use
I/O
Output
Structure
Input
p-up R
Reset
Notes
Note : Hz = High impedance
5
Training Manual FC3G2 Chassis
Page 6
≪CPU Specification outline≫
This tuning system is equipped with the F/S tuning system for AC5G2 chassis. It has the
following specification.
(1) Monaural, Simple AV Stereo & AV stereo Function
(2) Maximum 256 Positions. Optional 100 or 256 Position (E
PROM : 16k bit for 256
Pos)
① The direct tuning function can be work by pressing “[0]~[9] key” and “[-/--] key”
② The sequential tuning function can be work by pressing [POS -] and [POS +]
key
③ The alternate tuning function can be work by [Alt] key
(3) PRESET function [Automatic Tuning/Semi-Auto Tuning/Manual Tuning]
Plug & Play function
(4) Channel Swap function & Channel Skip function
(5) Bilingual system
(6) Option system
A. Memory options
① Color system selection : Five kinds
② Sif system selection : Six kinds
③ AV input option : AV only or AV1/AV2 or AV1/AV2/AV3
④ BASS EXPANDER selection : with or without
⑤ SURROUND selection : with or without
B. Special function (Dealer) options
① Tuning Lock : on or off
② Volume Lock : on or off
③ AV start : on or off
④ Music mode : on or off
(9) OSD is a multi-color display (the R/G/B output).
(10) OFF timer function(30/60/90/120 minutes)
(11) ON timer function (10 minutes ~ 24 hours)
6
Training Manual FC3G2 Chassis
Page 7
(12) Auto shut off timer function (10 minute)
(13) FACTORY KEY(R/C DATA code “80h”~ “DFh”)
(14) Service mode (Adjustment of bus data : one chip and audio IC etc.)
(15) PWR Error Detection Function
2
(16) I
C bus correspondence (One chip : LA76818)
(17) EEPROM (8k bit for 100 position, 16k bit for 256 position)
(18) GAME (Air Tennis)
(19) Six Language OSD
① English
② Thai
③ Arabic
④ Russian
⑤ French
⑥ Bahasa Indonesia
(20) White Tone user adjustable
7
Training Manual FC3G2 Chassis
Page 8
2-1 A-D Key Identification Circuit.
The key identification circuit used in this chassis uses a switched resistive ladder
network in a A-D conversion circuit to generate and send a voltage to the CPU when a
key pressed. The CPU uses this voltage to determine which key was pressed. This
resistive circuit eliminates the need for encoder/decoder devices, simplifying design
and adding to the reliability of the TV.
The table shows the voltage input to CPU pin 12, when a given key pressed.
Front Control Key Input
1) Action
Front panel SW is decied by the input voltage of A/D port (12pin).
3. Action
* The Key scan will be performed every 20 msec. It judges whether the key was
pressed or not .
* When the Key signal is match within two consecutive time at intervals of 20msec ,
the key is decided.
* The Key scan priority is K6 -> K1.
* The high priority key has pushed, other keys cannot operate
.
4. S-input Option
* The “KEY OFF” voltage distinguishes availability of S-Terminal.
* The “KEY OFF” voltage range is divided into two kinds.
1. When KEY OFF voltage is less than 0.51V, it is decide as an S-terminal-less
model.
2. When KEY OFF voltage is from 0.51 to 1.13V, it is decide as S-terminal model.
<The option selection method >
* Judgment is always (20 ms) performed. (agrement with two consecutive time
* This option is decided only in KEY OFF. An option does not change when
K1 ~ K6 was inputted.
□Bus data of LA76818
VIDEO
SW
OFF 1
(S term less)
OFF 2
(S term)
Address TV AV TV AV
14H DAO0 1 1 1
9
Training Manual FC3G2 Chassis
Page 10
2-2 Memory Option
This chassis uses the option function to determine several different specifications of the
TV set. The CPU determines the specification of TV by setting the data of memory
option.
Following table shows the option function of the CPU.
The SERVICE MODE NO From 83 to 96 is EEPROM MEMORY OPTION.
《SERVICE MODE NO 83》
* ”STEREO” OR “MONO” OPTION
Bit OPTION
0 MONO
1 Simple AV Stereo
2,3 AV Stereo
※ AV STEREO : Control by Audio IC (NJW1142)
Simple AV : Control By CPU PWM port
MONO : Control by Volume ATT register of One chip IC.
《SERVICE MODE NO 84》
* VOLUME TABLE 1, 2 SWITCHING
Bit VOL TABLE
1 VOLUME TABLE2
0 VOLUME TABLE1
※ Refer to “volume.doc”.
《SERVICE MODE NO 85》
* MPP FUNCTION option
Bit
1 MPP ON
0 MPP OFF
* M.P.P. function memorize
VOLUME/BRIGHT/CONTRAST/SHARPNESS/TINT for every channel
(1~30 POS).
* Refer to 121Multi_PP_Level.DOC
《SERVICE MODE NO 86》
* TUNER option
Bit
1 Matsushita Tuner
0 ALPS Tuner
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Training Manual FC3G2 Chassis
Page 11
《SERVICE MODE NO 87》
* AV1, AV2, AV3 Option
Bit
0
1
2-3
TV→AV→TV
TV→AV1→AV2→TV
TV→AV1→AV2→AV3→TV
《SERVICE MODE NO 91》
《Description》
* A color system option is changed by a setup in Service Mode No. 91 OPT COL.
* A color system option is shown below. There are five kinds of color systems.
* COLOR SYSTEM OPTIONS Tabel
SVS
data
0,1 NO SYSTEM (No Display) PAL only same as the TV MODE.
2 VMT SYSTEM (No Display) PAL + NTSC only
3 CHINA,
《The option selection method》
* An option is changed by Service Mode NO. 91 OPT COL.
* The Option check will be carry out on RESET START.
* A judgment is performed only once after RESET START.
《SERVICE MODE NO 92》
《Description》
* A SIF system option is changed by Service Mode.
* A SIF system option is shown below. There are six kinds of SIF systems.
* The bilingual operation differs from the other SIF system option
※Bilingual specification is displayed as S-1 and S-2. The other modes, each SIF
system name is displayed.
11
Training Manual FC3G2 Chassis
Page 12
《The option selection method》
* An option is changed by Service Mode Data No.92 OPT SIF
* The voltage is read in a RESET START after operation.
* This judgment operation carry out only a RESET START.
《SERVICE MODE NO 93》
* BASS EXPANDER FUNCTION option
Bit Display
0 No Display
1 “BASS”
2 “BASS EXPANDER”
3 “WOOFER”
* If Bass Exp Option is ‘0’ on MONO and Simple AV mode then there will be No AUDIO
Menu on MAIN Menu
* This function is available only when using Audio Control IC.
* In AV Stereo Mode While BASS EXPANDER ON, AUDIO IC of Bass/Treble DATA is
set as : Bass : +10 dB, Treble : +6 dB
* In MONO & Simple AV Stereo Mode if BASS EXPANDER ON, Pin 34 will be “High”
《SERVICE MODE NO 94》
* SURROUND option
Bit
1 Surround
0 No Surround
《SERVICE MODE NO 95》
* SUB - BASS/TREBLE adjustment of AudioControlIC (NJW1142)
Bit
0 BASS TREBLE Gain –3 db
1 BASS TREBLE Gain 0 db
2,3
BASS TREBLE Gain +3 db
* This function available only when using Audio Control IC.
《SERVICE MODE NO 96》
* AGC setting AudioControlIC (NJW1142)
Bit
0 AGC OFF
1 AGC ON Level= 600 Mv
2 AGC ON Level= 500 mV
3 AGC ON Level= 300 mV
* This function available only when using Audio Control IC
12
Training Manual FC3G2 Chassis
Page 13
2-3 Power On/ Stand-by circuit.
Power on / stand-by
The power on/stand-by signal is output from pin 31 of the CPU.
When the stand-by mode is selected the voltage of pin 31 changes from Hi(5V) to
Low(0V) to turn off Q681and Q652. Q652 turning off causes Q653 and
Q654 to turn off. +24V supply for vertical and horizontal output circuit, +9V supply
for IF/VIDEO/Chroma circuit and +5V for tuner circuit are all cut off, resulting in the
TV set going into the stand-by mode.
When the TV is switched back into the power on mode, Q681 and Q652 are turned
on and the relevant voltage are supplied back to each circuit.
Q681
TO HEATER PROTECT
& HOLDDOWN CIRCUIT
TO VERTICAL
DEFL. CIRCUIT
(FOR PROTECTION)
IC681
TO CPU
TO IC201, IC281
AUDIO PROCESSOR,
AV SWITCH & CRT UNIT
TO VIDEO PROCESSOR,
Q652
TO HOR & VER,
DEFLECTION CIRCUIT
TUNER & DEFLECTION
TO AUDIO AMP. IC
TO TUNER AND
HOR DEFL. CIRCUIT
Fig. of Power On/Stand by Circuit
2-4 Protection circuit
This chassis employs two kinds of protection circuit, one controlled by software through
the CPU and the other by hardware.
. Protection circuit (software)
The protection circuit is provided to disable the operation of the TV set in case of a
circuit malfunction. When an abnormality occurs during TV reception it causes pin 31 of
the CPU to go continually Low (less then 0.8V) for about one second. The CPU detects
that circuit malfunction has occurred and cut off the signal output to Q681.
. Protection circuit (hardware)
When a power failure is detected by diodes D655, D690 and D468, this protection circuit
operates causing the power oscillation to stop. If one of above diode is turned on, the
voltage of Q661-emitter decreases, and it turns on completely. Photo-coupler D610 is
driven by this and generates a current which drives Q625 on. As a result, the operation
of the power oscillation circuit is stopped. Under normal circumstances these parts,
D610, Q661, D661, R661, VR661, R662 are operating as the error detection and
regulation circuit for +130V power supply.
13
Training Manual FC3G2 Chassis
Page 14
AT3
Q690
AH
R694
5.6K
C691
35EM47
1
4
X
4
5
6
X
7
1
2
2400030
3
23
14
15
12
16
13
17
L652
BA178M05T:
MC78M05CT:
UPC78M05AHF:
L78M05CV
C657
1000KK470
(CRD:NH)
L653
J
FE301-1L43:
RU4YXLF-L1
X
L654
J
X
J
D653
C658
1000KK470
(CRD:NH)
YG901C2-LB
R646
J
D654
D691
AA
D692
EU1
C656
1000KK
470(CRD:NH)
D652
RN1Z
IC681
123
10EM470
R658
X
C643
25EM
1000T
C654
25EM
3300
C655
1000KK680
(CRD:NH)
L651
J
D651
RU3AM
160EM
220XJ
R693
1/16GJ
10KC
R653
1FJ5.6
C652
35EM
470T
5VRC
C681
R654
15K
X
X
C651
R661
DJ100K
VR651
R3D6222NJ:
R3D7222NJ
R652
33K
JP653
1/16GZ0C
Q653
X
11V
AUDIO
C653
PM1
JP631
DJ10K
R691
1/16GJ
47KC
R692
1/16GJ
20KC
R645
R655
R659
X
J
R662
1/16GJ
3.9KC
X
Q661
AH
EM2.2
CT
JP652
X
2SB1565E
R657
DJ3.9K
R668
2SJ12
R669
2SJ
12
D659
X
TP-130
X
JP633
X
D661
MTZJ6.2C:
RD6.2EB3:
DZXLBZA6.2C
C690
R690
1/16GJ
47KC
Q652
1SJ270
MTZJ10B:
RD10EB2:
DZXLBZA10B
R663
150K
24V
R656
D664
16EM220LBWA
R665
DJ12K
D690
1SS355
AD
Q693
Q654
2SD1913
(QRA:RRA)
C664
16EM220:
B1
130V
R664
1SJ27K
C639
X
PROTECT
R697
1/16GJ
47KC
9V
C665
16EM470
Q651
R695
DJ6.8K
R696
1/16GJ
4.7KC
C693
16EM47
Q662
AC
D655
AA
AD
R651
1K
Q681
AE
R682
1/16GJ
560KC
D693
AA
D662
MTZJ
6.8A:
DZXLB
ZA6.8A
R681
22K
R672
12K
R660
11V
X
L-ST
H-ON
R666
1/16GJ
22KC
R667
1/16GJ
10KC
Q663
R671
22K
AH
D671
AA
C663
EM0.22
R673
1/16GJ
560KC
2-5 AFT
* Basic operation of tuning
(Common operation : Direct tuning / Sequential tuning / Alternate tuning)
(1) The tuned-in position is memorized to E2PROM as a last position.
(2) The transient MUTE is performed at the time of tuning. ( direct / alternate tuning.)
(3) A position OSD is displayed for 5 seconds.
(4) Digital AFT operation is performed after 240ms.
* This tuning system is F/S tuning, thus digital AFT is unnecessary in principle at least.
But, AFT is carrying out for the following reasons.
(1)If some hundreds of kHz RF shifts by move etc.,the claim will occur that NICAM
and TEXT do not operate.
(2)The old chassis of F/S tuning system shown below that has the digital AFT
function. F/S tuning system model : EB1/EB3/WB2A/WB2B/AB3A/AB3B.
(3)The V/S tuning system quality standards are satisfied that RF change can be
corrected to ±800kHz.
(In case of the China national standard, it is necessary to receive to ±1MHz.)
14
Training Manual FC3G2 Chassis
Page 15
《Digital AFT》
* Digital AFT is substitute of the “hardware AFT” inside a tuner.
In order to set the tuning voltage as the optimal value, center frequency is searched
from the starting frequency
which deducted 1MHZ from the local frequency
memorized by E2PROM.
However, this digital AFT is terminated when rise/down processing of tuning voltage
becomes 100 times.
- LOCAL frequency is controlled by AFT voltage of the following table.
direction AFT Vol.
UP Vol. 3.5v-
CENTER Vol. 2.0v-3.0v
DOWN Vol. -1.5v
①The starting frequency data is outputed to Tuner. Wait for 240msec. → If AFT voltage is less than [ 1.5V ]. Jump to ④
→ Other, To the next.
②Frequency is raised by 500KHz/40msec (Tab.1-A) until AFT voltage becomes more
than UP voltage (3.5v).
- In case of following, Local frequency is set to an EEPROM data. Jump to ⑤
- Tuning data raised to +1.5MHz on the way,
- The digital AFT was performd 100 times or more,
③Frequency is raised by 100KHz/40msec (Tab.1-B) until AFT voltage becomes more
than DOWN voltage (1.5v).
- If a synchronized signal is lost on the way, it will return to ②
- In case of following, Local frequency is set to an EEPROM data. Jump to ⑤
1. Tuning data raised to +1.5MHz on the way,
2. The digital AFT was performed 100 times or more.
④Frequency is raised by 50KHz/40msec (Tab.1-C) until AFT vol becomes more than
CENTER voltage (2.0v).
- If a synchronized signal is lost on the way, it will return to ②
- In case of following, Local frequency is set to an EEPROM data. Jump to ⑤
1. Tuning data raised to +1.5MHz on the way,
2. The digital AFT was performd 100 times or more,
⑤Digital AFT complete.
Tab. 1 Digital AFT tuning speed
A B C
high speed up mid speed up low speed down
500KHz/40msec 100KHz/40msec 50KHz/40msec
15
Training Manual FC3G2 Chassis
Page 16
* Input
(1) Detection of the synchronized signal of TV/AV.
Read register of the 1 chip IC (LA76818)
Status(D1 bit)
Judgment
1 Non - sign
0 sign
- It is determined by two continuation correspondence (20ms interval).
(2) Detection of an AFT signal uses a A-D input port (10pin).
- The AFT signal (0V-9V) outputted from an AFT circuit that is changed to 0V-5V by
resistance.
- This A-D input terminal port which consists of a 6-bit D-A conversion and a
comparator.
- Tuner always output AFT voltage of the TV signal, even if AV.
- An AFT signal is judged as follows:
The voltage level is read every 10ms.
↓f1
←3.5v 3.5v→ center freq
AFT signal ←2.0v
1.5v→
↑f2
Synchronized signal
(Attention)
The necessary condition of the sensitivity of an AFT signal is f2-f1 > 50kHz.
Input Vol. Level Judgment
L(0v~1.5v)
M(2.0v~3.0v)
H(3.5v~5v)
TU Vol. down
TU Vol. center
TU Vol. up
《Output》
* IIC bus is used for PLL control. (Matsushita PAL standardization F/S tuner)
* PLL control (transmission of data) is not performed in standby mode.
(the power voltage is not supplied to a PLL circuit)
* PLL control is not performed during bus open mode.
* PLL control register is refreshed every 20ms.
VL < 178.25MHzVH
②Classification of VH and UHF
Z33 ch+4MHz(466.25MHz) is a boundary.
VL < 466.25MHz UHF
17
Training Manual FC3G2 Chassis
Page 18
2-6 Horizontal/Vertical pulse input
The vertical and horizontal pulses from deflection circuits are input to pins 17 and 18 in
order to synchronize the ON Screen Display.
The vertical pulse is supplied from pin 3 of IC501 through the inverter circuit Q871.
The horizontal pulse is supplied from pin 5 of the fly back transformer through the
inverter circuit Q881 .
If one of these pulses is not supplied to the CPU, the on-screen display cannot be
displayed.
5VRC
R871
1/16GJ
10KC
Q871
AH
R870
1/16GZ0C
IC801
QXXAVC305P
14
FILT
15
C-CAPTION
BILINGUAL
16
17
VS
1819
HS
R877
X
R877TM
1/16GJ
3.3KC
R878
X
MN/ST
BLK
Q881
AH
B
G
R
1/16GJ
3.3KC
C835
EM1
23
22
21
20
1/16GJ
3.3KC
R882
R881
R872
27K
R883
1/16GJ
33KC
R510
10K
R511
10K
C880
KK3300GQ
5V-1
C510
16EM22
(:LBWAJ)
V-SYNC
H-SYNC
IC501
LA78041
C511
KK0.01
GQ
76
R512
DJ
470
C517
35EM
220
:ERA15-02
:ED0448
R355
DJ10K
INPUT
D512
EM01Z
OUTPUT
STG VCC
C491
500KK
680A
D485
EU1
7SJ6.8VC
JP435
X
B1
130V
R488
1/2FJ1
R435
OUTPUT
5
R519
100
H-OUT
JP407
J
JP408
C437
250GJ
0.47
INPUT
4
X
JW1
1
GND
JP409
JP412
J
T471-H4
JP410
J
GND
VCC
C518
KK3300
T471
L40B16000
T471A
X
INVERT
R503
C521
35EM
2200
(:LBWA)
T471-H8
JP403
J
HEATER
LOW B
X
JP501
J
2400010
24V
JW37
1
JP503
J
B4S10B00100:
S10B1370N
JW36
1
D501
J
HV
FO
SC
7
11
T471-H6
2400010
64
64
PUMP UP
321
C520
100FK0.1
(D:BE)
T471-H1
2400030
1
1
T471-H10
2400010
10
10
VIDEO
T471-H2
2400030
2
2
+B
C437A
X
J
AFC
2400010
2400010
53
53
T471-H5
SW501
R501
2SJ1K
18
Training Manual FC3G2 Chassis
Page 19
2-7 Service mode
19
Training Manual FC3G2 Chassis
Page 20
20
Training Manual FC3G2 Chassis
Page 21
21
Training Manual FC3G2 Chassis
Page 22
3. IF /Video/Chroma/Deflection
The following figure shows a block diagram of the IF/Video/Chroma/Deflection IC
LA76818A peripheral circuit.
R125
9V
R115
56
C125
R121
1/16GJ
X
6.8KC
R124
1/16GJ
10KC
R122
D122
1/16GJ
2.2KC
1SS356
R244
Q122
27K
1/16GJ
AH
47KC
5V-1
X
JP171
R178
X
R188
C124
KK0.01
GQ
X
Q171
Q172
X
R245
1/16GJ
47KC
1/16GZ0C
X
R172
C185
C358
EM1
Q174
JP174
X
X161A
R180
X
X
R174
X
R175
X
C138
KK
0.022GQ
X
X
R358
1/16
GZ0C
JP173
R171
R177
X
X
X
1/16GZ
0C
1/16GZ0C
SF6376U
C121
KK0.01
GQ
C122
16EM
100
R185
C120
KK
0.022GQ
R130
C123
X161
X
Q176
C176
X
R186
X
X
JP176
1/16
GZ0C
AUDIO
1
OUTPUT
2
FM OUTPUT
3
PIF AGC
RF AGC
4
OUT
5
IF IN
6
IF IN
7
IF GND
8
IF VCC
FM FILTER
R291
2SJ4.7
IC201
LA76818AM
EXT.AUDIO
APC FILTER
VCO COIL1
VCO COIL2
VCO FILTER
9V
C275
EM47
SIF IN
SIF APC
FILTER
SIF OUT
VIDEO
OUTPUT
(2Vpp)
IC202
L78M05CV:
BA178M05T:
MC78M05CT:
UPC78M05AHF
54
R176
C172
1/16GJ
KK0.01
10KC
GQ
53
52
R170
X
51
IN
R181
X
C133
X
50
C132
EM0.47
49
R179
X
48
C135
EM0.47
47
R140
1/16GZ
0C
469
L175
C171
KK1500
GQ
X
C177
321
X
L273
J
C174
CD10CGQ
R132
1/16GJ
470C
5V-1
C276
EM47
X171
X
L171
L14B1830N
:L14B1870N
Q173
X
R173
X
R114
1/16GJ
330C
C113
KK0.01
GQ
Q111
2SC2814
F4P
R116
1/16GJ
56C
JP111
B1
130V
R103
1SJ39K
R112
1/16GJ
5.6KC
C111
KK
0.01
GQ
R111
1/16GJ
1KC
X
3-1 IF stage
The IF signal output from the tuner is amplified by the pre-amplifier Q111, then sent to
the SAW (Surface Acoustic Wave) filter X161. The output signal of the SAW filter
X161 is input to pins 5 and 6. The IF signal thus input to the IC is then amplified by
the IF amplifier, and is detected by video detector with the VCO (Voltage Controlled
Oscillator) circuit consisted of L 171 (38 MHz coil) and it is output as a composite video
signal. The composite video signal passes through sound traps then amplified and it is
output as a video signal at pin 46. The output of pin 52 is supplied to pin 54, and is
detected by FM detector with SPLL (Sound Phase Loop Lock) circuit and it is output as
a FM signal at pin 2, and Audio signal at pin 1.
3-2 Video/Chroma stage
The video signal output from pin 46 of IC201 is then supplied to pin 44. The external
video signal from the A V terminal is supplied to pin 42.
The video signal input to pin 44 or 42 is processed in IC201, then seperated into the R
(red) at pin 19, G (green) at pin 20, and B (blue) at pin 21.
The external RGB signals for the on screen display or teletext display are input to pins
14(R), 15(G), 16(B). In the IC, the external RGB signal are mixed in the selection
circuit driven by blanking signal input to pin 17 and finally output to 19, 20, 21.
The colour, contrast, brightness, tint and sharpness controls can be controlled by the
CPU in 7 bits digital data through the analogue bus lines on pins 11 and 12.
3-3 Deflection stage
The Horizontal drive pulse is processed in IC201, and sent from pin27 than drives
transistor Q431. The vertical drive pulse is sent from pin 23 of IC201 to pin 1 of IC501,
vertical output is from IC LA78041.
D103
RD36EB1:
MTZJ36A:
DZXLBZA36A
C112
KK0.01
GQ
R101
1/16GZ
0C
R104
C107
EM47
X
11.IF
L101
J
5V-1
R106
R107
100
100
C109
9.TB
7.PB
6.MB
R105
JP102
J
X
R102
J
D102
C102
X
X
R108
18K
C101
16EM
470
X
5.DATA
R109
1/16GJ
68KC
4.CLOCK
J30B0250N
:J30B1380N
C108
TP-A
X
3.GND
C106
EM47
A101
F1BEB0270:
F1BEB0300
1.AGC
22
Training Manual FC3G2 Chassis
Page 23
4. Audio Output.
The internal audio signal from pin 1 of IC201 is supplied to pin 1 and 30 of IC3701,
audio output amp using AN17820B (for stereo model) or AN7523N (for mooral model).
The external audio signal is supplied to IC3701(for model with surround option) or
IC1201 (for model without surround option). The sound volume control by CPU data.
Note : IC3701 (NJW1142MP) is used as audio/tone control IC.
JP374
L-FI
R-FI
FROM CPU
MNST
LIN
RIN
R1202
R1201
X
R1203
X
MN/ST
AUDIO-CONTROL
R3701
XX
18
2
3
4
5
6
7
8
9
10
11
12
13
14
IC3701
NJW1142MP
CVA
CVB
OUTa
L--L
L--R
L--L
R--R
L--R
TV
AV
AV
AV
IN1B
IN2B
IN3B
IN4B
MONB
CSR
TONE-Hb
TONE-Lb
LINEbLINEa
OUTb
AGC
CTH
CTL
VREF
Vcc
IN1A
IN2A
IN3A
IN4A
MONA
SR-FIL
TONE-Ha
TONE-La
SDA
SCL
GND
30
C3721
EM4.7
29
C3722
EM4.7
28
C3723
EM4.7
27
26
25
24
23
22
R3725
X
21
20
19
18
17
1615
C3701
16EM470
IC1201
1
2
3
D1201
R
L
NC
MONO/ST
X
X
C1202
X
C015
X
R015
1/16GJ3.3KC
GND
VCC
NC
X
R1205
X
9V-2
R1204
X
7
6
C1201
54
X
X
KK0.022GQ
JP373
X
16KK0.33BA
L OUT
IIC BUS
R OUT
C3710C3720
EM4.7EM4.7
C3711
EM4.7
C3712
EM4.7
C3713
EM4.7
C3730
C3714
KK2200GQ
C3715
R3702
C3717
EM1
C3727
EM1
SDA
R3731
1/16GJ100C
SCL
R3732
1/16GJ100C
C025
X
R025
1/16GJ
3.3KC
L OUT
R OUT
R3726
X
JP375
C3731
16KZ1GMF
C3724
KK2200GQ
C3725
16KK0.33BA
C3732
16KK
0.33BA
C3733
EM1
C3734
EM1
C3735
EM1
C3702
25KK
0.1GQ
1/16GZ0C
X
JP372
X
JP371
L-RO
R-RO
ATV
X
AOUT
AIN
9V
D3701
AA
L3701
9V-1
J
9V-2
FOR WOOFER
OUT OPTION
SP901
A10B26200
SP902
A10B26200
00
K1
J12B06000
HEAD
PHONE
GND AUDIO
K001
K002
J10EA040N
:J10KR040N
1
X
R006
1/2DJ150
R007
1/2DJ150
C035
J
JP012
X
C034
IC001
AN17820B
J
JP011
X
JP011A
X
TO CPU
R012
Q011
X
R out +
R052
X
R051
X
9V
R022
R013
X
X
R014
X
R out -
Q021
X
R023
R024
Vol
X
C012
X
X
C022
X
Gnd out
C060
X
C059
X
X
R in
C021
EM1
Gnd in
C011
EM1
L in
R032
1/16GJ
27KC
Std by
= L
R005
10K
D002
X
L out -
C031
EM47
9V
R034
1/16GZ0C
C013
X
R036
1/16GZ0C
C014
X
Gnd out
L out +
R033
27K
R035
1.5K
R037
27K
R038
1/16GJ
1.5KC
Vcc
123456789101112
25EM2200
LBWA
C001
C3737
R008
J
C3738
J
D003
X
D004
11V
P.F
JP010
X
J
R010
X
X
XX
R644-H1
TO CPU
MUTE
L IN
FROM AUDIO
PROCESSOR OUTPUT
R IN
23
Training Manual FC3G2 Chassis
Page 24
5. Vertical
The ramp signal, from pin 23 of IC201 drives the vertical drive circuit at pin 1 of IC501.
In the first half of scanning period, a deflection current is sent from pin 5 and passed
through the following path;
Vcc(24V) Æ D512 Æ pin 6 Æ pin 5 Æ DY Æ C515 Æ R518.
An electric charge is then stored in C515. In the last half of scanning period, the
current path is C515 Æ DY Æ pin 5 Æ pin 4 (GND) Æ R518.
In this way, an increasing sawtooth waveform current flows directly to the DY to
perform electron beam deflection. During the first half of the blanking period, the
vertical ramp signal suddenly turns off. Since there is no longer any current flowing
into the DY, the magnetic field in DY collapses causing an induced current to flow as
flows; DY Æ pin 5 Æ pin 4 Æ R518 Æ C515 Æ DY. Once the magnetic field in DY has
dissipated, the current path becomes; Vcc Æ pin 2 Æ pin 3 Æ C517 Æ pin 6 Æ pin 5 Æ
DY Æ C515 Æ R518. And when the prescribed current values is reached, the vertical
drive pulse turns on. This completes one cycle.
6. Horizontal Output
The horizontal oscillator signal is output from pin 27 of IC201 and used for switching
the drive transistor Q431. This switching signal is current amplified by the drive
transformer T431 and drives the output transistor Q432. When Q432 turns ON,
increasing current flows directly to the DY through
D439 Æ C441/C442 Æ L441/R441 Æ L442/R442 Æ DY Æ Q432-C Æ Q432-E.
And the deflection occurs during the last half of the scanning period. When Q432
turns off, the magnetic field stored in the DY up to that point causes a resonant current
to flow into the capacitors C420/C423 and charges them. The current stored in
C420/C423 then flows back to the DY causing an opposite magnetic field to be stored in
the DY. This field then collapses increasing a current which switches the dumper diode
in Q432 ON.
The resonance state is completed, and an increasing current then flows again directly
to the DY through the dumper diode.
By this means, the deflection in the first half of the scanning period is performed.
When Q432 turns ON at the end of the first half of the scanning period, the deflection
during the last half is begun, thus completing one cycle. ( see fig. on p. 25 )
24
Training Manual FC3G2 Chassis
Page 25
J
X
R241
D249
X
D421
MTZJ16A:
RD16EB1:
9V
X
Q540
AE
R359
82K
R357
1.8K
R211
150
R212
150
R243
X
HORIZ.
DRIVE
R540
1K
L462
L26A00200:
L26B4630N
L26B0170N:
LM0045(:D)
D357
1SS133
5V-1
D210
J
24V
C540
25PM10
L461
C465
100GK
2.2
V-OUT
C230
X
JP202
J
R432
1/16GJ1KC
C431
X
L462-H1
2400030X
L462-H3
2400010
Q461-H2
2400010
Q461-H1
C232
HJ0.33G
C210
25EM
1000
JP201
X
Q431
2SC3332
(R:S)
2400010
134
L462-H2
R478
X
2HEF0068--
C201
PM1
R431
X
Q461
2SB1274
(QRA:RRA)
Q461-1
C231
HJ
0.33G
R210
1/16GJ
3KC
C202
FJ0.015
(A:BE:D)
24V
R434
1/2DJ
100
C433
500KK
3900A
R433
1/2DJ
1K
R473
470
Q461A
X
Q462
H-DRIVE
TRANS
:B4L18B0020N
C434
35EM
47
JWW1
1
R471
1.5K
AE
VR462
R3D6472NJ:
R3D7472NJ
23
V-OUT
RAMP ALC
24
FILTER
25
H-VCC
H-AFC
26
FILTER
H-OUT
B1
130V
T431
AD0002(:C)
:L18B0540N
T431-H2 T431-H4
24000302400030
2400030
T431-H1
C432
500KK
1000A
R355
DJ10K
R426
10K
R480
C461
47K
X
R472
47K
R468
X
R469
82K
2400030
T431-H3
C355
KK1500
EM220T
CCD FILTER
CCD VCC
CLOCK
OUTPUT
VCO IREF
FBP IN
R445
X
400MJ0.15CQ:
250MJ0.15AP:
250MJ0.18AU
Q432-1
2HEA0236--
Q432
2SD2634YB
L431
L7201B:
L2G31R0MN
L432
B4Z21B0030N:
Z21B0050N:
ZZ0008
HORIZONTAL
DEFLECTION
PCC
CIRCUIT
C463
R461
C462
470
EM
0.47
C466
63GK0.39V
:HJ0.39G
D462
1.8K
R352
DJ10K
C442
Q432-H3
32
31
30
29
2827
2400010
KK0.01
GQ
R510
10K
R511
10K
R466
1.8K
D461
1SS133
R464
12K
R286
1/16GF4.7KC
D352
RD5.1EB2
5V-1
(:LBWAJ)
V OUT
PROTECT
L441
L71B0160N
C442-H1
2400030
2400030
C442-H2
X2400030
C442-H3C441-H3
Q432-H2
2400010
2400010
Q432-H1
D642
1.5M
D465
R467
1.2M
C468
25EM22
R354
22K
C510
16EM22
Q527
AH
L26B4560N
J441
X
C441-H1
2400030
C441
400MJ0.18CQ:
250MJ0.18A
X
(P:U)
C441-H2
D438
ERD07
-15L
D439
ERB44
-04
R463
680
J
C470
KZ
0.01F
D466
MTZJ20A:
RD20EB1
C527
EM10
L442
L442-H1
L441-H1
L441-H3
L441-H2
1500MH6800
(AN:XK:VBA)
C423A
C425
400NJ
0.02EAQ
R465
4.7K
VR463
R3D7102NJ
C467
10EM
220
D469
L442-H2
C423-H2
X
C423-H1
C511
KK0.01
GQ
X
X
2400010
2400030
2400030
C420
2400030
2400030
EU1
R462
470
R512
DJ
470
C517
35EM
220
C423-H3
2400030
C423
1500MH
7800(AN
:XK)
JP436
J
C424
400NJ
0.022EAQ
C464
EM1
JP463
R474
1/2DJ1K
R527
1/16GJ
56KC
R442
2SJ1K
R441
1SJ1K
C424AC425A
XX
X
INPUT
OUTPUT
STG VCC
76
D512
EM01Z
:ERA15-02
:ED0448
R514
8.2K
C491
X
C420-H3
2400030
C420-H2
R492
X
2400030
C420-H1
C486
250EM
33CY
JP435
R423
DJ47K
R422
DJ47K
OUTPUT
5
100
R515
39K
C514
EM22
R522
470
500KK
680A
D485
EU1
R488
1/2FJ1
R435
7SJ6.8VC
X
B1
130V
PROTECT
VERT.
DEFLECTION
IC501
LA78041
INPUT
VCC
GND
4
INVERT
PUMP UP
321
C518
R503
KK3300
X
24V
JW37
1
JP503
J
R519
T471-H10
VIDEO
T471-H2
+B
AFC
T471-H5
Q449
X
C521
35EM
2200
(:LBWA)
C524
R525
1SJ180
T471
L40B16000
T471A
X
R477
X
R477A
1SJ560
C449
X
JP501
J
100FK
0.1(D:BE)
D441
ERC05-10B:
RM11C
C487
X
T471-H8
2400010
JP403
J
HEATER
LOW B
R424
1K
R449
X
D501
J
11
D448
7
64
64
HV
FO
SC
2400010
2400010
2400010
JP404
X
D468
JW36
T471-H11
T471-H6
X
AA
1
R502
R487
J
ABL
T471-H7
JP405
R479
1/16GJ
2.2KC
X
R484
X
R486
X
J
C471
100PM
2.2(X:
LBZAJ)
MTZJ11C:
RD11EB3
C520
100FK0.1
(D:BE)
R516
1.2K
C515
25EM2200
LBWA
R518
1SJ1.8
T471-H1
H-OUT
2400030
1
1
JP407
J
2400010
10
10
JP408
X
JW1
2400030
2
2
1
C437
C437A
X
250GJ
0.47
JP409
J
JP412
X
2400010
T471-H4
JP410
J
2400010
53
53
GND
JP411
X
JP477
J
SW501
B4S10B00100:
S10B1370N
R501
2SJ1K
KDY
J10B0730N
HEATER
180V
R485
X
D486
X
JP483
J
R483
X
R481
2SJ4.7
R481A
X
D467
P
D476
C469
EM10
KDY-6
6
5
KDY-3
3
KDY-1
1
4
GND
GND
1
PROTECT
R475
1/2DJ330
DY
L70B17400
2400010
2400010
2400010
KQ
X
HV
FOCUS
SCREEN
25
Training Manual FC3G2 Chassis
Page 26
7. Power Consumption Saving Circuit.
This chassis employs the internal oscillation circuit (SMPS : Switching Mode Power
Supply) on the power circuit for saving consumption of power during the stand-by mode.
( see page 26 for circuit diagram of power supply ).
The internal oscillation circuit consist of Q663, Q662, D662 and peripheral circuit.
Q663 and Q662 drives the photo coupler D610 and oscillation of power circuit
according to voltage level on point (A) in figure. During power on mode, the voltage on
point (A) is almost 0V and Q663 and Q662 maintain turning off.
When the set switches into stand-by mode, the voltage on point (A) increases about
24V. The voltage which is decided with R671 and R673 is applied to Q663-base and
drives Q663 and Q662 turning on. When Q662 turns on, the photo-diode in D610 is
completely turned on, then Q612 is turned on and Q613 is turned off. By this means,
the oscillation of power circuit stops and the voltage of secondary power supply falls
down. Also the voltage of point(A) falls down from 24 V gradually.
When the voltage on Q663-base is less than voltage of Q663-emitter, Q663 is turn off
and then Q662 is off, then D610 and Q612 are turned off. Finally Q613 starts the
oscillation and voltages are supplied to the secondary circuit. By this means, the
voltage on point (A) rises up and drives Q663 on again. By repeating the above
operation, the power consumption in the stand-by mode can be saved.
26
Training Manual FC3G2 Chassis
Page 27
g
pp
y
PROTECT
D690
C690
EM2.2
Q690
1SS355
CT
R691
1/16GJ
AH
47KC
R694
5.6K
R690
R692
D691
1/16GJ
47KC
1/16GJ
20KC
AA
R693
1/16GJ
10KC
R695
C691
DJ6.8K
AD
Q693
35EM47
R696
1/16GJ
4.7KC
R697
1/16GJ
D692
47KC
EU1
C693
16EM47
11V
D693
R673
1/16GJ
560KC
EM0.22
C663
1/16GJ
22KC
R667
Q662
1/16GJ
10KC
AC
Q663
R666
AA
AH
Q654
24V
D662
MTZJ
6.8A:
9V
2SD1913
(QRA:RRA)
DZXLB
ZA6.8A
AA
D655
C665
R671
22K
R672
12K
16EM470
R656
Q652
R645
X
X
JP652
C656
1000KK
470(CRD:NH)
L652
1
R655
R653
J
DJ10K
1FJ5.6
23
2SB1565E
35EM
470T
C652
RN1Z
D652
IC681
BA178M05T:
MC78M05CT:
X
T611-H14
T611B-H14
R657
R652
5VRC
UPC78M05AHF:
X
R668
2SJ12
DJ3.9K
JP653
33K
1/16GZ0C
123
J
R646
C657
L78M05CV
1000KK470
(CRD:NH)
14
C681
L653
J
2SJ
12
R669
10EM470
R658
X
D653
FE301-1L43:
X
T611B-H13
15
D659
R659
X
Q653
25EM
C643
RU4YXLF-L1
T611-H12
T611B-H12
X
12
R651
1SJ270
X
X
1000T
C658
1000KK470
2400030
X
R660
1K
MTZJ10B:
D664
11V
(CRD:NH)
J
L654
16
AA
D671
AE
Q681
AD
Q651
C664
16EM220:
16EM220LBWA
RD10EB2:
DZXLBZA10B
AUDIO
D654A
2HEF0021--
:2HEF0065--
D654
2400010
D654-H1
D654-H2
2400010
T611-H13
L-ST
H-ON
R681
22K
PM1
C653
R654
15K
C654
25EM
3300
YG901C2-LB
T611B-H17
2400030
13
R682
1/16GJ
X
TP-130
C655
(CRD:NH)
1000KK680
2400030
T611-H17
X
17
560KC
JP631
L651
X
1SJ27K
X
C651-H1
X
C651
RU3AM
R661
160EM
220XJ
C639
DJ100K
VR651
R665
DJ12K
R663
150K
Q661
AH
R662
1/16GJ
R3D6222NJ:
R3D7222NJ
D661
MTZJ6.2C:
RD6.2EB3:
3.9KC
DZXLBZA6.2C
B1
130V
R664
JP633
J
C651-H2
X
D651
J
C610
X
T611-H6
7
6
5
4
R615
T611
L51B5900N
220
X
X
T611-H5
L611
C618A
X
C618
630GK0.047DCN
2SJ
68K
R626
R625
2SJ68K
R620
1/2DJ
470K
C616
C615
C617
R621
X
2000KK
220CRD
2000KK
220CRD
EG01C
D611
Q611
R622
DJ47
1/2DJ
470K
2SC
T611-H7
L613
2274
2400030
ZZ0122:
R624
(D:E:F)
R623
C628
X
AT3AT3AT3AT3AT3AT3AT3AT3AT3AT3AT3 AT3
4
X
C619
PC123X5YFZ:
PC123Y52:
TLP421F-BL
D610
R619
400EM
220XC
C609A
2400010
2400010
2400010
2400010
400EM
220XC
AT3AT3AT3AT3
X
AT3AT3AT3
AT3
AT3
AT3AT3AT3
RBV-608
D601
C609
D606
C606
C605
D605
1234
R602A
15WK1.8
(VE:M)
2400010
2400010
XX
24000102400010
JP601
D608
X
C608
C608
1000KK
1000(CBB:HB)
D605/.../D608
XX
XX
C607
X
X
D607
C605/.../C607
C602
2400030
2400030
2400030
J
X
PS601
JP602
1
2
250GM0.1X
(BJ:D:E):
275GM0.1
(VB:XB)
X
2400030
X
2400030
L601
DHXAAEV0070
X
L601A
R601
X
2400030
X
2400030
F35B0570N
:B4F35B0040N
:F35B1130N
X
C601
250GM0.1X
(BJ:E:D):
275GM0.1
VA601
ERZV14D471
(XB:VB)
C613
FK0.1BE
:FK0.1D
SW601
S10B6230N
2400010
2400010
X
T611-H8
J
L612
X
Q613-H6
Q613-H2
2400010
2400010
Q613-H3
ZZ0122XXA
1/2
FJ10
L615
D617
330K
R627
22K
X
D615
DJ22
D614
ES1
F601
4A250VTW
:4A250VHOTS
L614
Q613-H1
2400010
Q613
R631
ZZ0122
(:XXA)
1SS133
1
ZZ0122
(:XXA)
2SK
3102F
47K
C614
D612
ERA81-004
Q612
2SA984
(E:F)
HJ0.22G
D616
MTZJ20B
D619
MTZJ10C:
RD10EB3
2
L616
:RD20EB2
Z21B
0140B
DJ
R611
470
R616
R613
3
2400030
T611-H3
2400010
2400010
Q613-H5
R633
1SS
D643
10K
FJ330P
Q613-H4
2SJ0.33
133
Q625
R632
2SC
2SJ
2274
0.27
(E:F)
R628
C611
R614
1/2CK
D641
R641
22K
1/2CK
R629
5.6MXG
C644
25EM
3.3
18K
R643
AD
Q642
J
10K
Q641
FJ0.01BE:
FJ0.01D
5.6MXG
C629
250KM3300XN:
R644
22K
R642
AB
250KK3300XH
Circuit
l
47K
. of AC5G1 Power Su
Fi
AT3
27
Training Manual FC3G2 Chassis
Page 28
Part 2 Block Diagram of ICs
1. LA76818A (IF/VIDEO/CHROMA/DEFLECTION)
28
Training Manual FC3G2 Chassis
Page 29
29
Training Manual FC3G2 Chassis
Page 30
2. LA78041N (VERTICAL OUTPUT)
3. AN17820B (AUDIO OUTPUT)
30
Training Manual FC3G2 Chassis
Page 31
4. LA7642NM (SECAM DECODER)
5. 24LC16B/P (IC MEMORY)
31
Training Manual FC3G2 Chassis
Page 32
Part 3 Trouble shooting Chart
Dead
No picture – no sound
No picture – sound OK
No sound – picture OK
No Color & color NG
No vertical deflection
No On-Screen Display
Page 33 - 35
Page 36 - 37
Page 38
Page 39
Page 40
Page 41
Page 42
32
Training Manual FC3G2 Chassis
Page 33
Trouble Shooting Chart Startpoint symptom: Dead
Is the fuse OK
Check voltage on both
ends of C609
Check voltage on pin 1
of IC681
Is the power LED
lighting ?
Check voltage (+24V)
on Q652-collector
Check voltage (+130V)
on both ends of C651
Go to next page
Dead
YES
+390V~400V
+12.5V
YES
YES
YES
NO
0V
0V
NO
NO
NO
Are there any burned part ?
Check power primary circuit C601, C602,
VA601, PS601, R602, C608, C609,
D601/D605~D608, Q611, Q612, Q613, Q625,
C613, R624.
Secondary circuit, Q661, D661, C651, R661,