SAMSUNG S3C72K8, S3P72K8 Technical data

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S3C72K8/P72K8 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to­320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an
excellent design solution for a wide variety of applications which require LCD functions.

Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.

OTP

The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8.
S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM.
The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration.

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PRODUCT OVERVIEW S3C72K8/P72K8

FEATURES

Memory

— 8 K × 8-bit RAM
— 1,024 × 4-bit ROM

27 I/O Pins

— Input only: 4 pins
— I/O: 15 pins
— Output: maximum 8 pins for 1-bit level output

(sharing with segment driver outputs)

Comparator

— Two channel mode: internal reference

(4-bit resolution)

— One channel mode: external reference

LCD Controller/Driver

— 40 segments and 8 common terminals
— 3, 4 and 8 common selectable
— Internal resistor circuit for LCD bias
— All dot can be switched on/off

8-Bit Basic Timer

— 4 interval timer functions
— Watchdog timer

8-Bit Timer/Counter

— Programmable 8-bit timer
— External event counter
— Arbitrary clock frequency output
— External clock signal divider
— Serial I/O interface clock generator

8-Bit Serial I/O Interface

— 8-bit transmit/receive mode

Watch Timer

— Timer interval generation:

0.5 s, 3.9 ms at 32,768 Hz
— Four frequency outputs to BUZ pin
— Clock source generation for LCD

Interrupts

— Three internal vectored interrupts:

INTB, INTT0, INTS

— Four external vectored interrupts:

INT0, INT1, INT4, INTK

— Two quasi-interrupts: INT2, INTW

Memory-Mapped I/O Structure

— Data memory bank 15

Two Power-Down Modes

— Idle mode (only CPU clock stops)
— Stop mode (main system oscillation stops)
— Subsystem clock stop mode

Oscillation Sources

— Crystal, ceramic, or External RC for system clock
— Main system clock frequency: 0.4 MHz–6 MHz
— Subsystem clock frequency: 32,768 kHz
— CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

— 0.67 us at 6 MHz (minimum)
— 0.95 µs at 4.19 MHz (minimum)
— 122 µs at 32,768 kHz (minimum)

Operating Temperature

— – 40 °C to 85 °C

— 8-bit receive only mode
— LSB-first or MSB-first transmission selectable
— Internal or external clock source

Bit Sequential Carrier

— Support 16-bit serial data transfer in arbitrary

format

1-2

Operating Voltage Range

— 2.0 V to 5.5 V

Package Type

— 80-pin QFP

S3C72K8/P72K8 PRODUCT OVERVIEW

SEG0-SEG31

BLOCK DIAGRAM

IN

OUT

X

X

XT

IN

XT

Clock

OUT

Stack

Pointer

Program

Counter

Program

Status Word

Flags

8 Kbyte

Program

Memory

LCD Driver/

Controller

I/O Port 2

I/O Port 3

I/O Port 4

8-Bit

Timer/

Counter

V

LC1-VLC5

COM0-COM7
P5.0/SEG32-

P5.7/SEG39

P2.0-P2.3
P3.0

P3.1
P3.2/LCDSY
P3.3/CLDCK

P4.0/CLO
P4.1/TCL0
P4.2/TCLO0

Watchdog

Timer

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

P1.0/INT0/CIN0
P1.1/INT1/CIN1

P1.2/INT2
P1.3/INT4

Basic

Timer

Watch

Timer

SIO

I/O Port 0

Comparator

Input Port 1

RESET

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

1024 x 4-Bit

Data Memory

Figure 1-1. S3C72K8 Simplified Block Diagram

1-3

PRODUCT OVERVIEW S3C72K8/P72K8

PIN ASSIGNMENTS

SEG32/P5.0

SEG33/P5.1

SEG34/P5.2

SEG35/P5.3

SEG36/P5.4

SEG37/P5.5

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

P5.6/SEG38
P5.7/SEG39

VLC1
VLC2
VLC3
VLC4
VLC5

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P1.0/INT0/CIN0
P1.1/INT1/CIN1

P1.2/INT2
P1.3/INT4

P2.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25

S3C72K8

(80-QFP-1420C)

32

31

30

29

28

27

26

33

34

35

36

37

38

39

40

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6

1-4

COM5

COM4

COM3

COM2

COM1

COM0

TCLO0/P4.2

TCL0/P4.1

CLO/P4.0

LCDCK/P3.3

LCDSY/P3.2

P3.1

P3.0

P2.3

P2.2

P2.1

Figure 1-2. S3C72K8 80-QFP Pin Assignment

S3C72K8/P72K8 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C72K8 Pin Descriptions

Pin Name Pin

Type

P0.0

I/O 4-bit I/O port.
P0.1
P0.2
P0.3

1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

Description Circuit

Type

E–2 8

Pin

Number

9
10
11

Share Pin

K0/SCK

K1/SO

K2/SI

K3/BUZ

Individual pins are software configurable as open­drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

P1.0
P1.1
P1.2
P1.3

I 4-bit input port.

1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.

F–4
F–4
A–3
A–3

20
21
22
23

INT0/CIN0
INT1/CIN1

INT2

INT4
An interrupt is generated by digital input at P1.0,
P1.1.

P2.0–P2.3 I/O Same as port 0 except that 8-bit read/write and test is

E–2 24–27 –

possible.

P3.0
P3.1
P3.2
P3.3

P4.0

I/O Same as port 0 except that port 4 is 3-bit I/O port. E–2 32
P4.1
P4.2

P5.0–P5.7 O Output port for 1-bit data H–11 75–

SCK

I/O Serial I/O interface clock signal E–2 8 P0.0/K0

28
29
30
31

33
34

80,1,2

–

–
LCDSY
LCDCK

CLO

TCL0

TCLO0

SEG32–

SEG39

SO I/O Serial data output E–2 9 P0.1/K1

SI I/O Serial data input E–2 10 P0.2/K2

BUZ I/O 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at

E–2 11 P0.3/K3

the watch timer clock frequency of 32.768 kHz.

K0–K3 I/O External interrupt. The triggering edge is selectable. E–2 8–11 P0.0–P0.3

INT0
INT1

INT2 I Quasi-interrupt with detection of rising or falling

I External interrupts. The triggering edge for INT0 and

INT1 is selectable.

F–4 20

21

P1.0/CIN0
P1.1/CIN1

A–3 22 P1.2

edges

INT4 I External interrupts with detection of rising and falling

A–3 23 P1.3

edges

1-5

PRODUCT OVERVIEW S3C72K8/P72K8

Table 1-1. S3C72K8 Pin Descriptions (Continued)

Pin Name Pin

Type

CIN0

I 2-channel comparator input.

CIN1

CIN0: comparator input or external reference input

Description Circuit

Type

F–4 20

Pin

Number

21

Share Pin

P1.0/INT0
P1.1/INT1

CIN1: comparator input only.

LCDSY I/O LCD synchronization clock output for display

E–2 30 P3.2

expansion

LCDCK I/O LCD clock output for display expansion E–2 31 P3.3

CLO I/O Clock output E–2 32 P4.0

TCL0 I/O External clock input for timer/counter 0 E–2 33 P4.1

TCLO0 I/O Timer/counter 0 clock output E–2 34 P4.2

SEG32–

SEG39
SEG0–

O LCD segment signal output H–11 75–

P5.0–P5.7

80,1,2

O LCD segment signal output H–6 43–74 –

SEG31

COM0–

O LCD common signal output H–6 35–42 –

COM7

V

LC1–VLC5

– LCD power supply. Voltage dividing resistors are

– 3–7 –

assignable by mask option.

X

X

,

IN

OUT

– Crystal, ceramic or RC oscillator pins for system

– 15, 14 –

clock.

XT

IN

XT

OUT

V

DD

V

SS

RESET

,

– Crystal oscillator pins for subsystem clock. – 17, 18 –

– Main power supply – 12 –
– Ground – 13 –

I Chip reset signal input B 19 –

TEST I Chip test signal input (must be connected to VSS) – 16 –

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode

1-6

S3C72K8/P72K8 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

P-Channel

In

N-Channel

Figure 1-3. Pin Circuit Type A

VDD

Pull-Up

Resistor

P-Channel

In

Pull-Up
Resistor
Enable

Data

Output

Disable

VDD

Pull-Up
Resistor

In

Schmitt Trigger

Figure 1-5. Pin Circuit Type B

VDD

P-Channel

Out

N-Channel

Schmitt Trigger

Figure 1-4. Pin Circuit Type A-3

Figure 1-6. Pin Circuit Type 7

1-7

PRODUCT OVERVIEW S3C72K8/P72K8

VDD

Data

Output

Disable

PNE

Schmitt Trigger

VDD

Figure 1-7. Pin Circuit Type E-2

Pull-up
Resistor

Resistor
Enable

P-CH

I/O

N-CH

VDD

Resistor Enable

Schmitt Trigger

Digital In

EXT-REF

(P1.0 only)

Analog In

Comparator

Digital or Analog Selectable

by Software (P1MOD)

Figure 1-8. Pin Circuit Type F-4

Pull-up

Resistor

I/O

+

-

INT-REF

1-8

S3C72K8/P72K8 PRODUCT OVERVIEW

VDD

VLC1

VLC2

SEG/COM Data

Output Disable

VLC3

VLC4

VLC5

Out

Figure 1-9. Pin Circuit Type H-5

1-9