Samsung S3C72G9, S3P72G9 Datasheet

S3C72G9/P72G9 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With an up-to-896-dot LCD direct drive capability, and flexible 8-bit timer/counters, the S3C72G9 offers an
excellent design solution for a high-end LCD game.

Up to 12 pins of the 100-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C72G9's advanced CMOS technology provides for
low power consumption.

OTP

The S3C72G9 microcontroller is also available in OTP (One Time Programmable) version, S3P72G9. S3P72G9
microcontroller has an on-chip 32 K-byte one-time-programmable EPROM instead of masked ROM. The
S3P72G9 is comparable to S3C72G9, both in function and in pin configuration.

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PRODUCT OVERVIEW S3C72G9/P72G9

FEATURES

Memory

• 768 × 4-bit RAM (excluding LCD display RAM)

• 32,768 × 8-bit ROM

12 I/O Pins

• I/O: 12 pins

LCD Controller/Driver

• 56 segments and 16 common terminals
(8, 12 and 16 common selectable)

• Capacitor bias for LCD output.

• Voltage booster and regulator

• All dots can be switched on/off

8-bit Basic Timer

• 4 interval timer functions

• Watch-dog timer

One 16-bit Timer/Counter 1

• Programmable 16-bit timer

• Arbitrary clock output (TCLO1)

• Inverted clock output (TCLO1)

• Configurable two 8-bit timer/counters

Interrupts

• Three Internal vectored interrupt

• Four external vectored interrupts

• Two quasi-interrupts

Memory-Mapped I/O Structure

• Data memory bank 15

Power-Down Modes

• Idle mode (only CPU clock stops)

• Stop mode (main system oscillation stops)

• Subsystem clock stop mode

Oscillation Sources

• Crystal, ceramic, or RC for main system clock

• Crystal oscillator for subsystem clock

• Main system clock frequency: 0.4-4.19 MHz

• Subsystem clock frequency: 32.768 kHz

• CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19 MHz (main)

• 122 µs at 32.768 kHz (subsystem)

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz

• Four frequency outputs to BUZ pin and BUZ pin

• Clock source generation for LCD

Battery Level Detector

• Programmable low voltage detector

• One criteria voltage (2.4 V)

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Operating Temperature

• – 40 °C to 85 °C

Operating Voltage Range

• 2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)

Package Type

• 100-pin QFP or pellet

S3C72G9/P72G9 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

RESET

X

X

IN

TIN

X

OUT

TOUT

Basic

(Watchdog)

Timer

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P0.3/BUZ/K3
P0.2/

BUZ

P0.1/
P0.0/TCLO1/K0

/K2

TCLO1

/K1

P2.0/CLO

P2.1/TCL1

P2.2
P2.3

8-bit Timer

Counter 1A

8-bit Timer

Counter 1B

I/O Port 1

I/O Port 0

I/O Port 2

16-bit
Timer

Counter 1

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic

and

Logic Unit

768 x 4-bit

Data

Memory

Clock

Instruction

Register

Program

Counter

Program

Status Word

Stack

Pointer

32-Kbyte

Program

Memory

Watch

Timer

Voltage

Regulator/

Booster

LCD Driver/

Controller

Battery

Level

Detector

TEST 2
CA
CB

SEG0-SEG55
COM0-COM15
VLC1-VLC5

Figure 1-1. S3C72G9 Simplified Block Diagram

1-3

PRODUCT OVERVIEW S3C72G9/P72G9

PIN ASSIGNMENTS

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

VLC1

VLC2

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

VLC3
VLC4
VLC5

CA
CB

TEST2
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

BUZ/P0.3/K3

BUZ/P0.2/K2

TCLO1/P0.1/K1

TCLO1/P0.0/K0

VDD

VSS

XOUT

XIN

TEST1

XTIN

XTOUT

RESET

CLO/P2.0

TCL1/P2.1

P2.2

P2.3
COM15
COM14
COM13
COM12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32

33

34

35

36

37

KS57C21632

100-QFP 1420 C

41

40

39

38

42

43

44

45

46

47

48

49

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

SEG18
SEG19
SEG21
SEG22
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47

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SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

Figure 1-2. S3C72G9 100-QFP Pin Assignment Diagram

S3C72G9/P72G9 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C72G9 Pin Descriptions

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

INT0, INT1 I/O External interrupts. The triggering edge for INT0 and

INT2 I/O Quasi-interrupt with detection of rising or falling

INT4 I/O External interrupt with detection of rising and falling

BUZ I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for

BUZ

CLO I/O Clock output 23 P2.0
TCL1 I/O External clock input for timer/counter 1 24 P2.1

TCLO1
TCLO1 I/O Timer/counter 1 clock output 14 P0.0/K0
COM0–COM15 O LCD common signal output 42-27 –
SEG0–SEG55 O LCD segment signal output 98-43 –

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open­drain or push-pull output.
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for output
pins.

I/O Same as port 0 10

I/O Same as port 0 23

INT1 is selectable.

edges.

edges.

buzzer signal.

I/O Inverted BUZ signal 12 P0.2/K2

I/O Timer/counter 1 inverted clock output 13 P0.1/K1

14
13
12
11

9
8
7

24
25
26

10, 9 P1.0, P1.1

8 P1.2

7 P1.3

11 P0.3/K3

TCLO1/K0

TCLO1/K1

BUZ/K2

BUZ/K3

INT0
INT1
INT2
INT4

CLO

TCL1

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PRODUCT OVERVIEW S3C72G9/P72G9

Table 1-1. S3C72G9 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share Pin

K0–K3 I/O External interrupt (triggering edge is selectable) 14–11 P0.0–P0.3
V

DD

V

SS

RESET

– Main power supply 15 –
– Ground 16 –

I Reset signal 22 –

CA, CB – Capacitor terminal for voltage boosting 4, 5 –
VCL1–VCL2

VCL3–VCL5
TEST2 I

X

X

,

IN

OUT

– LCD power supply 99–100

1–3

Test input (must be connected VSS)

– Crystal, ceramic or RC oscillator pins for system

6 –

18, 17 –

–

clock

XT

XT

,

IN

OUT

TEST1 I

NOTES

1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

2. Refer to chapter 16 for OTP version.

– Crystal oscillator pins for subsystem clock 20, 21 –

Test input (must be connected to VSS)

(2)

19 –

Table 1-2. Overview of S3C72G9 Pin Data

Pin Name Share Pins I/O Type Reset Value Circuit Type

P0.0–P0.3

TCLO1/K0, TCLO1/K1

I/O Input E-2

BUZ/K2, BUZ/K3
P1.0–P1.3 INT0, INT1, INT2, INT4 I/O Input E-2
P2.0–P2.1 CLO, TCL1 I/O Input E-2
P2.2–P2.3 – I/O Input E-2
COM0–COM15 – O Low H-6
SEG0–SEG55 – O Low H-6
V

DD

V

SS

RESET

– – – –
– – – –
– I – B

CA – – – –
CB – – – –
VLC1–VLC5 – – – –
X

XT

X

,

IN

OUT

XT

,

IN

OUT

– – – –
– – – –

TEST1, 2 – I – –

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S3C72G9/P72G9 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

V

DD

P-Channel

In

N-Channel

Figure 1-3. Pin Circuit Type A

Data

Output

Disable

VLC1

PNE

Schmitt Trigger

VDD

Figure 1-5. Pin Circuit Type E-2

Pull-up
Resistor

Resistor
Enable

I/O

VDD

Pull-up Resistor

IN

Schmitt Trigger

Figure 1-4. Pin Circuit Type B

VLC2

VLC3/VLC4

SEG/COM Data

VLC3/VLC4

VLC5

VSS

Figure 1-6. Pin Circuit Type H-6

Out

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S3C72G9/P72G9 ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C72G9 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Battery level detector characteristics
— Voltage booster characteristics
— A.C. electrical characteristics
— Operating voltage range

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request

Miscellaneous Timing Waveforms

— A.C timing measurement point
— Clock timing measurement at X
— Clock timing measurement at XT
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts

IN

IN

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