Samsung S3C7235, S3C7238, S3P7235, S3P7238 Datasheet

S3C7238/P7238/C7235/P7235 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7238/C7235 offer an excellent design solution for a wide variety of applications that require LCD functions.

Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C7238/C7235's advanced CMOS technology provides for low power consumption and a wide operating voltage range.

OTP

The S3C7238/C7235 microcontroller is also available in OTP (One Time Programmable) version, S3P7238/P7235. S3P7238/P7235 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7238/P7235 is comparable to S3C7238/C7235, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C7238/P7238/C7235/P7235

FEATURES

Memory

– 512 × 4-bit RAM – 8 K × 8-bit ROM (S3C7238/P7238) – 16 K × 8-bit ROM (S3C7235/P7235)

I/O Pins

– Input only: 8 pins – I/O: 24 pins – Output: 8 pins sharing with segment driver

outputs

LCD Controller/Driver

– Maximum 16-digit LCD direct drive capability – 32 segment, 4 common pins – Display modes: Static, 1/2 duty (1/2 bias),

1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

– Programmable interval timer – Watchdog timer

8-Bit Timer/Counter 0

– Programmable 8-bit timer – External event counter – Arbitrary clock frequency output – Serial I/O interface clock generator

Watch Timer

Bit Sequential Carrier

– Support 16-bit serial data transfer in arbitrary

format

Interrupts

– Three internal vectored interrupts – Three external vectored interrupts – Two quasi-interrupts

Memory-Mapped I/O Structure

– Data memory bank 15

Two Power-Down Modes

– Idle mode (only CPU clock stops) – Stop mode (main or sub system oscillation stops)

Oscillation Sources

– Crystal, ceramic, or RC for main system clock – Crystal or external oscillator for subsystem clock – Main system clock frequency: 4.19 MHz (typical) – Subsystem clock frequency: 32.768 kHz – CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

– 0.95, 1.91, 15.3 µs at 4.19 MHz (main) – 122 µs at 32.768 kHz (subsystem)

– Real-time and interval time measurement – Four frequency outputs to BUZ pin – Clock source generation for LCD

8-Bit Serial I/O Interface

– 8-bit transmit/receive mode – 8-bit receive only mode – LSB-first or MSB-first transmission selectable – Internal or external clock source

1-2

Operating Temperature

– – 40 °C to 85 °C

Operating Voltage Range

– 1.8 V to 5.5 V

Package Type

– 80-pin QFP

S3C7238/P7238/C7235/P7235 PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.3/TCL0

P2.0/TCLO0

P4.0-P4.3

P5.0-P5.3

P6.0-P6.3/

KS0-KS3

P7.0-P7.3/

KS4-KS7

P8.0-P8.7/

SEG24-SEG31

INT0, INT1,INT2

8-Bit Timer/

Counter 0

I/O Port 3

I/O Port 4

I/O Port 6

I/O Port 7

I/O Port 8

Watch-Dog

Timer

X

IN

RESET

Interrupt

Control

Block

Internal

Interrupts

Instruction Decoder

Arithmetic and Logic Unit

XT

IN

Clock

X

XT

OUT

Basic Timer

Instruction

Register

4-Bit

Accumulator

Program

Counter

Program

Status Word

FLAGS

Stack

Pointer

Watch

Timer

P2.3/BUZ

LCD Drive/

Controller

I/O Port 0

Input Port 1

I/O Port 2

I/O Port 3

BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23

P8.0-P8.7/ SEG24-SEG31

P0.0/INT4 P0.1/SCK P0.2/SO P0.3/SI

P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0

P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ

P3.0/LCDCK P3.1/LCDSY P3.2 P3.3

P0.1 /SCK

Serial I/O

Port

P0.2 /SO

512 x 4-Bit

Data

Memory

8/16-Kbyte

Program

Memory

Figure 1-1. S3C7238/C7235 Simplified Block Diagram

P0.3 /SI

1-3

PRODUCT OVERVIEW S3C7238/P7238/C7235/P7235

PIN ASSIGNMENTS

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1

SDAT / SCLK

V

TEST

RESETRESET

SEG2 SEG1

SEG0 COM0 COM1 COM2 COM3

BIAS VLC0 VLC1

/ VLC2

/ VDD

DD

/ VSS

V

SS

/ TEST

XTout

/

RESET

P0.0/INT4

P0.1/SCK

P0.2/SO

P0.3/SI

P1.0/INT0

Xout

Xin

XTin

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S3C7238 S3C7235

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

1-4

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

P1.1/INT1

P1.2/INT2

P1.3/TCL0

P2.1

P2.2/CLO

P2.0/TCLO0

P2.3/BUZ

P3.2

P3.3

P3.0/LCDCK

P3.1/SCDSY

P4.0

P4.1

P4.2

P4.3

P5.0

Figure 1-2. S3C7238/C7235 80-QFP Pin Assignment Diagram

S3C7238/P7238/C7235/P7235 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C7238/C7235 Pin Descriptions

Pin Name Pin

Type

P0.0 P0.1 P0.2 P0.3

P1.0

I I/O I/O

I

I 4-bit input port.

P1.1 P1.2 P1.3

P2.0

I/O 4-bit I/O port.

P2.1 P2.2 P2.3

P3.0

I/O 4-bit I/O port.

P3.1 P3.2 P3.3

4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable.

1-bit and 4-bit read/write and test are possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software

Description Number Share

20 21 22 23

24 25 26 27

28 29 30 31

32 33

INT4

SCK

SO SI

INT0 INT1 INT2 TCL0

TCLO0 – CLO BUZ

LCDCK

LCDSY 34 35

Reset Value

Circuit

Type

Input A-1

D D

A-1

Input A-1

Input D

assignable.

P4.0– P4.3 P5.0– P5.3

I/O 4-bit I/O ports. N-channel open-drain output up

to 5 V. 1-, 4-, and 8-bit read/write and test are possible. Ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up

36–43 – Input E

resistors are software assignable.

P6.0– P6.3 P7.0– P7.3

I/O 4-bit I/O ports. Port 6 pins are individually

software configurable as input or output. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. Ports

44–51 KS0–KS3

KS4–KS7

Input

D

6 and 7 can be paired to enable 8-bit data transfer.

P8.0– P8.7

SEG0– SEG23

SEG24–

O Output port for 1-bit data (for use as CMOS

driver only)

O LCD segment signal output 3–1,

59–52 SEG24–

SEG31

– Output H-15

Output H-16

80–60

O LCD segment signal output 59–52 P8.0–P8.7 Output H-16

SEG31 COM0–

O LCD common signal output 4–7 – Output H-15

COM3 V

LC0–VLC2

– LCD power supply. Voltage dividing resistors

are assignable by mask option

9–11 SCLK

SDAT

– –

BIAS – LCD power control 8 – – – LCDCK I/O LCD clock output for display expansion 32 P3.0 Input D

* *

*

1-5

PRODUCT OVERVIEW S3C7238/P7238/C7235/P7235

Table 1-1. S3C7238/C7235 Pin Descriptions (Continued)

Pin Name Pin

Type

LCDSY I/O LCD synchronization clock output for LCD

Description Number Share

33 P3.1 Input D

Reset Value

Circuit

Type

display expansion TCL0 I/O External clock input for timer/counter 0 27 P1.3 Input A-1 TCLO0 I/O Timer/counter 0 clock output 28 P2.0 Input D SI I Serial interface data input 23 P0.3 Input A-1 SO I/O Serial interface data output 22 P0.2 Input

SCK

INT0 INT1

I/O Serial I/O interface clock signal 21 P0.1 Input

I External interrupts. The triggering edge for

INT0 and INT1 is selectable. Only INT0 is

24 25

P1.0 P1.1

Input A-1

D D

synchronized with the system clock. INT2 I Quasi-interrupt with detection of rising edge

26 P1.2 Input A-1

signals. INT4 I External interrupt input with detection of rising

20 P0.0 Input A-1

or falling edge KS0–KS7 I/O Quasi-interrupt inputs with falling edge

44–51 P6.0–P7.3 Input

D

detection. CLO I/O CPU clock output 30 P2.2 Input D BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer

31 P2.3 Input D

sound with 4.19 MHz main system clock or

32.768 kHz subsystem clock.

X

IN,

X

OUT

XT

IN,

XT

OUT

V

DD

V

SS

RESET

TEST –

– Crystal, ceramic or RC oscillator pins for main

15,14 – – – system clock. (For external clock input, use XIN and input XIN‘s reverse phase to X

– Crystal oscillator pins for subsystem clock.

OUT

)

17,18 – – – (For external clock input, use XTIN and input

XTIN's reverse phase to XT

OUT

)

– Main power supply 12 – – – – Ground 13 – – – – Reset signal 19 – Input B

Test signal input (must be connected to VSS)

16 – – –

* *

*

NOTES:

1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

2. D * Type has a schmitt trigger circuit at input.

1-6

S3C7238/P7238/C7235/P7235 PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

IN

Figure 1-3. Pin Circuit Type A

V

DD

PULL-UP RESISTOR

P-CHANNEL

N-CHNNEL

RESISTOR ENABLE

DATA

OUTPUT DISABLE

Figure 1-5. Pin Circuit Type C

RESISTOR

ENABLE

V

DD

P-CHANNEL

N-CHANNEL

V

DD

PULL-UP RESISTOR

P-CHANNEL

OUT

IN

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3)

DATA

OUTPUT

DISABLE

CIRCUIT

TYPE C

CIRCUIT TYPE A

Figure 1-6. Pin Circuit Type D

(P0.1, P0.2, P2, P3, P6, P7)

I/O

1-7

PRODUCT OVERVIEW S3C7238/P7238/C7235/P7235

RESISTOR

V

DD

PNE

DATA

P-CH

PULL-UP

V

DD

RESISTOR

ENABLE I/O

V

DD

V

LC0

V

LC1

OUTPUT

N-CH

ENABLE

CIRCUIT TYPE A

Figure 1-7. Pin Circuit Type E (P4, P5)

V

LC0

V

LC1

LCD SEGMENT/ COMMON DATA

V

LC2

OUT

LCD SEGMENT/ & PORT 8 DATA

V

LC2

Figure 1-9. Pin Circuit Type H-16 (P8)

V

DD

IN

OUT

Figure 1-8. Pin Circuit Type H-15 (SEG/COM)

1-8

SCHMITT TRIGGER

Figure 1-10. Pin Circuit Type B (RESETRESET)

S3C7238/P7238/C7235/P7235 ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7238/C7235 electrical characteristics is presented as tables and graphics. The information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — A.C. electrical characteristics — Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point — Clock timing measurement at X

— Clock timing measurement at XT — TCL timing — Input timing for RESET

— Input timing for external interrupts — Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request

IN

14-1

ELECTRICAL DATA S3C7238/P7238/C7235/P7235

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Units

Supply Voltage Input Voltage Output Voltage Output Current High

V

DD

I

V V

I1 O

OH

All I/O ports

One I/O pin active – 15 mA

– – 0.3 to + 6.5 V

– 0.3 to V

–

– 0.3 to VDD + 0.3

DD

+ 0.3

All I/O ports active – 35

Output Current Low

I

OL

One I/O pin active + 30 (Peak value)

(note)

+ 15

Total value for ports 0, 2, 3, and 5 + 100 (Peak value)

(note)

+ 60

Total value for ports 4, 6, and 7 + 100

(note)

+ 60

Operating Temperature Storage Temperature

T

A

T

stg

– – 40 to + 85 – – 65 to + 150

°

C

NOTE: The values for Output Current Low (IOL) are calculated as Peak Value × Duty .

Table 14-2. D.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Input high voltage

Input low voltage

Output high voltage

V

V V

V

V V V

OH1

IH1

IH2 IH3

IL1 IL2 IL3

All input pins except those specified below for V

IH2

, V

IH3

Ports 0, 1, 6, 7 and RESET XIN, X

OUT, XTIN

and XT

OUT

Ports 2, 3, 4 and 5 – – Ports 0, 1, 6, 7 and RESET

X

IN, XOUT, XTIN

and XT

OUT

VDD = 4.5 V to 5.5 V Ports 0, 2, 3, 4, 5, 6, 7 and BIAS

0.7 V

0.8 V

V

DD

– 0.1

–

– –

– – – – 0.1

V

DD

– 1.0

– – V

V

DD

V

DD

V

DD

0.3 V

0.2 V

DD DD

IOH = – 1 mA

V

OH2

VDD = 4.5 V to 5.5 V

V

DD

– 2.0

– –

Port 8 ONLY IOH = – 100 µA

V

14-2

S3C7238/P7238/C7235/P7235 ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

Parameter Symbol Conditions Min Typ Max Units

Output low voltage

V

OL1

V

= 4.5 V to 5.5 V, Ports 0, 2–7

DD

IOL = 15 mA

– 0.4 2 V

Input high leakage current

Input low leakage current

Output high leakage current

Output low leakage current

Pull-up resistor

LCD voltage dividing resistor

COM output impedance SEG output impedance

V

OL2

V

DD

IOL = 100 µA

I

LIH1

VIN = V All input pins except those specified

below for I

I

LIH2

VIN = V XIN, X

I

LIL1

V

IN

All input pins except XIN, X XT

IN and

I

LIL2

V

IN

XIN, X

I

LOH1

V

OUT

All output pins

I

LOL

V

OUT

All output pins

R

L1

R

L2

R

LCD TA = 25

R

COM

Ports 0–7 V

IN

V

DD

V

IN

V

DD

VDD = 5 V VDD = 3 V

R

SEG

VDD = 5 V VDD = 3 V

= 4.5 V to 5.5 V, Port 8 only

DD

LIH2

DD

OUT, XTIN and

= 0 V

XT

OUT

= 0 V

, XT

OUT

= V

DD

IN and

XT

OUT

OUT,

OUT

= 0 V

= 0 V; V

DD

= 5 V

= 3 V

= 0 V; V

= 5 V, RESET

DD

= 3 V

°

C

– – 1

– – 3 µA

– – 20

– – – 3

– 20

– – 3 µA

– 3

25 47 100

50 95 200

100 220 400 200 450 800

50 93 140

– 3 6

5 15 3 6 5 15

KΩ

COM output voltage deviation

SEG output voltage deviation

VDC

VDS

VDD = 5 V (VLC0 – COMi) Io = ± 15uA (I = 0–3)

VDD = 5 V (VLC0-SEGi) Io = ± 15µA (I = 0–31)

–

± 45 ± 90

ñ 45 ñ 90

mV

14-3