Samsung ML-1450 Block Diagram

Block Diagram

6-1

Samsung Electronics

6. Block Diagram

OSC.

48 MHz

USB

INTERFACE IC

(USBN9602)

USB

INTERFACE

PARALLEL

INTERFACE

SPGPe

(KS32C61100)

OSC.

20MHz

POWER

ON RESET

PROGRAM ROM

(FLASHMEMORY)

512K*16b*2EA

FONT ROM

(MASK ROM)

512K*16b*2EA

DATA ROM

(DRAM)

1M*16b*2EA

SIMM

(Up to 64MB)

(Option)

Post Script 3

(Flash : 2MB

Font : 2MB)

(Option)

RAS
CAS

MA
MD

RCS
RD
WR

IOCS

PLL

Reset & W D T

Generation

ROM/SRAM/
FLASH ROM

Control

(4 Bank)

I/O

Control

(5 Bank)

Interrupt

Control

(4 External)

Timer

(3 CH)

Tone

Generator

Engine

Comm. I/F

RAM : 512B

GPIO

VIS

CPU Bus

Interface

Blo c k

Systerm Bus

Interface

Block

[Arbiter]

EDO / FPM

DRAM
Control

(4Bank)

A/D Bus

CPU Addr BUS

CPU DATA BUS

Sys Addr BUS

Sys Data BUS

Sys Cntl BUS

ARM 7TDM I
Cache 8 KB

ADC

UART
(3CH)

JBIG

RAM

512B + 512B

OSC.(Video)

53.0109277MHz

/CS,/RD,/WR

NETWORK

INTERFACE

(Option)

SYSTEM DATA BUS
SYSTEM ADDR. BUS

CPU DATA BUS
CPU ADDR. BUS

I / O

INTERFACE

74HC245*2EA
74LS273*3EA

THERM STOR

ADC INPUT
THV READ

ADC INPUT

[ COVER OPEN SWITCH ]

[ LASER DIODE ON/OFF SWITCH ]

SMPS

SUPPLY 5V to each ICS

24V

5V

24VS

SUPPLY 24V to

Motor/HVPS/FAN/LSUA

Laser Diode Vcc

on LSU

LRAM :1296B
CXRAM :256B

PANEL INTERCACE
MOTOR CONTROL

NV RAM INTERCACE

SENSORS INPUT

SOLENOID CONTROL

FAN/PTL CONTROL

SCF INTERFACE

FUSER CONTROL

HVPS CONTROL

LSU INTERFACE

G E U

P V C

P P I

HPVC

HCT

D M A C

(2 CH)