Preliminary
RT9262/A
High Efficiency, Low Supply Current,
Step-up DC/DC Converter
General Description
The RT9262/A is a compact, high efficient, step-up
DC/DC converter with an adaptive current mode
PWM control loop, providing a stable and high
efficient operation over a wide range of load
currents. It operates in both continuous and
discontinuous current modes in stable waveforms
without external compensation.
The low start-up input voltage below 1V makes
RT9262/A suitable for 1 to 4 battery cell applications
providing up to 400mA output current. The 550KHz
high switching rate minimized the size of external
components. Besides, the 17µA low quiescent
current together with high efficiency maintains long
battery lifetime.
The 1.8V to 5V output voltage is set with 2 external
resistors. Both internal 2A switch and driver for
driving external power devices (NMOS or NPN) are
provided.
A 300mA LDO is included in RT9262 to provide a
secondary low noise output as well as an output
current stop in the shutdown mode. Similarly, a 1.8V
to 5V LDO output voltage can be set with 2 external
resistors. For RT9262A, a low battery detector with
0.86V detection voltage is included. RT9262/A are
provided in SOP-8 packages.
Ordering Information
RT9262A
Package type
S : SOP-8
Operating temperature range
C: Commercial standard
A : Include low battery detector
Default : Include LDO
Features
z
1.0V Low Start-up Input Voltage
z
High Supply Capability to Deliver 3.3V 100mA
with 1V Input Voltage
z
17µµµµA Quiescent (Switch-off) Supply Current
z
90% Efficiency
z
550KHz Fixed Switching Rate
z
Providing Flexibility for Using Internal and
External Power Switches
z
Built-in 300mA LDO, also for the Zero-Output-
Current Shutdown Mode (RT9262)
z
Boost DC-DC Integrating LDO for Up-Down
Regulation (RT9262)
z
Built-in 0.86V Voltage Detector (RT9262A)
z
8-Pin SOP Package
Applications
PDA
z
Portable Instrument
z
Wireless Equipment
z
DSC
z
LCD Back Bias Circuit
z
RF-Tags
z
Pin Configurations
Part Number Pin Configurations
RT9262CS
(Plastic SOP-8)
LDOO
RT9262ACS
(Plastic SOP-8)
GND
EXT
LFB
GND
EXT
LBO
LBI
TOP VIEW
1
2
3
4
TOP VIEW
1
2
3
4
CE
8
LX
7
VDD
6
FB
5
CE
8
LX
7
VDD
6
FB
5
DS9262/A-03 July 2001 www.richtek-ic.com.tw
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RT9262/A
Marking Information
Part Number Marking
RT9262CS RT9262CS
RT9262ACS RT9262ACS
Typical Application Circuit
V
IN
Preliminary
100µF
100pF
R1
1.6M
R2
980K
C2
1µF
2.5V
V
OU T2
C3
10µF
VDD
CE
R4
1.3M
+
R3
680K
LDOO LX
1nF
LFB GND FB
RT9262
EXT
Fig. 1 RT9262 Typical Application for Portable Instruments below 400mA
V
IN
R1
1.6M
R2
L1
4.7µH
C2
1µF
Low Battery
Warning Output
(Open Collector)
VDD
CE
LBO LX
R4
LBI GND FB
R3
RT9262A
100pF
EXT
980K
L1
4.7µH
D1
D1
+
+
100µF
C1
100µF
3.3V
V
OU T1
C1
100µF
3.3V
V
OU T1
Fig. 2 RT9262A Typical Application for Portable Instruments below 400mA
www.richtek-ic.com.tw DS9262/A-03 July 2001
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Preliminary
V
IN
RT9262/A
100µF
Chip Ena bl e I np ut
3.3V
V
OU T
+
C3
10µF
VDD
CE
LDOO LX
LFB GND FB
RT9262
EXT
100pF
980K
R1
1.6M
R2
L1
4.7µH
C2
1µF
Fig. 3 Application Circuit with Zero-Output-Current Shutdown Mode Control
V
IN
2.5V
V
OU T2
C3
10µF
R1
VDD
CE LX
R4
1.3M
+
R3
680K
LDOO EXT
1nF
LFB GND FB
RT9262
100pF
980K
1.6M
R2
L1
4.7µH
Q1
NMOS
C2
1µF
D1
D1
+
+
C1
100µF
100µF
3.3V
V
OU T1
C1
100µF
Fig. 4 0.4A ~ 2A Output Current Application
2.5V
V
OU T2
5V
V
C3
10µF
L1
IN
100µF
CE
R4
1.3M
+
R3
680K
LDOO LX
1nF
LFB GND FB
VDD
RT9262
10µH
EXT
0.05 ~0. 1
Q1
NMOS
0.1µF
Rm
Ω
D1
2.2M
200K
R1
R2
C2
1µF
+
15V
V
OU T1
C1
100µF
Fig. 5 High Voltage Application (Rm should be added when IL > 100mA)
DS9262/A-03 July 2001 www.richtek-ic.com.tw
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RT9262/A
Pin Description
Preliminary
Pin No.
Pin Name
RT9262 RT9262A
11GND
22EXT
3--LFB
4--LDOO
-- 3 LBO
-- 4 LBI
55FB
66VDD
77LX
88CE
Pin Function
Ground
Output pin for driving external NMOS or NPN
When driving an NPN, a resistor should be added for limiting base current.
Feedback pin of the built-in LDO (Internal Vref = 0.86V)
Voltage output pin of the built-in LDO
Drain output pin of the NMOS of the built-in low voltage detector
This pin will be internally pulled low when the voltage at LBI pin drops to
below 0.86V.
Input pin of the built-in low voltage detector
Trip point = 0.86V
Feedback input pin
Internal reference voltage for the error amplifier is 1.25V.
Input positive power pin of RT9262/A
Pin for switching
Chip enable
RT9262/A gets into shutdown mode when CE pin set to low.
Absolute Maximum Ratings
z Supply Voltage -0.3V to 6V
z LX Pin Switch Voltage -0.3V to (VDD + 0.8V)
z LDO Output Voltage -0.3V to (VDD + 0.3V)
z Other I/O Pin Voltages -0.3V to (VDD + 0.3V)
z LX Pin Switch Current 2.5A
z EXT Pin Driver Current 30mA
z LBO Current 30mA
z Power Dissipation, P
SOP-8 0.625W
• Package Thermal Resistance
SOP-8, θ
z Operating Junction Temperature 150°C
z Storage Temperature Range -65°C ~ +150°C
JA
@ TA = 25°C
D
160°C/W
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Preliminary
Electrical Characteristics
(VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units
RT9262/A
Start-UP Voltage
Operating VDD Range V
No Load Current I (VIN)
Switch-off Current I (VDD) I
Shutdown Current I (VIN)
Feedback Reference Voltage
Feedback Reference
Voltage for LDO
RT9262
LBI Pin Trip Point RT9262A
Switching Rate
Maximum Duty
LX ON Resistance
Current Limit Setting
EXT ON Resistance to VDD
EXT ON Resistance to GND
Line Regulation
Load Regulation
LDO PMOS ON Resistance RT9262
V
ST
DD
I
NO LOAD
SWITCH OFF
I
OFF
V
REF
V
REF
F
S
D
MAX
I
LIMIT
∆V
LINE
∆V
LOAD
IL = 1mA
Start-up to I
VIN = 1.5V, V
> 250µA
DD1
OUT
= 3.3V
VIN = 6V
CE Pin = 0V, VIN = 4.5V
Close Loop, VDD = 3.3V
Close Loop, VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V
VIN = 1.5 ~ 2.5V, IL = 1mA
VIN = 2.5V, IL = 1 ~ 100mA
VDD = 3.3V
-- 0.98 1.05 V
0.8 -- 6 V
-- 47 --
-- 17 --
-- 0.1 1
µA
µA
µA
1.225 1.25 1.275 V
0.843 0.86 0.877 V
0.843 0.86 0.877 V
-- 550 -- KHz
-- 92 -- %
-- 0.25 --
-- 2 --
-- 40 --
-- 30 --
-- 10 --
-- 0.25 --
-- 1
1.5
mV/V
mV/mA
Ω
A
Ω
Ω
Ω
LDO Drop Out Voltage RT9262
LBO ON Resistance RT9262A
CE Pin Trip Level
Temperature Stability for FB, LFB, LBI
Thermal Shutdown
Thermal Shutdown Hysterises
V
T
T
∆T
DROP
S
SD
SD
VDD = 3.3V, IL = 100mA
VDD = 3.3V
VDD = 3.3V
-- 70 -- mV
-- 40 --
0.2 0.8 1.4 V
Guaranteed by Design -- 50 --
Guaranteed by Design -- 165 --
Guaranteed by Design -- 10 --
Ω
ppm/
°C
°C
°C
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RT9262/A
Function Block Diagram
Preliminary
VDD
LDOO
LFB
FB
CE
VDD
LBI
LBO
FB
Q2
PMOS
Q2
NMOS
VDD
VDD
VDD
1.25V
R2
Q3
NMOS
1.25V
_
0.86V
+
_
L oop Control Circuit
+
Over Temp.
Detector
RT9262A
_
+
0.86V
_
L oop Control C ircuit
+
RT9262
EXT
LX
Q1
NMOS
R1
Shut Down
GND
EXT
LX
Q1
NMOS
CE
R2
Q3
NMOS
Over Temp.
Detector
R1
Shut Down
GND
www.richtek-ic.com.tw DS9262/A-03 July 2001
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Typical Operating Charateristics
I
(
A)
I
(
A)
µ
Preliminary
RT9262/A
Efficiency
V
= 3.3V ; TA = 25°C
OUT
No Load Current
90
80
70
60
50
40
DD
30
20
10
Refer to Application Circuit Fig.1 and Fig.2
0
1 1.2 1.5 2 2.5 3
Input Voltage (V)
TA = 25°C
V
OUT
= 3.3V
Efficiency
V
= 5.0V; TA = 25°C
OUT
No Load Current
140
120
100
80
60
DD
40
20
Refe r to Application Circuit Fig.1 and Fig.2
0
1 1.2 1.5 2 2.5 3 4
Input Voltage (V)
T
V
A
OUT
= 25°C
= 5.0V
1.4
Start Up Voltage
TA = 25°C
V
= 3.3V
OUT
1.3
1.2
1.1
1.0
Input Voltage (V)
0.9
Refer to Application Circuit Fig.1 and Fig.2
0.8
020406080100
I
(mA)
I
(mA) in constant resistance load
LOAD
LOAD
1.25
TA = 25°C
1.20
V
OUT
Refe r to Application Circuit Fig.1 and Fig.2
0 25 50 75 100
Input Voltage (V)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
Start Up Voltage
= 5.0V
I
I
(mA) in constant resistance load
LOAD
LOAD
(mA)
DS9262/A-03 July 2001 www.richtek-ic.com.tw
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RT9262/A
Application Note
Preliminary
Output Voltage Setting
Referring to application circuits Fig.1 to Fig.5, the
output voltage of the switching regulator (V
OUT1
) can
be set with Eq.1.
The LDO output voltage (V
of RT9262) can be
OUT2
set with Eq.2.
1OUT
2OUT ×+=
1R
1(V
2R
4R
1(V
3R
V25.1)
×+=
V86.0)
Eq.1
Eq.2
And trip point of the low battery detector is 0.86V at
LBI pin of RT9262A.
Feedback Loop Design
Referring to application circuits Fig.1 to Fig.5, The
selection of R1, R2, R3, and R4 based on the trade-
off between quiescent current consumption and
interference immunity is stated below:
• Follow Eq.1 and Eq.2.
• Higher R reduces the quiescent current (Path
current = 1.25V/R2, and 0.86V/R3), however
resistors beyond 5MΩ are not recommended.
• Lower R gives better noise immunity, and is less
sensitive to interference, layout parasitics, FB/LFB
node leakage, and improper probing to FB/LFB
pins.
• A proper value of feed forward capacitor parallel
with R1 (or R4) on Fig.1 to Fig.5 can improve the
noise immunity of the feedback loops, especially in
an improper layout. An empirical suggestion is
around 100pF ~ 1nF for feedback resistors of MΩ,
and 10nF ~ 0.1µF for feedback resistors of tens to
hundreds KΩ.
For applications without standby or suspend modes,
lower values of R1 to R4 are preferred. For
applications concerning the current consumption in
standby or suspend modes, the higher values of R1
to R4 are needed. Such “high impedance feedback
loops” are sensitive to any interference, which require
careful layout and avoid any interference, e.g.
probing to FB/LFB pins.
PRECAUTION 1: Improper probing to FB or LFB pin
will cause fluctuation at V
damage RT9262/A and system chips because V
OUT1
and V
OUT2
. It may
OUT1
may drastically rise to an over-rated level due to
unexpected interference or parasitics being added to
FB pin.
PRECAUTION 2: Disconnecting R1 or short circuit
across R2 may also cause similar IC damage as
described in precaution 1.
PRECAUTION 3: When large R values were used in
feedback loops, any leakage in FB/LFB node may
also cause V
OUT1
and V
voltage fluctuation, and
OUT2
IC damage. To be especially highlight here is when
the air moisture frozen and re-melt on the circuit
board may cause several µA leakage between IC or
component pins. So, when large R values are used in
feedback loops, post coating, or some other
moisture-preventing processes are recommended.
V
OU T1
Prober Parasitics
_
Q
+
R1
FB Pin
R2
Layout Guide
• A full GND plane without gap break.
• V
to GND noise bypass – Short and wide
OUT1
connection for C2 to Pin1 and Pin6.
• V
to GND noise bypass – Add a 100µF
IN
capacitor close to L1 inductor, when VIN is not an
idea voltage source.
• Minimized FB/LFB node copper area and keep
far away from noise sources.
• Minimized parasitic capacitance connecting to LX
and EXT nodes, which may cause additional
switching loss.
• The following diagram is an example of 2-layer
board layout for application circuits Fig.1 to Fig.4.
www.richtek-ic.com.tw DS9262/A-03 July 2001
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Preliminary
RT9262/A
RT9262/A
First Layer
Second Layer (Full GND Plane)
DS9262/A-03 July 2001 www.richtek-ic.com.tw
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RT9262/A
Package Information
B
J
Preliminary
H
A
M
F
C
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
8–Lead SOP Plastic Package
I
www.richtek-ic.com.tw DS9262/A-03 July 2001
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Preliminary
RT9262/A
DS9262/A-03 July 2001 www.richtek-ic.com.tw
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RT9262/A
Preliminary
RICHTEK TECHNOLOGY CORP.
Headquarter
6F, No. 35, Hsintai Road, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5510047 Fax: (8863)5537749
www.richtek-ic.com.tw DS9262/A-03 July 2001
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek-ic.com.tw
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