Richtek RT8015BGQW Schematic [ru]

3A, 2MHz, Synchronous Step-Down Converter

RT8015B

General Description

The RT8015B is a high efficiency synchronous, step down
DC/DC converter. Its input voltage range is from 2.6V to

5.5V and provides a n adjustable regulated output voltage
from 0.8V to 5V while delivering up to 3A of output current.

The internal synchronous low on resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The switching frequency is
set by an external resistor . The 100% duty cycle provides
low dropout operation extending battery life in portable
systems. Current mode operation with external
compensation allows the transient response to be
optimized over a wide range of loa ds and output ca pacitors.

The RT8015B is operated in forced continuous PWM Mode
which minimizes ripple voltage a nd reduces the noise and
RF interference.

The 100% duty cycle in Low Dropout Operation further
maximize battery life.

Features

zz

High Efficiency : Up to 95%

z

zz

zz

z Low R

zz

zz

z Programmable Frequency : 300kHz to 2MHz

zz

zz

z No Schottky Diode Required

zz

zz

z 0.8V Reference Allows for Low Output Voltage

zz

zz

z Forced Continuous Mode Operation

zz

zz

z Low Dropout Operation : 100% Duty Cycle

zz

zz

z Power Good Output Voltage Indicator

zz

zz

z RoHS Compliant and Halogen Free

zz

Internal Switches : 110m

DS(ON)

ΩΩ

Ω

ΩΩ

Applications

z Portable Instruments
z Battery-Powered Equipment
z Notebook Computers
z Distributed Power Systems
z IP Phones
z Digital Camera s

The RT8015B is available in the W DF N-10L 3x3 and SOP­8 (Exposed Pad) packages.

Ordering Information

RT8015B

Package Type
QW : WDFN-10L 3x3
SP : SOP-8 (Exposed Pad-Option 2)

Lead Plating System
G : Green (Halogen Free and Pb Free)

Note :
Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

GND

LX
LX

PGND

1
2
3
4
5

SHDN/RT

WDFN-10L 3x3

SHDN/RT

LX

2
3
4

GND

PGND

SOP-8 (Exposed Pad)

GND

10

COMP

9

FB

8

PGOOD

7

VDD

9

11

PVDD

8

COMP

7

FB

6

9

VDD

5

PVDD

Marking Information

For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.

DS8015B-04 March 2011 www.richtek.com

1

RT8015B

Typical Application Circuit

V

IN

5V

PGOOD

C

IN

22µF

R4
100k

R3
1

R

OSC

332k

C1

0.1µF

Note : Using all Ceramic Capacitors

Table 1. Recommended Component Selection

V

(V) R1 (kΩ) R2 (kΩ) R

OUT

3.3 750 240 30

2.5 510 240 27

1.8 300 240 22

1.5 210 240 18

1.2 120 240 15

1.0 60 240 13

6

PVDD

7

VDD

8

PGOOD

1

SHDN/RT

RT8015B

COMP

GND

PGND

COM P

2.2µH

3, 4

LX

9

FB

R

COMP

27k

10

2
5

(kΩ) C

L1

C

22pF

C

COMP

1nF

COM P

1
1
1
1
1
1

R1

F

510k

R2
240k

C

OUT

22µF x 2

(nF) L1 ( μH) C

2.2

2.2

2.2

2.2

1.0

1.0

V

OUT

2.5V/3A

(μF)

OUT

22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2

Functional Pin Description

Pin No.

WDFN

-10L 3x3

SOP-8

(Exposed Pad)

1 1 SHDN/RT

2 2 GND

3, 4 3 LX

5 4 PGND
6 5 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor.
7 6 VDD

8 -- PGOOD

9 7 FB

10 8 COMP

11 -- (Exposed Pad)

-- 9 GND

Pin Name Pin Function

Osc illator Resi stor Input . Con nectin g a r esis tor t o grou nd fr om t his
pin sets t he s w itc hi ng freq uency. For c in g th is pin t o VDD ca us es t he
device to be shu t down.
Signal Ground. All small signal components and compensation
comp onents shou ld co nne ct to thi s grou nd, whic h in tu r n con nec ts to
PGND at one point.
Inte rnal Power MO SFE T Swit ches Out put . Conne ct this pin to t he
inductor.
Power Ground . Conne ct thi s pin close to the neg ative term i nal of C
and C

OUT

.

Signal Input Supply. Decouple this pin to GND with a capacitor.
Normally V

is equal to PVDD.

DD

Power Good Indicator. T his pin is ope n drain logic output that is

pulled to gr ound when the output volt age is not within ±12.5% of

regulation point .
Feedback Pin. This pin receives the feedback voltage from a
resistive divid er connected across th e output.
Error Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. Connect external
compensation elements to this pin to stabilize the control loop.
No Internal Connection. The exposed pa d must b e soldered to a
l arge PC B and conn ected to GND for maximum power diss ipation.

The exposed pad must be soldered to a l arge PC B and conne c ted to
GND for maxi mum po wer dissipation.

IN

DS8015B-04 March 2011www.richtek.com

2

Function Block Diagram

RT8015B

SHDN/RT

COMP

FB

0.8V

POR

VDD

EA

Int-SS

SD

Output
Clamp

0.9V

0.7V

0.2V

OSC

ISEN

Slope
Com

OC

Limit

Driver

Control

Logic

NISEN

NMOS I Limit

OTP

V

REF

PVDD

LX

PGND

PGOOD

GND

Layout Guide

GND

C

V

V

F

IN

Bottom Layer

R3

C1

R4

PVDD

PGOOD

COMP

R1

OUT

R2

R

COMP

C

COMP

Place the feedback and
compensation components as
close to the IC as possible.

Place the input and output
capacitors as close to the
IC as possible.

GND

C

IN

RT8015B

6
7

VDD

8
9

FB

10

GND

5

PGND

4

LX

3

LX

2

GND

1

SHDN/RT

OUT

OUT

connected to Inductor

C

LX should be

V

by wide and short
trace, keep sensitive
components away

L1

from this trace

R

OSC

DS8015B-04 March 2011 www.richtek.com

3

RT8015B

Operation

Main Control Loop

The RT8015B is a monolithic, constant-frequency , current
mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-Channel
MOSFET) is turned on at the beginning of each clock
cycle. Current in the inductor increases until the peak
inductor current reach the value defined by the voltage on
the COMP pin. The error a mplifier adjusts the voltage on
the COMP pin by comparing the feedback signal from a
resistor divider on the FB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the COMP voltage until the
average inductor current matches the new load current.
When the top power MOSFET shuts off, the synchronous
power switch (N-MOSFET) turns on until either the bottom
current limit is rea ched or the beginning of the next clock
cycle.

The operating frequency is set by an external resistor
connected between the RT pin a nd ground. The practical
switching frequency can ra nge from 300kHz to 2MHz.

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by a dding a compensating ra mp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. In the RT8015B, however, separated inductor
current signals are used to monitor over current condition.
This keeps the maximum output current relatively constant
regardless of duty cycle.

Short Circuit Protection

When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. A
current runaway detector is used to monitor inductor
current. As current increa sing beyond the control of current
loop, switching cycles will be skipped to prevent current
runaway from occurring.

Dropout Operation

When the input supply voltage decrea ses toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually reaching 100% duty cycle.

The output voltage will then be determined by the input
voltage minus the voltage drop across the internal
P-Channel MOSFET a nd the inductor.

Low Supply Operation

The RT8015B is designed to operate down to an input
supply voltage of 2.6V. One important consideration at
low input supply voltages is that the R
P-Channel a nd N-Cha nnel power switches increase s. The
user should calculate the power dissipation when the
RT8015B is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.

DS(ON)

of the

DS8015B-04 March 2011www.richtek.com

4

RT8015B

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, VDD, PVDD ----------------------------------------------------------------------------−0.3V to 6V
z LX Pin Switch Voltage --------------------------------------------------------------------------------------------−0.3V to (PV DD + 0.3V)

<200ns --------------------------------------------------------------------------------------------------------------- −5V to 7.5V

z Other I/O Pin Voltages -------------------------------------------------------------------------------------------−0.3V to (VD D + 0.3V)
z LX Pin Switch Current --------------------------------------------------------------------------------------------4A
z Power Dissipation, P

SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------1.333W
WDFN-10L 3x3-----------------------------------------------------------------------------------------------------1.429W

z Package Thermal Resistance (Note 2)

SOP-8 (Exposed Pad), θJA-------------------------------------------------------------------------------------75°C/W
SOP-8 (Exposed Pad), θJC-------------------------------------------------------------------------------------15°C/W
WDFN-10L 3x3, θJA-----------------------------------------------------------------------------------------------70°C/W

WDFN-10L 3x3, θJC-----------------------------------------------------------------------------------------------8.2°C/W

z Junction T emperature--------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------260°C
z Storage T emperature Range ------------------------------------------------------------------------------------−65°C to 150°C
z ESD Susceptibility (Note 3)

HBM (Human Body Mode) --------------------------------------------------------------------------------------2kV
MM (Ma chine Mode)----------------------------------------------------------------------------------------------200V

@ TA = 25°C

D

Recommended Operating Conditions (Note 4)

z Supply Input V oltage----------------------------------------------------------------------------------------------2.6V to 5.5V
z Junction T emperature Range------------------------------------------------------------------------------------
z Ambient T emperature Range------------------------------------------------------------------------------------

−40°C to 125°C

−40°C to 85°C

Electrical Characteristics

(V

= 3.3V, T

DD

Input Volt age Ra nge VDD 2.6 -- 5.5 V
Feedback Reference Vol tage V
Feedback Leakage Current IFB -- 0.1 0.4 μA

DC Bias Cu rre nt

Out put Volta ge Line Regul at ion VIN = 2.7V to 5.5V -- 0.03 -- %/V
Out put Volta ge Load R egulation
Er ror A mp lifier

Transconductance

= 25°C, unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Unit

0.784 0.8 0.816 V

REF

Active , VFB = 0.78V, Not Swit ching -- 460 -- μA
Shutdown -- -- 1 μA

Me as ured in Se rv o Loop,
V

-- 800 -- μs

g

m

= 0.2V to 0.7V (Note 5)

COMP

−0.2

±0.02 0.2 %

Current Sense Transresistance RT -- 0.4 -- Ω
Switching Leakage Current SHDN/RT = VIN = 5. 5V -- -- 1 μA

To be continued

DS8015B-04 March 2011 www.richtek.com

5

RT8015B

Parameter Symbol Test Conditions Min Typ Max Unit

Swit c hi ng Freq uenc y

R

= 332k 0.8 1 1.2 MHz

OSC

Switching Frequency 0.3 -- 2 MHz
Switch On Resistance, High R
Switch On Resistance, Low

R

ISW = 0.5A -- 110 160 mΩ

PMOS

ISW = 0.5A -- 110 170 mΩ

NMOS

Power Good R ang e -- ±12 .5 ± 15 %
Power Good P ull -D ow n

Resistance
Peak Current Limit I

Under Voltage Lockout
Threshold

-- -- 120 Ω

3.2 3.8 -- A

LIM

V
V

Rising -- 2.4 -- V

DD

Falling -- 2.3 -- V

DD

Shutdown Threshold -- VIN − 0.7 VIN − 0.4 V

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization

is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of

JA

JEDEC 51-7 thermal measurement standard. The measurement case position of θ
packages.

and correlation with statistical process controls.

is on the exposed pad of the

JC

DS8015B-04 March 2011www.richtek.com

6

Typical Operating Characteristics

RT8015B

Efficiency vs. Load Current

100

90
80
70
60
50

Eff iciency (%)

40
30
20

0.01 0.1 1 10

VIN = 4.5V

VIN = 5.5V

VIN = 5V

Load Current (A)

Frequency vs. Temperature

1.08

1.06

1.04

1.02

Frequency (MHz)

1.00

0.98

VIN = 5V, V

-50 -25 0 25 50 75 100 125

Temperature

= 2.5V, I

OUT

(°C)

V

OUT

OUT

= 2.5V

= 0A

Output Voltage vs. Load Current

2.492

2.488

2.484

2.480

2.476

2.472

2.468

Output Voltage ( V)

2.464

2.460

2.456

0.00.51.01.52.02.53.0

Load Current (A)

Peak Current Limit vs. Input Voltage

5.0

4.5

4.0

3.5

3.0

Current Limit (A)

2.5

V

2.0

3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5

Input Vol tage (V)

OUT

VIN = 5V

= 2.5V

Quiescent Current vs. Input Voltage

450
440
430
420
410
400
390
380

Quiescent Current (uA)

370
360

2.5 3 3.5 4 4.5 5 5.5

Input Vol tage (V)

450

440

430

420

410

400

Quiescent Current (uA)

390

380

Quiescent Current vs. Temperature

VIN = 5V

-50-25 0 25 50 75100125

Temperature

(°C)

DS8015B-04 March 2011 www.richtek.com

7

RT8015B

3.34

3.32

3.30

3.28

3.26

Output V oltage ( V)

3.24

3.22

V

OUT_ac

(100mV/Div)

Output Voltage vs. Temperature

VIN = 5V

-50 -25 0 25 50 75 100 125

Temperature

(°C)

Load Transient Response

VIN = 5V, V
I

= 0A to 3A

OUT

OUT

= 2.5V

V

OUT

(1V/Div)

V

LX

(5V/Div)

I

LX

(5A/Div)

PGOOD

(5V/Div)

V

LX

(5V/Div)

UVP

VIN = 5V, V

Time (4μs/Div)

Output Ripple

OUT

= 1.05V

I

LOAD

(1A/Div)

V

IN

(5V/Div)

V

LX

(5V/Div)

V

OUT

(1V/Div)

PGOOD
(5V/Div)

Time (100μs/Div)

Start up with No Load

VIN = 5V, V

= 10.5V, I

OUT

OUT

= 0A

V

OUT_ac

(10mV/Div)

I

LX

(2A/Div)

V

IN

(5V/Div)

V

LX

(5V/Div)

V

OUT

(1V/Div)

PGOOD

(5V/Div)

VIN = 5V, V
I

OUT

OUT

= 3A

Time (400ns/Div)

Start up with Heavy Load

VIN = 5V, V

= 1.05V, I

OUT

= 2.5V

= 3A

OUT

Time (400μs/Div)

Time (400μs/Div)

DS8015B-04 March 2011www.richtek.com

8

Application Information

RT8015B

The basic R T8015B application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current a nd begins with
the selection of the inductor value and operating frequency
followed by CIN and C

OUT

.

Output Voltage Programming

The output voltage is set by an external resistive divider
according to the f ollowing equation :

R1

⎞

+×=

1VV

⎟

R2

⎠

where V

⎛
⎜

REFOUT

⎝

equals to 0.8V typical.

REF

The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.

V

OUT

R1

FB

RT8015B

GND

R2

Figure 1. Setting the Output Voltage

Soft-Start

The RT8015B contains an internal soft-start clamp that
gradually raises the clamp on the COMP pin. The full
current range becomes available on COMP after 2048
switching cycles as shown in Figure 2.

V

IN

(2V/Div)

Power Good Output

The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is 12.5% a bove
or 12.5% below its set voltage, PGOOD will be pulled
low. It is held low until the output voltage return s to within
the allowed tolerances once more. In soft start, PGOOD
is actively held low a nd is allowed to transition high until
soft start finished over and the output voltage reaches

87.5% of its set voltage.

Operating Frequency

Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequency improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance a nd/or capa cita nce to maintain
low output ripple voltage.

The operating frequency of the RT8015B is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing ca pacitor within the oscillator . The RT resistor value
can be determined by examining the frequency vs. RT
curve. Although frequencies a s high a s 2MHz are possible,
the minimum on-time of the RT8015B imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns. Therefore, the minimum duty cycle is
equal to 100 x 1 10ns x f(Hz).

2.5

RT = 152k for 2MHz

2

V

OUT

(500mV/Div)

I

LX

(1A/Div)

VIN = 5V, V

Time (1ms/Div)

Figure 2. Soft-Start

= 1.05V, I

OUT

OUT

= 2A

1.5

RT = 330k for 1MHz

1

Frequency ( M H z)

0.5

0

0 200 400 600 800 1000

R

(kٛ)

R

(kΩ)

OSC

OSC

Figure 3

DS8015B-04 March 2011 www.richtek.com

9

RT8015B

Inductor Selection

For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increa ses with higher VIN and decrea ses
with higher inductance.

V

⎡

I

=Δ

L

⎢

Lf

×

⎣

V

⎡

⎤

1

−

⎢

⎥

⎣

⎦

⎤

OUTOUT

⎥

V

IN

⎦

Having a lower ripple current reduces the ESR losses in
the output capa citors and the output voltage ri pple. Highest
efficiency operation is a chieved at low frequency with small
ripple current. This, however , requires a large inductor . A
reasonable starting point for selecting the ripple current
is ΔI = 0.4(I

). The largest ripple current occurs at the

MAX

highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :

L(MAX)

⎤

⎡

V

−

1

⎥

⎢

V

IN(MAX)

⎦

⎣

OUT

⎤
⎥

⎦

⎡

V

=

L

OUT

⎢

Δ×

If

⎣

Inductor Core Selection

Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and theref ore copper losses
will increa se.

Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which mean s that
inductance collapses abruptly when the peak design
current is exceeded.

This result in an abrupt increa se in inductor ri pple current
and consequent output voltage ri pple.

Do not allow the core to saturate!
Different core materials a nd sha pes will change the size/

current and price/current relationship of a n inductor. T oroid
or shielded pot cores in ferrite or permalloy materials are

small and don't radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs. size requirements and
any radi ated field/EMI requirements.

CIN and C

Selection

OUT

The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET. T o
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :

V

II

OUT(MAX)RMS

OUT

V

This formula has a maximum at VIN = 2V
I

RMS

= I

/2. This simple worst-case condition is

OUT

IN

V

V

IN

OUT

1

−=

, where

OUT

commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required.

Several cap acitors may also be paralleled to meet size or
height requirements in the design.

The selection of C

is determined by the effective series

OUT

resistance (ESR) that is required to mini mize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient re sponse as described in a later section.
The output ripple, ΔV

⎡

ESRIV

LOUT

⎢

⎣

, is determined by :

OUT

⎤

1

+Δ≤Δ

8fC

OUT

⎥

⎦

The output ripple is highest at maximum input voltage
since ΔIL increa ses with input voltage. Multiple ca pacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic a nd cera mic capa citors are
all available in surface mount pa ckages. Speci al polymer
ca pacitors offer very low ESR but have lower ca pa citance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but ca n be used in cost sensitive

10

DS8015B-04 March 2011www.richtek.com

RT8015B

application s provided that consideration is given to ripple
current ratings and long term relia bility. Cera mic ca pacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric ef fects.
The high Q of ceramic capacitors with trace inductance
can also lead to signif ica nt ringing.

Using Ceramic In put and Output Capacitors

Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR ma ke them ideal
for switching regulator a pplications. However , care must
be taken when these ca pacitors are used at the in put and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall ad a pter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.

Checking Tra n sient Re spon se

are the individual losses as a percentage of in put power .
Although all dissipative elements in the circuit produce
losses, two main sources usually account f or most of the
losses: VDD quiescent current and I2R losses.

The VDD quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
actual power lost is of no consequence.

1. The VDD quiescent current is due to two components :
the DC bi as current a s given in the electrical characteristics
and the internal main switch a nd synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each ti me the gate is switched from
high to low to high again, a packet of charge ΔQ moves
from VDD to ground. The resulting ΔQ/Δt is the current out
of VDD that is typically larger than the DC bi as current. In
continuous mode, I

GATECHG

= f(QT+QB) where QT and QB
are the gate charges of the internal top and bottom
switches.

The regulator loop response can be checked by looking
at the load transient respon se. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ΔI
resistance of C
discharge C

LOAD(ESR)

OUT

generating a feedback error signal used

OUT

by the regulator to return V
During this recovery time, V

immediately shifts by a n amount

OUT

, where ESR is the effective series

. ΔI

also begins to charge or

LOAD

to its steady state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability problem.
The COMP pin external components and output ca pa citor
shown in T ypical Application Circuit will provide adequate
compensation for most a pplication s.

Efficiency Considerations

The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency ca n be expressed as :

Both the DC bi as a nd gate charge losses are proportional
to VDD and thus their effects will be more pronounced at
higher supply voltages.

2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series re sistance
looking into the LX pin is a function of both top and bottom
MOSFET R

RSW = R

DS(ON)

and the duty cycle (D) as follows :

DS(ON)

TOP x D + R

BOT x (1"D) The R

DS(ON)

DS(ON)

for both the top and bottom MOSFETs can be obtained
from the Typical Perf ormance Characteristics curves. Thus,
to obtain I2R losses, simply add RSW to RL a nd multi ply
the result by the square of the average output current.
Other losses including CIN and C

ESR dissipative

OUT

losses and inductor core losses generally a ccount for less
than 2% of the total loss.

Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc.

DS8015B-04 March 2011 www.richtek.com

11

RT8015B

Current Limit

RT8015B ha s cycle by cycle current limiting control. The
current limit circuit employs a “peak” current sensing
algorithm. If the magnitude of the current sense signal is
above the current limit threshold, the controller will turn
off high side MOSFET and turn on low side MOSFET.

Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
25% of its set voltage threshold, the under voltage
protection circuit will be triggered to terminate switching
operation and the controller will be latched unless VDD
POR is detected again. During soft-start, the UVP will be
blanked until soft-start finish.

Thermal Considerations

For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and a mbient temperature. The
maximum power dissipation can be calculated by the
following formula :

The maximum power dissipation depends on the operating
ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8015B packages, the derating
curves in Figure 4 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Maximum Power Dissipation (W )

0.1

0.0

SOP-8 (Exposed Pad)

0 25 50 75 100 125

Ambient Temper atur e (°C)

WDFN-10L 3x3

Four-Layer PCB

Figure 4. Derating Curves f or RT8015B Package

Layout Considerations

Follow the PCB layout guidelines for optimal performa nce
of RT8015B.

P
where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, TA is

is the junction to ambient

JA

thermal resistance.
For recommended operating condition specifications of

the RT8015B, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For SOP-8
(Exposed Pad) packages, the thermal resistance, θJA, is
75°C/W on a standard JEDEC 51-7 f our-layer thermal test
board. For WDFN-10L 3x3 packages, the thermal
resistance, θJA, is 70°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formula s :

P

= (125°C − 25°C) / (75°C/W) = 1.333W for

D(MAX)

SOP-8 (Exposed Pad) package
P

= (125°C − 25°C) / (70°C/W) = 1.429W for

D(MAX)

W DF N-10L 3x3 pa ckage

` A ground pla ne is recommended. If a ground plane layer

is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.

` Connect the terminal of the input capacitor(s), C

IN

, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.

` LX node is with high frequency voltage swing and should

be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray cap acitive
noise pick-up.

` Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise
of powercomponents. Y ou can connect the copper area s
to any DC net (PV DD, V DD, VOUT, PGND, GND, or a ny
other DC rail in your system).

12

DS8015B-04 March 2011www.richtek.com

` Connect the FB pin directly to the feedback resistors.

The resistor divider must be connected between V
and GND.

Figure 5

OUT

RT8015B

Figure 6

DS8015B-04 March 2011 www.richtek.com

13

RT8015B

Recommended component selection for T ypical Application

Table 1. Inductors

Component

Supplier

TAIYO YUDEN NR 8040 2 9 7800 8x8x4

Component Supplier Part No. Capacitance (μF) Case Size

TDK C3225X5R0J226M 22 1210

TDK C2012X5R0J106M 10 0805
Panasonic ECJ4YB0J226M 22 1210
Panasonic ECJ4YB1A106M 10 1210

TAIYO YUDEN LMK325BJ226ML 22 1210
TAIYO YUDEN JMK316BJ226ML 22 1206
TAIYO YUDEN JMK212BJ106ML 10 0805

Series

Inductance (μH) DCR (mΩ) Current Rating

(mA)

Table 2. Capacitors for CIN and C

OUT

Dimensions

(mm)

14

DS8015B-04 March 2011www.richtek.com

Outline Dimension

RT8015B

D

E

A

A3

A1

D2

L

E2

SEE DETAIL A

1

2

e

b

1

1

2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Dimensions In Millimeters Dimensio ns In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 2.300 2.650 0.091 0.104

E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 10L DFN 3x3 Package

DS8015B-04 March 2011 www.richtek.com

15

RT8015B

H

M

EXPOSED THERMAL PAD
(Bottom of Package)

A

Y

J

F

I

B

X

C

D

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1

Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2

Y 3.000 3.500 0.118 0.138

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

Richtek Technology Corporation

Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8015B-04 March 2011www.richtek.com

16