Renesas g1a, rl78 User Manual

User’s Manual

A

RL78/G1

16

User’s Manual: Hardware

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.2.00 Jul 2013

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a

reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If

an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause

destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS

device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply

while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

How to Use This Manual

Readers This manual is intended for user engineers who wish to understand the functions of the

RL78/G1A and design and develop application systems and programs for these devices.

The target products are as follows.

• 25-pin: R5F10E8x (x = A, C, D, E)

• 32-pin: R5F10EBx (x = A, C, D, E)

• 48-pin: R5F10EGx (x = A, C, D, E)

• 64-pin: R5F10ELx (x = C, D, E)

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The RL78/G1A manual is separated into two parts: this manual and the instructions edition

(common to the RL78 Microcontroller).

RL78/G1A

User’s Manual

(This Manual)

• Pin functions

• Internal block functions

• Interrupts

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• To gain a general understanding of functions: → Read this manual in the order of the CONTENTS. The mark “<R>” shows major

revised points. The revised points can be easily searched by copying an “<R>” in the

PDF file and specifying it in the “Find what:” field.

• How to interpret the register format: → For a bit number enclosed in angle brackets, the bit name is defined as a reserved

word in the assembler, and is defined as an sfr variable using the #pragma sfr

directive in the compiler.

• To know details of the RL78G1A Microcontroller instructions: → Refer to the separate document RL78 Microcontroller Instructions User’s Manual

(R01US0015E).

• CPU functions

• Instruction set

• Explanation of each instruction

RL78 Microcontroller

User’s Manual

Instructions

Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representations: Binary

Decimal

Hexadecimal

...

×××× or ××××B

...

××××

...

××××H

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

RL78/G1A User’s Manual Hardware This manual

RL78 family User’s Manual: Software R01US0015E

Documents Related to Flash Memory Programming

Document Name Document No.

PG-FP5 Flash Memory Programmer User’s Manual R20UT0008E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

CHAPTER 1 OUTLINE

DD = 1.8 to 3.6 V, TA = -20 to +85°C)

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RL78/G1A CHAPTER 1 OUTLINE

DMA (Direct Memory Access) controller

• 2 channels

• Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks

Multiplier and divider/multiply-accumulator

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

Serial interface

• CSI: 2 to 6 channels

• UART/UART (LIN-bus supported): 2 or 3 channels

2

• I

C/Simplified I2C communication: 2 to 7 channels

Timer

• 16-bit timer: 8 channels

• 12-bit interval timer: 1 channel

• Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function)

• Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)

A/D converter

• 8/12-bit resolution A/D converter (V

• Analog input: 13 to 28 channels

• Internal reference voltage (1.45 V) and temperature sensor

I/O port

• I/O port: 19 to 56 (N-ch open drain I/O [withstand voltage of 6 V]: 2 to 4,

N-ch open drain I/O [V

• Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor

• Different potential interface: Can connect to a 1.8/2.5 V device

• On-chip key interrupt function

• On-chip clock output/buzzer output controller

Others

• On-chip BCD (binary-coded decimal) correction circuit

Notes 1. Can be selected only in HS (high-speed main) mode

2. Products with 25 to 48 pins

3. Products with 64 pins

Remark The functions mounted depend on the product. See 1.6 Outline of Functions.

DD = 1.6 to 3.6 V)

DD withstand voltage

Note 1

Note 2

/EVDD withstand voltage

Note 3

]: 6 to 12)

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RL78/G1A CHAPTER 1 OUTLINE

{ ROM, RAM capacities

Data flash

64 KB 4 KB

48 KB 4 KB 3 KB R5F10E8D R5F10EBD R5F10EGD R5F10ELD

32 KB 4 KB 2 KB R5F10E8C R5F10EBC R5F10EGC R5F10ELC

16 KB 4 KB 2 KB R5F10E8A R5F10EBA R5F10EGA

RAM

4 KB

Note

25 pins 32 pins 48 pins 64 pins

R5F10E8E R5F10EBE R5F10EGE R5F10ELE

Note

This is about 3 KB when the self-programming function and data flash function are used. (For details, see

CHAPTER 3)

RL78/G1A Flash ROM

−

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RL78/G1A CHAPTER 1 OUTLINE

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A

Part No. R 5 F 1 0 E L C A x x x F B # V 0

Packing

#U0 : Tray (HWQFN, VFBGA, WFLGA) #V0 : Tray (LFQFP) #W0 : Embossed Tape (HWQFN, VFBGA, WFLGA) #X0 : Embossed Tape (LFQFP)

Package type:

BG : VFBGA, 0.40 mm pitch FB

: LFQFP, 0.50 mm pitch

LA

: WFLGA, 0.50 mm pitch

NA : HWQFN, 0.50 mm pitch

ROM number (Omitted with blank products)

Classification:

A : Consumer applications : TA = −40˚C to 85˚C G : Industrial applications

: TA = −40˚C to 105˚C

ROM capacity:

A

: 16 KB

C

: 32 KB

D

: 48 KB

E

: 64 KB

Pin count:

8 : 25-pin B

: 32-pin G : 48-pin L

: 64-pin

RL78/G1A group

Memory type:

F : Flash memory

Renesas MCU

Renesas semiconductor product

Caution The part number above is valid as of when this manual was issued. For the latest part number, see the

web page of the target product on the Renesas Electronics website.

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RL78/G1A CHAPTER 1 OUTLINE

Table 1-1. List of Ordering Part Numbers

A

Note 2

A

G

A

G

A

G

A

G

A

Note 2

Note 1

R5F10E8AALA#U0, R5F10E8CALA#U0, R5F10E8DALA#U0, R5F10E8EALA#U0, R5F10E8AALA#W0, R5F10E8CALA#W0, R5F10E8DALA#W0, R5F10E8EALA#W0

R5F10E8AGLA#U0, R5F10E8CGLA#U0, R5F10E8DGLA#U0, R5F10E8EGLA#U0, R5F10E8AGLA#W0, R5F10E8CGLA#W0, R5F10E8DGLA#W0, R5F10E8EGLA#W0

R5F10EBAANA#U0, R5F10EBCANA#U0, R5F10EBDANA#U0, R5F10EBEANA#U0, R5F10EBAANA#W0, R5F10EBCANA#W0, R5F10EBDANA#W0, R5F10EBEANA#W0

R5F10EBAGNA#U0, R5F10EBCGNA#U0, R5F10EBDGNA#U0, R5F10EBEGNA#U0, R5F10EBAGNA#W0, R5F10EBCGNA#W0, R5F10EBDGNA#W0, R5F10EBEGNA#W0

R5F10EGAAFB#V0, R5F10EGCAFB#V0, R5F10EGDAFB#V0, R5F10EGEAFB#V0, R5F10EGAAFB#X0, R5F10EGCAFB#X0, R5F10EGDAFB#X0, R5F10EGEAFB#X0

R5F10EBAGNA#V0, R5F10EBCGNA#V0, R5F10EBDGNA#V0, R5F10EBEGNA#V0, R5F10EBAGNA#X0, R5F10EBCGNA#X0, R5F10EBDGNA#X0, R5F10EBEGNA#X0

R5F10EGAANA#U0, R5F10EGCANA#U0, R5F10EGDANA#U0, R5F10EGEANA#U0, R5F10EGAANA#W0, R5F10EGCANA#W0, R5F10EGDANA#W0, R5F10EGEANA#W0

R5F10EGAGNA#U0, R5F10EGCGNA#U0, R5F10EGDGNA#U0, R5F10EGEGNA#U0, R5F10EGAGNA#W0, R5F10EGCGNA#W0, R5F10EGDGNA#W0, R5F10EGEGNA#W0

R5F10ELCAFB#V0, R5F10ELDAFB#V0, R5F10ELEAFB#V0, R5F10ELCAFB#X0, R5F10ELDAFB#X0, R5F10ELEAFB#X0

R5F10ELCGFB#V0, R5F10ELDGFB#V0, R5F10ELEGFB#V0, R5F10ELCGFB#X0, R5F10ELDGFB#X0, R5F10ELEGFB#X0

R5F10ELCABG#U0, R5F10ELDABG#U0, R5F10ELEABG#U0, R5F10ELCABG#W0, R5F10ELDABG#W0, R5F10ELEABG#W0

R5F10ELCGBG#U0, R5F10ELDGBG#U0, R5F10ELEGBG#U0, R5F10ELCGBG#W0, R5F10ELDGBG#W0, R5F10ELEGBG#W0

Ordering Part Number

<R>

Pin count Package Fields of Application

25 pins

32 pins

25-pin plastic WFLGA (3 × 3 mm, 0.5 mm pitch)

G

32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)

<R>

48 pins

48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch)

<R>

48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch)

<R>

64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)

64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch)

For the fields of application, see

G

Figure 1-1 Part Number, Memory Size, and Package of RL78/G1A.

<R>

64 pins

Notes 1.

2. In planning

Caution The part number above is valid as of when this manual was issued. For the latest part number, see

the web page of the target product on the Renesas Electronics website.

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RL78/G1A CHAPTER 1 OUTLINE

1.3 Pin Configuration (Top View)

1.3.1 25-pin products

• 25-pin plastic WFLGA (3 × 3 mm, 0.50 mm pitch)

Top View

5

4

3

2

1

ABCDE EDCBA

Bottom View

INDEX MARK

A B C D E

SS

P40/TOOL0 RESET P03/ANI16/

5

P122/X2/ EXCLK

4

P121/X1 V

3

REGC

2

P60/SCLA0 P61/SDAA0 P31/ANI29/TI03/

1

A B C D E

P137/INTP0 P02/ANI17/

DD

SS P30/ANI27/

V

RxD1/TO00/ (KR1)

TxD1/TI00/ (KR0)

P21/ANI1/

REFM

AV

SCK11/SCL11/ INTP3

TO03/PCLBUZ0 /INTP4

P23/ANI3/ (KR3)

P22/ANI2/ (KR2)

P11/ANI20/ SI00/SDA00/ RxD0/ TOOLRxD

P51/ANI25/ SO11/INTP2

P12/ANI21/ SO00/TxD0/ TOOLTxD

AV

DD

AV

P10/ANI18/ SCK00/SCL00

P50/ANI26/ SI11/SDA11 INTP1

P20/ANI0/

REFP

AV

5

4

3

2

1

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1

μ

F).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

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RL78/G1A CHAPTER 1 OUTLINE

1.3.2 32-pin products

• 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)

<R>

P24/ANI4/(KR5)

P23/ANI3/(KR4) P22/ANI2/(KR3)

P21/ANI1/AV

P20/ANI0/AV

P03/ANI16/RxD1/TO00/(KR2)

P02/ANI17/TxD1/TI00/(KR1)

P120/ANI19/(KR0)

INDEX MARK

REFM

REFP

AVSSAVDDP10/ANI18/SCK00/SCL00/(KR0)

24 23 22 21 20 19 18 17

25 26 27 28 29 30 31 32

1 2 3 4 5 6 7 8

P40/TOOL0

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)

P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)

P13/ANI22/SO20/TxD2/(KR3)

P14/ANI23/SI20/SDA20/RxD2/(KR4)

P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)

exposed die pad

P51/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 P30/ANI27/SCK11/SCL11/INTP3 P70/ANI28/KR0 P31/ANI29/TI03/TO03/PCLBUZ0/INTP4 P62 P61/SDAA0 P60/SCLA0

RESET

P121/X1

P137/INTP0

P122/X2/EXCLK

SS

V

REGC

16 15 14 13 12 11 10

9

DD

V

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1

μ

F).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

3. It is recommended to connect an exposed die pad to V

ss.

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RL78/G1A CHAPTER 1 OUTLINE

1.3.3 48-pin products

• 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch)

REFP

REFM

P140/PCLBUZ0/INTP6

P02/ANI17/TxD1/TI00/(KR0)

P03/ANI16/RxD1/TO00/(KR1)

P130

P20/ANI0/AV

P21/ANI1/AV

P22/ANI2/(KR2)

P23/ANI3/(KR3)

P24/ANI4/(KR4)

P25/ANI5/(KR5)

P26/ANI6

P27/ANI7

P120/ANI19

P41/ANI30/TI07/TO07

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

V V

36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46

SS

DD

47 48

1 2 3 4 5 6 7 8 9 10 11 12

P62

P63

P60/SCLA0

P61/SDAA0

P73/SO01/KR3

24 23 22 21 20 19 18 17 16 15 14 13

P72/SO21/KR2

AV

SS

AV

DD

P150/ANI8 P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1

P71/SI21/SDA21/KR1

P74/SI01/SDA01/INTP8/KR4

P31/ANI29/TI03/TO03/INTP4

P75/SCK01/SCL01/INTP9/KR5

P70/ANI28/SCK21/SCL21/KR0

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

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RL78/G1A CHAPTER 1 OUTLINE

• 48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch)

REFP

REFM

P140/PCLBUZ0/INTP6

P02/ANI17/TxD1/TI00/(KR0)

P03/ANI16/RxD1/TO00/(KR1)

P130

P20/ANI0/AV

P21/ANI1/AV

P22/ANI2/(KR2)

P23/ANI3/(KR3)

P24/ANI4/(KR4)

P25/ANI5/(KR5)

P26/ANI6

P27/ANI7

P120/ANI19

P41/ANI30/TI07/TO07

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

V V

36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46

SS

DD

47 48

1 2 3 4 5 6 7 8 9 10 11 12

P62

P63

P60/SCLA0

P61/SDAA0

P73/SO01/KR3

24 23 22 21 20 19 18 17 16 15 14 13

P72/SO21/KR2

AV

SS

AV

DD

P150/ANI8 P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1

P71/SI21/SDA21/KR1

P74/SI01/SDA01/INTP8/KR4

P31/ANI29/TI03/TO03/INTP4

P75/SCK01/SCL01/INTP9/KR5

P70/ANI28/SCK21/SCL21/KR0

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 9 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.3.4 64-pin products

• 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)

P27/ANI7 P26/ANI6/(KR9) P25/ANI5/(KR8) P24/ANI4/(KR7) P23/ANI3/(KR6) P22/ANI2/(KR5)

P21/ANI1/AV

P20/ANI0/AV

P04/SCK10/SCL10/(KR4)

P03/ANI16/SI10/SDA10/RxD1/(KR3)

P02/ANI17/SO10/TxD1/(KR2)

P01/TO00/(KR1)

P00/TI00/(KR0) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6

REFM

REFP

P130

AVSSAVDDP150/ANI8

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P120/ANI19

P151/ANI9/(KR6)

P152/ANI10/(KR7)

P153/ANI11/(KR8)

P43

RESET

P40/TOOL0

P42/TI04/TO04

P41/ANI30/TI07/TO07

P154/ANI12/(KR9)

P10/ANI18/SCK00/SCL00/(KR0)

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)

P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)

P13/ANI22/SO20/TxD2/(KR3)

P14/ANI23/SI20/SDA20/RxD2/(KR4)

P15/ANI24/SCK20/SCL20/(KR5)

P16/TI01/TO01/INTP5

P51/ANI25/SO11/INTP2

P50/ANI26/SI11/SDA11/INTP1

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

SS

DD

SS0

DD0

V

EV

REGC

P121/X1

P123/XT1

P137/INTP0

P122/X2/EXCLK

P124/XT2/EXCLKS

EV

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ P05/TI05/TO05/KR8 P06/TI06/TO06/KR9 P70/ANI28/SCK21/SCL21/KR0 P71/SI21/SDA21/KR1 P72/SO21/KR2 P73/SO01/KR3 P74/SI01/SDA01/INTP8/KR4 P75/SCK01/SCL01/INTP9/KR5 P76/INTP10/KR6 P77/INTP11/KR7 P31/ANI29/TI03/TO03/INTP4 P63 P62 P61/SDAA0 P60/SCLA0

Cautions 1. Make EVSS0 pin the same potential as VSS pin.

2. Make VDD pin the potential that is higher than EVDD0 pin.

3. Connect the REGC pin to Vss via a capacitor (0.47 to 1

μ

F).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. When using the microcontroller for an application where the noise generated inside the microcontroller

must be reduced, it is recommended to supply separate powers to the V

the V

SS and EVSS0pins to separate ground lines.

DD and EVDD0 pins and connect

3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 10 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

• 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch)

Top View Bottom View

8

7

6

5

4

3

2

1

ABCDEFGH

Index mark

HGFEDCBA

Pin No.

A1 P05/TI05/TO05/KR8 C1 P51/ANI25/SO11

A2 P30/ANI27/SCK11

/SCL11/INTP3 /RTC1HZ

A3 P70/ANI28/SCK21

/SCL21/KR0

A4 P75/SCK01/SCL01

/INTP9/KR5

A5 P77/INTP11/KR7 C5 P15/ANI24/SCK20

A6 P61/SDAA0 C6 P63 E6 P41/ANI30/TI07/TO07 G6 P02/ANI17/SO10/TxD1

A7 P60/SCLA0 C7 VSS E7 RESET G7 P00/TI00/(KR0)

A8 EVDD0 C8 P121/X1 E8 P137/INTP0 G8 P124/XT2/EXCLKS

B1 P50/ANI26 /SI11

/SDA11/INTP1

B2 P72/SO21/KR2 D2 P06/TI06/TO06/KR9 F2 P151/ANI9/(KR6) H2 P27/ANI7

B3 P73/SO01/KR3 D3 P12/ANI21/SO00

B4 P76/INTP10/KR6 D4 P14/ANI23/SI20/

B5 P31/ANI29/TI03/TO03

/INTP4

B6 P62 D6 P40/TOOL0 F6 P43 H6 P141/PCLBUZ1/INTP7

B7 VDD D7 REGC F7 P01/TO00/(KR1) H7 P140/PCLBUZ0/INTP6

B8 EVSS0 D8 P122/X2/EXCLK F8 P123/XT1 H8 P120/ANI19

Name Pin No.

C2 P71/SI21/SDA21/KR1 E2 P154/ANI12/(KR9) G2 P25/ANI5/(KR8)

C3 P74/SI01/SDA01

C4 P16/TI01/TO01/INTP5 E4 P11/ANI20/SI00

D1 P13/ANI22/SO20

D5 P42/TI04/TO04 F5 P04/SCK10/SCL10

/INTP2

/INTP8/KR4

/SCL20/(KR5)

/TxD2/(KR3)

/TxD0/TOOLTxD/(KR2)

SDA20/RxD2/(KR4)

Name Pin No. Name Pin No.

E1 P153/ANI11/(KR8) G1 AVDD

E3 P10/ANI18/SCK00

/SCL00/(KR0)

/SDA00/RxD0 /TOOLRxD/(KR1)

E5 P03/ANI16/SI10

/SDA10/RxD1/(KR3)

F1 P150/ANI8 H1 AVSS

F3 P152/ANI10/(KR7) H3 P26/ANI6/(KR9)

F4 P21/ANI1/AVREFM H4 P23/ANI3/(KR6)

/(KR4)

G3 P24/ANI4/(KR7)

G4 P22/ANI2/(KR5)

G5 P130

/(KR2)

H5 P20/ANI0/AVREFP

Name

Cautions 1. Make EVSS0 pin the same potential as VSS pin.

2. Make V

DD pin the potential that is higher than EVDD0 pin.

3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. When using the microcontroller for an application where the noise generated inside the microcontroller

must be reduced, it is recommended to supply separate powers to the V

the V

SS and EVSS0 pins to separate ground lines.

DD and EVDD0 pins and connect

3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O

redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 11 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.4 Pin Identification

ANI0 to ANI12,

ANI16 to ANI30: Analog input

AV

DD: Analog power supply

AV

SS: Analog ground

AV

REFM: A/D converter reference

potential (− side) input

AV

REFP: A/D converter reference

potential (+ side) input

EV

DD0: Power supply for port

EV

SS0: Ground for port

EXCLK: External clock input (main

system clock)

EXCLKS: External clock input

(subsystem clock)

INTP0 to INTP11: Interrupt Request from

External

KR0 to KR9: Key return

P00 to P06: Port 0

P10 to P16: Port 1

P20 to P27: Port 2

P30, P31: Port 3

P40 to P43: Port 4

P50, P51: Port 5

P60 to P63: Port 6

P70 to P77: Port 7

P120 to P124: Port 12

P130, P137: Port 13

P140, P141: Port 14

P150 to P154: Port 15

PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer

output

REGC: Regulator capacitance

RESET: Reset

RTC1HZ: Real-time clock correction clock

(1 Hz) output

RxD0 to RxD2: Receive data

SCK00, SCK01, SCK10,

SCK11, SCK20, SCK21: Serial clock input/output

SCLA0, SCL00, SCL01,

SCL10, SCL11, SCL20,

SCL21: Serial clock output

SDAA0, SDA00, SDA01,

SDA10, SDA11, SDA20,

SDA21: Serial data input/output

SI00, SI01, SI10, SI11,

SI20, SI21: Serial data input

SO00, SO01, SO10,

SO11, SO20, SO21: Serial data output

TI00, TI01, TI03 to TI07: Timer input

TO00, TO01,

TO03 to TO07: Timer output

TOOL0: Data input/output for tool

TOOLRxD, TOOLTxD: Data input/output for external device

TxD0 to TxD2: Transmit data

V

DD: Power supply

VSS: Ground

X1, X2: Crystal oscillator (main system clock)

XT1, XT2: Crystal oscillator (subsystem clock)

R01UH0305EJ0200 Rev.2.00 12 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.5 Block Diagram

1.5.1 25-pin products

TI00/P02

TO00/P03

TI03/TO03/P31

TIMER ARRAY UNIT (8ch)

ch0

ch1

ch2

ch3

ch4

ch5

ch6

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

2

3

4

2

P02, P03

P10 to P12

P20 to P23

P30, P31

P40

P50, P51

P60, P61

LOW-SPEED

ON-CHIP

OSCILLATOR

RxD0/P11 TxD0/P12

RxD1/P03 TxD1/P02

SCK00/P10

SI00/P11

SO00/P12

SCK11/P30

SI11/P50

SO11/P51

SCL00/P10

SDA00/P11

SCL11/P30 SDA11/P50

ch7

WINDOW

WATCHDOG

TIMER

INTERVAL

TIMER

REAL-TIME

CLOCK

SERIAL ARRAY UNIT0 (4ch)

UART0

UART1

CSI00

CSI11

IIC00

IIC11

DIRECT MEMORY ACCESS

CONTROL

BCD

ADJUSTMENT

RL78

CPU

CORE

RAM

AV

SERIAL INTERFACE IICA0

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

MULTIPLIER&

DIVIDER,

MULITIPLY-

ACCUMULATOR

CODE FLASH MEMORY

DATA FLASH MEMORY

V

SS

DD

TOOLRxD/P11, TOOLTxD/P12

AV

SS

SDAA0/P61 SCLA0/P60

PCLBUZ0/P31

CRC

V

DD

PORT 12

PORT 13

(KEY RETURN)

A/D CONVERTER

POWER ON RESET/

VOLTAGE

DETECTOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

HIGH-SPEED

ON-CHIP

OSCILLATOR

VOLTAGE REGULATOR

INTERRUPT

CONTROL

P121, P122

2

P137

(KR0/P02, KR1/P03,

(4)

KR2/P22, KR3/P23)

ANI0/P20 to

4

ANI3/P23

ANI16/P03, ANI17/P02,

9

ANI18/P10, ANI20/P11, ANI21/P12, ANI25/P51, ANI26/P50, ANI27/P30, ANI29/P31

AV

REFP

/P20

REFM

/P21

AV

POR/LVD

CONTROL

TOOL0/P40

RESET

X1/P121

X2/EXCLK/P122

REGC

INTP0/P137

INTP1/P50

INTP2/P51

INTP3/P30,

2

INTP4/P31

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 13 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.5.2 32-pin products

<R>

TI00/P02

TO00/P03

TI03/TO03/P31

TIMER ARRAY UNIT (8ch)

ch0

ch1

ch2

ch3

ch4

ch5

ch6

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

2

6

5

2

3

P02, P03

P10 to P15

P20 to P24

P30, P31

P40

P50, P51

P60 to P62

RxD2/P14

LOW-SPEED

ON-CHIP

OSCILLATOR

RxD0/P11 TxD0/P12

RxD1/P03 TxD1/P02

SCK00/P10

SI00/P11

SO00/P12

SCK11/P30

SI11/P50

SO11/P51

SCL00/P10 SDA00/P11

SCL11/P30 SDA11/P50

RxD2/P14 TxD2/P13

SCK20/P15

SI20/P14

SO20/P13

SCL20/P15

SDA20/P14

ch7

WINDOW

WATCHDOG

TIMER

INTERVAL

TIMER

REAL-TIME

CLOCK

SERIAL ARRAY UNIT0 (4ch)

UART0

UART1

CSI00

CSI11

IIC00

IIC11

SERIAL ARRAY UNIT1 (2ch)

UART2

LINSEL

CSI20

IIC20

RL78

CPU

CORE

RAM

V

AV

SERIAL INTERFACE IICA0

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

MULTIPLIER&

DIVIDER,

MULITIPLY-

ACCUMULATOR

DIRECT MEMORY ACCESS

CONTROL

BCD

ADJUSTMENT

CODE FLASH MEMORY

DATA FLASH MEMORY

V

SS

,

DD

,

AV

SS

DD

SDAA0/P61

SCLA0/P60

PCLBUZ0/P31,

2

PCLBUZ1/P15

TOOLRxD/P11, TOOLTxD/P12

CRC

PORT 7

PORT 12

PORT 13

KEY RETURN

A/D CONVERTER

POWER ON RESET/

VOLTAGE

DETECTOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

HIGH-SPEED

ON-CHIP

OSCILLATOR

VOLTAGE REGULATOR

INTERRUPT

CONTROL

P70

P120

P121, P122

2

P137

KR0/P70 (KR0/P10 to KR5/P15)

1(6)

(KR0/P120, KR1/P02, KR2/P03, KR3/P22 to KR5/P24)

ANI0/P20 to

5

ANI4/P24 ANI16/P01, ANI17/P00, ANI18/P10,

13

ANI19/P120 to ANI24/P15, ANI26/P50, ANI27/P30, ANI28/P70, ANI29/P31

AV

REFP

/P20

AV

REFM

/P21

POR/LVD

CONTROL

TOOL0/P40

RESET

X1/P121

X2/EXCLK/P122

REGC

RxD2/P14

INTP0/P137

INTP1/P50,

2

INTP2/P51 INTP3/P30,

2

INTP4/P31

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 14 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.5.3 48-pin products

<R>

TI00/P02

TO00/P03

TI01/TO01/P16

TI03/TO03/P31

TI07/TO07/P41

RxD2/P14

LOW-SPEED

ON-CHIP

OSCILLATOR

RTC1HZ/P30

RxD0/P11

TxD0/P12

RxD1/P03

TxD1/P02

SCK00/P10

SI00/P11

SO00/P12

SCK01/P75

SI01/P74

SO01/P73

SCK11/P30

SI11/P50

SO11/P51

SCL00/P10

SDA00/P11

SCL01/P75

SDA01/P74

SCL11/P30

SDA11/P50

RxD2/P14

TxD2/P13

SCK20/P15

SI20/P14

SO20/P13

SCK21/P70

SI21/P71

SO21/P72

SCL20/P15

SDA20/P14

SCL21/P70

SDA21/P71

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

TIMER ARRAY UNIT (8ch)

ch0

ch1

ch2

ch3

ch4

ch5

ch6

ch7

WINDOW

WATCHDOG

TIMER

INTERVAL

TIMER

REAL-TIME

CLOCK

SERIAL ARRAY UNIT0 (4ch)

UART0

UART1

CSI00

CSI01

CSI11

IIC00

IIC01

IIC11

SERIAL ARRAY UNIT1 (2ch)

UART2

LINSEL

CSI20

CSI21

IIC20

IIC21

RL78 CPU

CORE

RAM

AV

SERIAL INTERFACE IICA0

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

MULTIPLIER&

DIVIDER,

MULITIPLY-

ACCUMULATOR

DIRECT MEMORY ACCESS

CONTROL

BCD

ADJUSTMENT

V

SS,

V

DD,

AV

SS

DD

2

CODE FLASH MEMORY

DATA FLASH MEMORY

TOOLRxD/P11, TOOLTxD/P12

SDAA0/P61

SCLA0/P60

PCLBUZ0/P140, PCLBUZ1/P15

CRC

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 12

PORT 13

PORT 14 P140

PORT 15

A/D CONVERTER

KEY RETURN

POWER ON RESET/

VOLTAGE

DETECTOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

HIGH-SPEED

ON-CHIP

OSCILLATOR

VOLTAGE REGULATOR

INTERRUPT

CONTROL

2

P02, P03

7

P10 to P16

8

P20 to P27

2

P30, P31

2

P40, P41

2

P50, P51

4

P60 to P63

6

P70 to P75

P120

4

P121 to P124

P130 P137

P150

9

ANI0/P20 to ANI7/P2, ANI8/P150

ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P11 to ANI24/P15,

15

ANI25, P51, ANI26/P50, P30/ANI27, ANI28/P70, ANI29/P31, ANI30/P41

AV

REFP

/P20

REFM

/P21

AV

KR0/P70 to KR5/P75

6(6)

(KR0/P10 to KR5/P15) (KR0/P02, KR1/P03, KR2/P22 to KR5/P25)

POR/LVD

CONTROL

TOOL0/P40

RESET X1/P121 X2/EXCLK/P122

XT1/P123

XT2/EXCLKS/P124

REGC

RxD2/P14 INTP0/P137

INTP1/P50,

2

INTP2/P51

INTP3/P30,

2

INTP4/P31

INTP5/P16

INTP6/P140

INTP8/P74,

2

INTP9/P75

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00 15 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.5.4 64-pin products

TI00/P00

TO00/P01

TI01/TO01/P16

TI03/TO03/P31

TI04/TO04/P42

TI05/TO05/P05

TI06/TO06/P06

TI07/TO07/P41

RxD2/P14

LOW-SPEED

ON-CHIP

OSCILLATOR

RTC1HZ/P30

RxD0/P11 TxD0/P12

RxD1/P03 TxD1/P02

SCK00/P10

SI00/P11

SO00/P12

SCK01/P75

SI01/P74

SO01/P73

SCK10/P04

SI10/P03

SO10/P02

SCK11/P30

SI11/P50

SO11/P51

SCL00/P10 SDA00/P11

SCL01/P75 SDA01/P74

SCL10/P04 SDA10/P03

SCL11/P30 SDA11/P50

RxD2/P14

TxD2/P13

SCK20/P15

SI20/P14

SO20/P13

SCK21/P70

SI21/P71

SO21/P72

SCL20/P15 SDA20/P14

SCL21/P70 SDA21/P71

TIMER ARRAY UNIT (8ch)

ch0

ch1

ch2

ch3

ch4

ch5

ch6

ch7

WINDOW

WATCHDOG

TIMER

INTERVAL

TIMER

REAL-TIME

CLOCK

SERIAL ARRAY UNIT0 (4ch)

UART0

UART1

CSI00

CSI01

CSI10

CSI11

IIC00

IIC01

IIC10

IIC11

SERIAL ARRAY UNIT1 (2ch)

UART2

LINSEL

CSI20

CSI21

IIC20

IIC21

RL78 CPU

CORE

RAM

EV

AV

SERIAL INTERFACE IICA0

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

MULTIPLIER&

DIVIDER,

MULITIPLY-

ACCUMULATOR

DIRECT MEMORY ACCESS

CONTROL

BCD

ADJUSTMENT

SS,

V

DD,

EV

SS0,

DD0,

AV

SS

DD

2

CODE FLASH MEMORY

DATA FLASH MEMORY

TOOLRxD/P11, TOOLTxD/P12

SDAA0/P61

SCLA0/P60

PCLBUZ0/P140, PCLBUZ1/P141

CRC

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 12

PORT 13

PORT 14

PORT 15

A/D CONVERTER

KEY RETURN

POWER ON RESET/

VOLTAGE

DETECTOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

HIGH-SPEED

ON-CHIP

OSCILLATOR

VOLTAGE REGULATOR

INTERRUPT

CONTROL

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

7

P00 to P06

7

P10 to P16

8

P20 to P27

2

P30, P31

4

P40 to P43

2

P50, P51

4

P60 to P63

8

P70 to P77

P120

4

P121 to P124

P130 P137

2

P140, P141

5

P150 to P154

ANI0/P20 to ANI7/P27,

13

ANI8/P150 to ANI12/P154 ANI16/P03, ANI17/P02, ANI18/P10,

ANI19/P120, ANI20/P11 to ANI24/P15,

15

ANI25//P51, ANI26/P50, ANI27/P30, ANI28/P70ANI29/P31, ANI30/P41

AVREFP/P20 AVREFM/P21

KR0/P70 to KR7/P77, KR8/P05, KR9/P06

10 (10)

(KR0/P00 to KR4/P04, KR5/P22 to KR9/P26) (KR0/P10 to KR5/P15, KR6/P151 to KR9/P154)

POR/LVD

CONTROL

TOOL0/P40

RESET X1/P121 X2/EXCLK/P122

XT1/P123

XT2/EXCLKS/P124

REGC

RxD2/P14 INTP0/P137

INTP1/P50,

2

INTP2/P51 INTP3/P30,

2

INTP4/P31

INTP5/P16

INTP6/P140,

2

INTP7/P141 INTP8/P74,

2

INTP9/P75 INTP10/P76,

2

INTP11/P77

R01UH0305EJ0200 Rev.2.00 16 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

1.6 Outline of Functions

25-pin 32-pin 48-pin 64-pin Item

R5F10E8x R5F10EBx R5F10EGx R5F10ELx

Code flash memory (KB) 16 to 64 16 to 64 16 to 64 32 to 64

Data flash memory (KB) 4 4 4 4

RAM (KB) 2 to 4

Address space 1 MB

Main system clock

High-speed system clock

High-speed on-chip oscillator

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: V

HS (High-speed main) mode : 1 to 32 MHz (V

HS (High-speed main) mode : 1 to 16 MHz (V

LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 3.6 V),

LV (Low-voltage main) mode : 1 to 4 MHz (V

Subsystem clock XT1 (crystal) oscillation, external subsystem

Low-speed on-chip oscillator 15 kHz (TYP.)

(8-bit register × 8) × 4 bank General-purpose register

0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation) Minimum instruction execution time

0.05 μs (High-speed system clock: fMX = 20 MHz operation)

Instruction set

• Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)

• Multiplication (8 bits × 8 bits)

• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.

Total 19 26 42 56 I/O port

<R>

CMOS I/O 14

(N-ch O.D. I/O [V

withstand voltage]: 6)

CMOS input 3 3 5 5

CMOS output 1 1

N-ch open-drain I/O (6 V tolerance)

16-bit timer 8 channels Timer

Watchdog timer 1 channel

Real-time clock (RTC) 1 channel 1 channel

12-bit interval timer (IT) 1 channel

Timer output 2 channels (PWM outputs: 1 ) 4 channels

RTC output 1

Notes 1. In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are

used. (For details, see CHAPTER 3)

<R>

2. Only the constant-period interrupt function when the low-speed on-chip oscillator clock (f

3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters

and slaves). (6.9.3 Operation as multiple PWM output function).

Note1 Note1 Note1 Note1

DD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V

2 to 4 2 to 4 2 to 4

DD = 2.7 to 3.6 V),

DD = 2.4 to 3.6 V),

DD = 1.6 to 3.6 V)

−

clock input (EXCLKS) 32.768 kHz (TYP.)

μ

s (Subsystem clock: fSUB = 32.768 kHz

−

30.5 operation)

(N-ch O.D. I/O [V

DD

withstand voltage]: 9)

20

DD

withstand voltage]: 11)

32

(N-ch O.D. I/O [V

DD

withstand voltage]: 12)

46

− −

2 3 4 4

Note 2

Note 3

(PWM outputs: 3

7 channels

Note 3 Note 3

) )

(PWM outputs: 6

−

• 1 Hz (subsystem clock: f

SUB = 32.768 kHz)

IL) is selected.

(1/2)

DD

R01UH0305EJ0200 Rev.2.00 17 Jul 04, 2013

RL78/G1A CHAPTER 1 OUTLINE

(2/2)

25-pin 32-pin 48-pin 64-pin Item

R5F10E8x R5F10EBx R5F10EGx R5F10ELx

1 2 2 2 Clock output/buzzer output

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,

2.5 MHz, 5 MHz, 10 MHz (Main system clock: f

MAIN = 20 MHz operation)

8/12-bit resolution A/D converter 13 channels 18 channels 24 channels 28 channels

Serial interface [25-pin products]

2

• CSI: 1 channel/simplified I

C: 1 channel/UART: 1 channel

2

C: 1 channel/UART: 1 channel

[32-pin products]

• CSI: 1 channel/simplified I

2

C: 1 channel/UART: 1 channel

2

C: 1 channel/UART: 1 channel

2

C: 1 channel/UART (UART supporting LIN-bus): 1 channel

[48-pin products]

2

• CSI: 2 channels/simplified I

• CSI: 1 channel/simplified I

• CSI: 2 channels/simplified I

C: 2 channels/UART: 1 channel

2

C: 1 channel/UART: 1 channel

2

C: 2 channels/UART (UART supporting LIN-bus): 1 channel

[64-pin products]

2

C: 2 channels/UART: 1 channel

2

C: 2 channels/UART: 1 channel

2

C: 2 channels/UART (UART supporting LIN-bus): 1 channel

I

2

C bus 1 channel 1 channel 1 channel 1 channel

Multiplier and divider/multiplyaccumulator

• CSI: 2 channels/simplified I

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

DMA controller 2 channels

Internal 24 27 27 27 Vectored interrupt

sources

Key interrupt 0 ch (4 ch) 1 ch (6 ch)

Reset

External 6 6 10 13

Note 1

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.)

• Power-down-reset: 1.50 V (TYP.)

Voltage detector

• Rising edge : 1.67 V to 3.14 V (12 stages)

• Falling edge : 1.63 V to 3.06 V (12 stages)

On-chip debug function Provided

Power supply voltage VDD = 1.6 to 3.6 V

TA = −40 to +85°C (A: Consumer application), TA = −40 to +105°C (G: Industrial application) Operating ambient temperature

Notes 1. Can be used by the Peripheral I/O redirection register (PIOR).

2. The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip

debug emulator.

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,

2.5 MHz, 5 MHz, 10 MHz (Main system clock: f

MAIN = 20 MHz operation)

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz,

4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: f

SUB = 32.768 kHz operation)

6 ch 10 ch

Note 2

R01UH0305EJ0200 Rev.2.00 18 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

CHAPTER 2 PIN FUNCTIONS

2.1 Port Function

Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is

shown below.

Table 2-1. Pin I/O Buffer Power Supplies

(1) 25-pin products

Power Supply Corresponding Pins

VDD Port pins other than P20 to P23

• RESET, REGC

AVDD • P20 to P23

(2) 32-pin products

Power Supply Corresponding Pins

VDD Port pins other than P20 to P24

• RESET, REGC

AVDD • P20 to P24

(3) 48-pin products

Power Supply Corresponding Pins

VDD Port pins other than P20 to P27, P150

• RESET, REGC

AVDD • P20 to P27, P150

(4) 64-pin products

Power Supply Corresponding Pins

EVDD0 Port pins other than P20 to P27, P121 to P124, P137, and P150 to P154

VDD • P121 to P124, P137

• RESET, REGC

AVDD • P20 to P27, and P150 to P154

R01UH0305EJ0200 Rev.2.00 19 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.

2.1.1 25-pin products

<R>

Function

Name

P02 7-3-2

P03 8-3-2

P10

P11

P12 7-3-2

P20 ANI0/AVREFP

P21 ANI1/AVREFM

P22 ANI2/(KR2)

P23

P30 ANI27/INTP3/

P31

P40 7-1-1 I/O Input port TOOL0

P50 7-3-2 ANI26/INTP1/SI11/

P51 7-3-1

P60

P61

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

I/O After Reset Alternate Function Function

Type

I/O Analog input port

ANI17/TI00/TxD1/ (KR0)

ANI16/TO00/RxD1/ (KR1)

Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P03 can be set to TTL input buffer. Output of P02 and P03 can be set to N-ch open-drain

DD tolerance).

Note 1

.

8-3-2

I/O Analog input port

ANI18/SCK00/SCL00

ANI20/SI00/RxD0/ TOOLRxD/SDA00

ANI21/SO00/TxD0/ TOOLTxD

output (V Can be set to analog input

Port 1. 3-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10 and P11 can be set to TTL input buffer. Output of P10 to P12 can be set to N-ch open-drain

DD tolerance).

Note 1

.

4-3-1 I/O Analog input port

output (V Can be set to analog input

Port 2. 4-bit I/O port. Input/output can be specified in 1-bit units. Can be set to analog input

Note 2

.

ANI3/(KR3)

7-3-1 I/O Analog input port

SCK11/SCL11

ANI29/TI03/TO03/ INTP4/PCLBUZ0

Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Can be set to analog input

Note 1

.

Port 4. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port.

I/O Analog input port

SDA11

Port 5. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a

ANI25/INTP2/SO11

software setting at input port. Output of P50 can be set to N-ch open-drain output

DD tolerance).

12-1-1 I/O Input port

SCLA0

SDAA0

(V Can be set to analog input

Port 6. 2-bit I/O port. Input/output can be specified in 1-bit units.

Note 1

.

Output of P60 and P61 can be set to N-ch open-drain output (6 V tolerance).

bit units).

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

(1/2)

R01UH0305EJ0200 Rev.2.00 20 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Function

Name

P121 X1

P122

P137 2-1-2 Input Input port INTP0 Port 13.

RESET 2-1-1 Input

Type

2-2-1 Input Input port

I/O After Reset Alternate Function Function

− −

X2/EXCLK

Port 12. 2-bit input only port.

1-bit input only port.

Input only pin for external reset When external reset is not used, connect this pin to V directly or via a resistor.

(2/2)

DD

R01UH0305EJ0200 Rev.2.00 21 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.1.2 32-pin products

<R>

Function

Name

P02 7-3-2

P03 8-3-2

P10

P11

P12

P13

P14

P15

P20 ANI0/AVREFP

P21 ANI1/AVREFM

P22 ANI2/(KR3)

P23 ANI3/(KR4)

P24

P30 ANI27/INTP3/

P31

P40 7-1-1 I/O Input port TOOL0

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

I/O After Reset Alternate Function Function

Type

I/O Analog input

port

ANI17/TI00/TxD1/ (KR1)

ANI16/TO00/RxD1/ (KR2)

Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P03 can be set to TTL input buffer. Output of P02 and P03 can be set to N-ch open-drain

DD tolerance).

Note 1

.

8-3-2

I/O Analog input

port

7-3-2

8-3-2

ANI18/SCK00/ SCL00/(KR0)

ANI20/SI00/RxD0/ TOOLRxD/SDA00/ (KR1)

ANI21/SO00/TxD0/ TOOLTxD/(KR2)

ANI22/TxD2/SO20/ (KR3)

ANI23/RxD2/SI20/

output (V Can be set to analog input

Port 1. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, P14, and P15 can be set to TTL input buffer. Output of P10 to P15 can be set to N-ch open-drain output (V Can be set to analog input.

SDA20/(KR4)

ANI24/PCLBUZ1/ SCK20/SCL20/(KR5)

4-3-1 I/O Analog input

port

Port 2. 5-bit I/O port. Input/output can be specified in 1-bit units. Can be set to analog input

Note 2

.

ANI4/(KR5)

7-3-1 I/O Analog input

port

SCK11/SCL11

ANI29/TI03/TO03/ INTP4/PCLBUZ0

Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Can be set to analog input

Note 1

.

Port 4. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.

bit units.

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

(1/2)

R01UH0305EJ0200 Rev.2.00 22 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Function

Name

P50 7-3-2 Analog input port ANI26/INTP1/SI11/

P51 7-1-1

P60

P61

P62

P70 7-3-1 I/O Analog input port ANI28/KR0 Port 7.

P120 7-3-1 I/O Analog input port ANI19/(KR0)

P121 X1

P122

P137 2-1-2 Input Input port INTP0 Port 13

Pin Type I/O After Reset Alternate Function Function

I/O

SDA11

Input port INTP2/SO11

Port 5. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P50 can be set to N-ch open-drain output

DD tolerance).

12-1-1 I/O Input port

SCLA0

SDAA0

(V P50 can be set to analog input

Port 6. 3-bit I/O port.

−

Input/output can be specified in 1-bit units.

Note

Output of P60 to P62 can be set to N-ch open-drain output (6 V tolerance).

1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Can be set to analog input

Note

.

Port 12.

2-2-1 Input Input port

X2/EXCLK

1-bit I/O port and 2-bit input only port. P120 can be set to analog input For only P120, input/output can be specified. For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port.

1bit input only port.

Note

.

(2/2)

RESET 2-1-1 Input

− −

Input only pin for external reset When external reset is not used, connect this pin to V directly or via a resistor.

Note Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-bit

units).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

DD

R01UH0305EJ0200 Rev.2.00 23 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.1.3 48-pin products

<R>

Function

Name

P02 7-3-2

P03 8-3-2

P10

P11

P12

P13

P14

P15

P16 8-1-1

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

I/O After Reset Alternate Function Function

Type

I/O Analog input port

ANI17/TI00/TxD1/ (KR0)

ANI16TO00/RxD1/ (KR1)

Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P03 can be set to TTL input buffer. Output of P02 and P03 can be set to N-ch open-drain

DD tolerance).

Note 1

.

Note 1

8-3-2

7-3-2

8-3-2

I/O

Analog input port

ANI18/SCK00/ SCL00/(KR0)

ANI20/SI00/RxD0/ TOOLRxD/SDA00/ (KR1)

ANI21/SO00/TxD0/ TOOLTxD/(KR2)

ANI22/TxD2/SO20/ (KR3)

ANI23/RxD2/SI20/

output (V Can be set to analog input

Port 1. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P14 to P16 can be set to TTL input buffer. Output of P10 to P15 can be set to N-ch open-drain output (V P10 to P15 can be set to analog input

SDA20/(KR4)

ANI24/PCLBUZ1/ SCK20/SCL20/(KR5)

Input port

4-3-1 I/O Analog input port

TI01/TO01/INTP5

ANI0/AV

ANI1/AV

REFP

REFM

ANI2/(KR2)

Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. Can be set to analog input

Note 2

.

ANI3/(KR3)

ANI4/(KR4)

ANI5/(KR5)

ANI6

ANI7

7-3-1 I/O Analog input port

ANI27/INTP3/ RTC1HZ/SCK11/ SCL11

ANI29/TI03/TO03/ INTP4

Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Can be set to analog input

Note 1

.

bit units).

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

.

(1/2)

R01UH0305EJ0200 Rev.2.00 24 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Function

Name

P40 7-1-1 Input port

P41 7-3-1

P50 7-3-2 ANI26/INTP1/SI11/

P51 7-3-1

P60

P61

P62

P63

P70 7-3-1 Analog input port

P71 7-1-2

P72

P73

P74 7-1-2

P75 7-1-1

P120 7-3-1 I/O Analog input port

P121

P122

P123

P124

P130 1-1-1 Output Output port

P137 2-1-2 Input Input port INTP0

P140 7-1-1 Input port

P150 4-3-1

RESET 2-1-1 Input

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

I/O After Reset Alternate Function Function

Type

I/O

Analog input port

I/O Analog input port

12-1-1 I/O Input port

I/O

Input port

7-1-1

2-2-1 Input Input port

I/O

Analog input port ANI18

− −

bit units).

TOOL0

ANI30/TI07/TO07

SDA11

ANI25/INTP2/SO11

SCLA0

SDAA0

−

ANI28/KR0/SCK21/ SCL21

KR1/SI21/SDA21

KR2/SO21

KR3/SO01

KR4/INTP8/SI01/ SDA01

KR5/INTP9/SCK01/ SCL01

ANI19

X1

X2/EXCLK

XT1

XT2/EXCLKS

−

PCLBUZ0/INTP6

Port 4. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P41 can be set to analog input

Note 1

.

Port 5. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P50 can be set to N-ch open-drain output

DD tolerance).

(V Can be set to analog input

Note 1

.

Port 6. 4-bit I/O port. Input/output can be specified in 1-bit units. N-ch open-drain output (6 V tolerance).

Port 7. 6-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P71 and P74 can be set to N-ch open-drain output (V P70 can be set to analog input

DD tolerance).

Note 1

.

Port 12. 1-bit I/O port and 4-bit input only port. For only P120, input/output can be specified. For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 can be set to analog input

Note 1

.

Port 13. 1-bit output port and 1-bit input only port.

Port 14. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port.

Port 15 1-bit I/O port. Input/output can be specified. Can be set to analog input

Note 2

.

Input only pin for external reset When external reset is not used, connect this pin to V directly or via a resistor.

(2/2)

DD

R01UH0305EJ0200 Rev.2.00 25 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.1.4 64-pin products

<R>

Function

Name

P00 TI00/(KR0)

P01

P02 7-3-2 ANI17/SO10/TxD1/

P03 8-3-2

P04 8-1-2 SCK10/SCL10/(KR4)

P05 TI05/TO05/KR8

P06

P10

P11

P12 ANI21/SO00/TxD0/

P13

P14 ANI23/RxD2/SI20/

P15

P16 8-1-1

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

I/O After Reset Alternate Function Function

Type

8-1-1 Input port

I/O

TO00/(KR1)

Analog input port

(KR2)

ANI16/SI10/RxD1/ SDA10/(KR3)

Input port

7-1-1

Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P00, P01, P03, and P04 can be set to TTL input buffer. Output of P02 to P04 can be set to N-ch open-drain output (V

DD tolerance).

P02 and P03 can be set to analog input

TI06/TO06/KR9

8-3-2

7-3-2

I/O

Analog input port

ANI18/SCK00/ SCL00/(KR0)

ANI20/SI00/RxD0/ TOOLRxD/SDA00/ (KR1)

TOOLTxD/(KR2)

ANI22/TxD2/SO20/ (KR3)

Port 1. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P10, P11, and P14 to P16 can be set to TTL input buffer. Output of P10 to P15 can be set to N-ch open-drain output (V P10 to P15 can be set to analog input

DD tolerance).

Note 1

8-3-2

SDA20/(KR4)

ANI24/SCK20/ SCL20/(KR5)

Input port TI01/TO01/INTP5

4-3-1 I/O Analog input port

ANI0/AV

ANI1/AV

REFP

REFM

ANI2/(KR5)

Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. Can be set to analog input

Note 2

.

ANI3/(KR6)

ANI4/(KR7)

ANI5/(KR8)

ANI6/(KR9)

ANI7

7-3-2 I/O Analog input port

bit units).

ANI27/INTP3/ RTC1HZ/SCK11/ SCL11

ANI29/TI03/TO03/ INTP4

Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Can be set to analog input

Note 1

.

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

Note 1

.

(1/3)

R01UH0305EJ0200 Rev.2.00 26 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Function

Name

P40 7-1-1 Input port TOOL0

P41 7-3-1 Analog input port ANI30/8TI07/TO07

P42 TI04/TO04

P43

P50 7-3-2 ANI26/INTP1/SI11/

P51 7-3-1

P60

P61

P62

P63

P70 7-3-1 Analog input port

P71 7-1-2

P72

P73

P74 7-1-2

P75

P76

P77

P120 7-3-1 I/O Analog input port

P121

P122

P123

P124

P130 1-1-1 Output Output port

P137 2-1-2 Input Input port INTP0

P140

P141

Note Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-bit

Pin Type I/O After Reset Alternate Function Function

I/O

Port 4. 4-bit I/O port.

7-1-1

Input port

−

Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P41 can be set to analog input

I/O Analog input port

SDA11

ANI25/INTP2/SO11

Port 5. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P50 can be set to N-ch open-drain output (V tolerance). Can be set to analog input

12-1-1 I/O Input port

I/O

Input port

7-1-1

SCLA0

SDAA0

−

ANI28/KR0/SCK21/ SCL21

KR1/SI21/SDA21

KR2/SO21

KR3/SO01

KR4/INTP8/SI01/ SDA01

KR5/INTP9/SCK01/

Port 6. 4-bit I/O port. Input/output can be specified in 1-bit units. N-ch open-drain output (6 V tolerance).

Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P71 and P74 can be set to N-ch open-drain output (V

DD tolerance).

P70 can be set to analog input

SCL01

KR6/INTP10

KR7/INTP11

Port 12. 1-bit I/O port and 4-bit input only port. For only P120, input/output can be specified. For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 can be set to analog input

Port 13.

2-2-1 Input Input port

ANI19

X1

X2/EXCLK

XT1

XT2/EXCLKS

−

1-bit output port and 1-bit input only port.

7-1-1 I/O Input port

PCLBUZ0/INTP6

PCLBUZ1/INTP7

Port 14. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port.

units).

Note

.

Note

.

Note

.

(2/3)

DD

R01UH0305EJ0200 Rev.2.00 27 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Function

Name

P150

P151

P152

P153

P154

RESET 2-1-1 Input

Note Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

Pin Type I/O After Reset Alternate Function Function

4-3-1 I/O Analog input port

− −

ANI8

ANI9/(KR6)

ANI10/(KR7)

ANI11/(KR8)

ANI12/(KR9)

Port 15. 5-bit I/O port. Input/output can be specified in 1-bit units. Can be set to analog input

Input only pin for external reset When external reset is not used, connect this pin to V directly or via a resistor.

Note

.

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

(3/3)

DD

R01UH0305EJ0200 Rev.2.00 28 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.2 Functions Other than Port Pins

2.2.1 With functions for each product

(1/4)

Function

Name

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

ANI8

ANI9

ANI10

ANI11

ANI12

ANI16

ANI17

ANI18

ANI19

ANI20

ANI21

ANI22

ANI23

ANI24

ANI25

ANI26

ANI27

ANI28

ANI29

ANI30

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

INTP7

INTP8

INTP9

INTP10

INTP11

64-pin 48-pin 32-pin 25-pin

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − √ √ − − √ √ − − √ √ − − √ √ − − √ − − − √ − − − √ − − − √ − − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − √ √ √ √ √ √ √ √ √ √ √ − √ √ √ − √ √ √ − √ √ − √ √ √ √ √ √ √ √ √ √ √ √ − √ √ √ √ √ √ − − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ − − √ √ − − √ − − − √ √ − − √ √ − − √ − − − √ − − −

R01UH0305EJ0200 Rev.2.00 29 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

(2/4)

Function

Name

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

KR8

KR9

PCLBUZ0

PCLBUZ1

REGC

RTC1HZ

RESET

RxD0

RxD1

RxD2

SCK00

SCK01

SCK10

SCK11

SCK20

SCK21

SCLA0

SCL00

SCL01

SCL10

SCL11

SCL20

SCL21

SDAA0

SDA00

SDA01

SDA10

SDA11

SDA20

SDA21

64-pin 48-pin 32-pin 25-pin

√ √ √

√ √

√ − − −

√ √ √ √

√ √ √ −

√ √ √ √

√ √ − −

√ √ √ √

√ √ √ −

√ √ √ √

√ √ − −

√ − − −

√ √ √ √

√ √ √ −

√ √ − −

√ √ √ √

√ √ − −

√ − − −

√ √ √ √

√ √ √ −

√ √ − −

√ √ √ √

√ √ − −

√ − − −

√ √ √ √

√ √ √ −

√ √ − −

(√) (√)

(√)

−

Remark The checked function is available only when the bit corresponding to the function in the peripheral I/O

redirection register (PIOR) is set to 1.

R01UH0305EJ0200 Rev.2.00 30 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

(3/4)

Function

Name

SI00

SI01

SI10

SI11

SI20

SI21

SO00

SO01

SO10

SO11

SO20

SO21

TI01

TI03

TI04

TI05

TI06

TI07

TO00

TO01

TO03

TO04

TO05

TO06

TO07

TxD0

TxD1

TxD2

X1

X2

EXCLK

EXCLKS

TI00

XT1

XT2

64-pin 48-pin 32-pin 25-pin

√ √ √ √

√ √ − −

√ − − −

√ √ √ √

√ √ √ −

√ √ − −

√ √ √ √

√ √ − −

√ − − −

√ √ √ √

√ √ √ −

√ √ − −

√ √ √ √

√ − − −

√ √ − −

√ √ √ √

√ √ − −

√ √ √ √

√ − − −

√ √ − −

√ √ √ √

√ √ √ −

√ √ √ √

√ √ − −

√ √ √ √

√ √ − −

R01UH0305EJ0200 Rev.2.00 31 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

(4/4)

Function

Name

VDD

EVDD0

AVDD

AVREFP

AVREFM

VSS

EVSS0

AVSS

TOOLRxD

TOOLTxD

TOOL0

64-pin 48-pin 32-pin 25-pin

√ √ √ √

√ − − −

√ √ √ √

√ − − −

√ √ √ √

R01UH0305EJ0200 Rev.2.00 32 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.2.2 Explanation of function

Function Name I/O Function

ANI0 to ANI12, ANI16 to ANI30 Input A/D converter analog input (see Figure 11-44 Analog Input Pin Connection)

INTP0 to INTP11 Input

KR0 to KR9 Input Key interrupt input

PCLBUZ0, PCLBUZ1 Output Clock output/buzzer output

REGC

RTC1HZ Output Real-time clock correction clock (1 Hz) output

RESET Input

RxD0 to RxD2 Input Serial data input pins of serial interface UART0, UART1, and UART2

TxD0 to TxD2 Output Serial data output pins of serial interface UART0, UART1, and UART2

SCK00, SCK01, SCK10, SCK11,

I/O

SCK20, SCK21

SCL00, SCL01, SCL10, SCL11,

Output

SCL20, SCL21

SDA00, SDA01, SDA10, SDA11,

I/O

SDA20, SDA21

SI00, SI01, SI10, SI11, SI20, SI21 Input

SO00, SO01, SO10, SO11, SO20,

Output

SO21

SCLA0 I/O Serial clock I/O pins of serial interface IICA0

SDAA0 I/O Serial data I/O pins of serial interface IICA0

TI00, TI01, TI03 to TI07 Input

<R>

TO00, TO01, TO03 to TO07 Output Timer output pins of 16-bit timers 00, 01, and 03 to 07

X1, X2

EXCLK Input External clock input for main system clock

XT1, XT2

EXCLKS Input External clock input for subsystem clock

External interrupt request input The valid edge can be specified : Rising edge, falling edge, or both rising and

falling edges)

Pin for connecting regulator output stabilization capacitance for internal operation.

−

Connect this pin to V

SS via a capacitor (0.47 to 1

μ

F). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.

This is the active-low system reset input pin. When the external reset is not used, connect this pin directly or via a resistor to V

Serial clock I/O pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, and CSI21

Serial clock output pins of serial interface IIC00, IIC01, IIC10, IIC11, IIC20, and IIC21

Serial data I/O pins of serial interface IIC00, IIC01, IIC10, IIC11, IIC20, and IIC21

Serial data input pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, and CSI21

Serial data output pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, and CSI21

The pins for inputting an external count clock/capture trigger to 16-bit timers 00, 01, and 03 to 07

Resonator connection for main system clock

−

Resonator connection for subsystem clock

−

(1/2)

DD.

R01UH0305EJ0200 Rev.2.00 33 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

(2/2)

Function Name I/O Function

VDD

EVDD0

AVDD

AVREFP Input A/D converter reference potential (+ side) input

AVREFM Input

VSS

EVSS0

AVSS

TOOLRxD Input

TOOLTxD Output

TOOL0 I/O Data I/O for flash memory programmer/debugger

Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows.

Table 2-2. Relationships Between P40/TOOL0 and Operation Mode After Reset Release

<25-pin, 32-pin 48-pin>

−

Positive power supply for port pin other than P20 to P27, P150 and RESET, REGC pin.

<64-pin >

Positive power supply for P121 to P124, P137 and RESET, REGC pin.

Positive power supply for ports (other than P20 to P27, P121 to P124, P137,

−

P150 to P154)

Positive power supply for P20 to P27, P150 to P154, and A/D converter

−

A/D converter reference potential (− side) input Make AV

<25-pin, 32-pin, 48-pin>

−

<64-pin>

Ground potential for ports (other than P20 to P27, P121 to P124, P137, P150 to

−

P154) Make EV

Ground potential for A/D converter, P20 to P27, and P150 to P154. Use this pin

−

with the same potential as EV

UART reception pin for the external device connection used during flash memory programming

UART transmission pin for the external device connection used during flash memory programming

REFM pin the same potential as AVSS and VSS pin.

Ground potential for port pin other than P20 to P27, P150 and RESET, REGC pin.

Ground potential for P121 to P124, P137 and RESET, REGC pin.

SS0 pin the same potential as VSS pin.

SS0, and VSS.

P40/TOOL0 Operating Mode

EVDD0 Normal operation mode

0 V Flash memory programming mode

For details, see 25.4 Serial Programming Method.

Remark Use bypass capacitors (about 0.1

the shortest distance to V

DD to VSS, EVDD0 to EVSS0 lines.

μ

F) as noise and latch up countermeasures with relatively thick wires at

R01UH0305EJ0200 Rev.2.00 34 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

<R>

Table 2-3 shows the connections of unused pins.

Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function.

<R>

Pin Name I/O Recommended Connection of Unused Pins

P00 to P06

P10 to P16

P20 to P27

P30, P31

P40/TOOL0

P41 to P43

P50, P51

P60 to P63

P70 to P77

P120

P121 to P124 Input Independently connect to VDD or VSS via a resistor.

P130 Output Leave open.

P137 Input Independently connect to VDD or VSS via a resistor.

P140, P141

P150 to P154

RESET Input Connect directly or via a resistor to VDD.

REGC

Remark With products not provided with an EVDD0, or EVSS0 pin, replace EVDD0 with VDD, or replace EVSS0 with VSS.

Table 2-3. Connection of Unused Pins

I/O

−

Input: Independently connect to EV Output: Leave open.

Input: Independently connect to AV Output: Leave open.

Input: Independently connect to EV Output: Leave open.

Input: Independently connect to EV Output: Set the port’s output latch to 0 and leave the pins open, or set the port’s

output latch to 1 and independently connect the pins to EV a resistor.

Input: Independently connect to EV Output: Leave open.

Input: Independently connect to AV Output: Leave open.

Connect to VSS via capacitor (0.47 to 1 μF).

DD0 or EVSS0 via a resistor.

DD or AVSS via a resistor.

DD0 or EVSS0 via a resistor.

DD0 or leave open.

DD0 or EVSS0 via a resistor.

DD0 or EVSS0 via

DD0 or EVSS0 via a resistor.

DD or AVSS via a resistor.

R01UH0305EJ0200 Rev.2.00 35 Jul 04, 2013

(

)

RL78/G1A CHAPTER 2 PIN FUNCTIONS

2.4 Block Diagrams of Pins

<R>

Figures 2-1 to 2-13 show the block diagrams of the pins described in 2.1.1 25-pin products to 2.1.4 64-pin products.

<R>

Internal bus

Figure 2-1. Pin Block Diagram for Pin Type 1-1-1

RD

WR

PORT

Output latch

Pmn

EV

DD

P-ch

Pmn

N-ch

<R>

Figure 2-2. Pin Block Diagram for Pin Type 2-1-1

RESET

Figure 2-3. Pin Block Diagram for Pin Type 2-1-2

<R>

Alternate

function

RD

Internal bus

Remark For alternate functions, see 2.1 Port Function.

EV

SS

RESET

Pmn

R01UH0305EJ0200 Rev.2.00 36 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Internal bus

Clock generator

RD

Figure 2-4. Pin Block Diagram for Pin Type 2-2-1

OSCSEL/

OSCSELS

Alternate function

CMC

EXCLK, OSCSEL/

EXCLKS, OSCSELS

Alternate function

CMC

N-ch

P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function

P-ch

Remark For alternate functions, see 2.1 Port Function.

P121/X1/Alternate function P123/XT1/Alternate function

R01UH0305EJ0200 Rev.2.00 37 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WRADPC

RD

WRPORT

Internal bus

WRPM

Figure 2-5. Pin Block Diagram for Pin Type 4-3-1

ADPC

ADPC3 to ADPC0

0: Analog input 1: Digital I/O

1

0

Output latch

(Pmn)

PM register

(PMmn)

V

VSS

DD

P-ch

Pmn

N-ch

P-ch

A/D converter

N-ch

R01UH0305EJ0200 Rev.2.00 38 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

RD

WR

PORT

Internal bus

WR

PM

Figure 2-6. Pin Block Diagram for Pin Type 7-1-1

PU register

(PUmn)

Alternate

function

1

0

Output latch

(Pmn)

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

(PMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 39 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

RD

WR

PORT

Internal bus

WR

PM

Figure 2-7. Pin Block Diagram for Pin Type 7-1-2

PU register

(PUmn)

Alternate

function

1

0

Output latch

(Pmn)

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

(PMmn)

WR

POM

POM register

(POMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 40 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

WR

PMC

RD

WR

PORT

Internal bus

WR

PM

Figure 2-8. Pin Block Diagram for Pin Type 7-3-1

PU register

(PUmn)

PMC register

(PMCmn)

Alternate

function

1

0

Output latch

(Pmn)

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

(PMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

A/D converter

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

P-ch

N-ch

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 41 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

WR

PMC

RD

WR

PORT

Internal bus

WR

PM

Figure 2-9. Pin Block Diagram for Pin Type 7-3-2

PU register

(PUmn)

PMC register

(PMCmn)

Alternate

function

1

0

Output latch

(Pmn)

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

WR

POM

(PMmn)

POM register

(POMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

A/D converter

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

P-ch

N-ch

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 42 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

WR

PIM

RD

WR

PORT

Internal bus

WR

PM

Figure 2-10. Pin Block Diagram for Pin Type 8-1-1

PU register

(PUmn)

PIM register

(PIMmn)

Alternate

function

1

0

Output latch

(Pmn)

CMOS

TTL

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

(PMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 43 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

WR

PU

WR

PIM

RD

WR

PORT

Internal bus

WR

PM

Figure 2-11. Pin Block Diagram for Pin Type 8-1-2

PU register

(PUmn)

PMC register

(PMCmn)

Alternate

function

1

0

Output latch

(Pmn)

CMOS

TTL

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

(PMmn)

WR

POM

POM register

(POMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 44 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R> <R>

WR

PU

WR

PIM

WR

PMC

RD

Internal bus

WR

PORT

WR

PM

Figure 2-12. Pin Block Diagram for Pin Type 8-3-2

PU register

(PUmn)

PIM register

(PMCmn)

PMC register

(PMCmn)

Alternate

function

1

0

Output latch

(Pmn)

CMOS

TTL

EV

DD

P-ch

EV

DD

P-ch

Pmn

PM register

WR

POM

(PMmn)

POM register

(POMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

A/D converter

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

P-ch

N-ch

EV

N-ch

SS

R01UH0305EJ0200 Rev.2.00 45 Jul 04, 2013

RL78/G1A CHAPTER 2 PIN FUNCTIONS

<R>

Figure 2-13. Pin Block Diagram for Pin Type 12-1-1

Alternate

function

RD

WR

PORT

Output latch

(Pmn)

WR

PM

Internal bus

PM register

(PMmn)

Alternate function

(SAU)

Alternate function

(other than SAU)

Remarks 1. For alternate functions, see 2.1 Port Function.

2. SAU: Serial array unit

1

0

Pmn

N-ch

EV

SS

R01UH0305EJ0200 Rev.2.00 46 Jul 04, 2013

RL78/G1A CHAPTER 3 CPU ARCHITECTURE

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the RL78/G1A can access a 1 MB address space. Figures 3-1 to 3-4 show the memory maps.

R01UH0305EJ0200 Rev.2.00 47 Jul 04, 2013

RL78/G1A CHAPTER 3 CPU ARCHITECTURE

Data memory space

FFFFFH

FFF00H FFEFFH

FFEE0H FFEDFH

FF700H FF6FFH

F4000H F3FFFH

F2000H F1FFFH

F1000H F0FFFH

F0800H F07FFH

F0000H EFFFFH

Figure 3-1. Memory Map (R5F10ExA (x = 8, B, G))

Special function register (SFR)

General-purpose register

Special function register (2nd SFR)

256 bytes

32 bytes

Notes 1, 2

RAM

2 KB

Reserved

Mirror

8 KB

Data flash memory

4 KB

Reserved

2 KB

03FFFH

010CEH 010CDH

010C4H 010C3H

010C0H 010BFH

01080H 0107FH

Program area

On-chip debug security

ID setting area

10 bytes

Option byte area

CALLT table area

64 bytes

Vector table area

128 bytes

Note 3

4 bytes

01FFFH

Boot cluster 1

01000H 00FFFH

Program area

On-chip debug security

ID setting area

10 bytes

Option byte area

CALLT table area

64 bytes

Vector table area

128 bytes

Note 3

4 bytes

Boot cluster 0

Program memory

space

04000H 03FFFH

00000H

Reserved

Code flash memory

16 KB

000CEH 000CDH

000C4H 000C3H

000C0H 000BFH

00080H 0007FH

00000H

Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as

branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be allocated to the area between addresses FFE20H and FFEDFH.

2. Instructions can be executed from the RAM area excluding the general-purpose register area.

3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.

When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the

on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.

4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).

Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data

access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 22.3.3 RAM parity error detection function.

Note 4

R01UH0305EJ0200 Rev.2.00 48 Jul 04, 2013

RL78/G1A CHAPTER 3 CPU ARCHITECTURE

Data memory space

FFFFFH

FFF00H FFEFFH

FFEE0H FFEDFH

FF700H FF6FFH

F8000H F7FFFH

F2000H F1FFFH

F1000H F0FFFH

F0800H F07FFH

F0000H EFFFFH

Figure 3-2. Memory Map (R5F10ExC (x = 8, B, G, L))

07FFFH

Special function register (SFR)

General-purpose register

Special function register (2nd SFR)

256 bytes

32 bytes

Notes 1, 2

RAM

2 KB

Reserved

Mirror 24 KB

Data flash memory

4 KB

Reserved

2 KB

010CEH 010CDH

010C4H 010C3H

010C0H 010BFH

01080H 0107FH

Program area

On-chip debug security

ID setting area

10 bytes

Option byte area

CALLT table area

64 bytes

Vector table area

128 bytes

Note 3

4 bytes

01FFFH

Boot cluster 1

01000H 00FFFH

Reserved

Program area

000CEH

Program memory

space

08000H 07FFFH

00000H

Code flash memory

32KB

000CDH