All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.2.00 Jul 2013
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The
recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas
Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any
application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred
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6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(2012.4)
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
ReadersThis manual is intended for user engineers who wish to understand the functions of the
RL78/G1A and design and develop application systems and programs for these devices.
The target products are as follows.
• 25-pin: R5F10E8x (x = A, C, D, E)
• 32-pin: R5F10EBx (x = A, C, D, E)
• 48-pin: R5F10EGx (x = A, C, D, E)
• 64-pin: R5F10ELx (x = C, D, E)
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The RL78/G1A manual is separated into two parts: this manual and the instructions edition
(common to the RL78 Microcontroller).
RL78/G1A
User’s Manual
(This Manual)
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in the
PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
• To know details of the RL78G1A Microcontroller instructions:
→ Refer to the separate document RL78 Microcontroller Instructions User’s Manual
(R01US0015E).
• CPU functions
• Instruction set
• Explanation of each instruction
RL78 Microcontroller
User’s Manual
Instructions
ConventionsData significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
Decimal
Hexadecimal
...
×××× or ××××B
...
××××
...
××××H
Related DocumentsThe related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name Document No.
Renesas MPUs & MCUs RL78 Family R01CP0003E
Semiconductor Package Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Semiconductor Reliability Handbook R51ZZ0001E
Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
®
Caution: This product uses SuperFlash
technology licensed from Silicon Storage Technology, Inc.
3.1.1 Internal program memory space ................................................................................................... 54
3.1.2 Mirror area .................................................................................................................................... 57
3.1.3 Internal data memory space ......................................................................................................... 59
3.1.4 Special function register (SFR) area............................................................................................. 60
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area..................... 60
3.1.6 Data memory addressing.............................................................................................................. 61
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 96
4.1 Port Functions........................................................................................................................... 96
4.2 Port Configuration..................................................................................................................... 97
4.2.1 Port 0 ............................................................................................................................................ 98
4.2.2 Port 1 ............................................................................................................................................ 98
4.2.3 Port 2 ............................................................................................................................................ 99
4.2.4 Port 3 ............................................................................................................................................ 99
4.2.5 Port 4 .......................................................................................................................................... 100
4.2.6 Port 5 .......................................................................................................................................... 100
4.2.7 Port 6 .......................................................................................................................................... 100
4.2.8 Port 7 .......................................................................................................................................... 101
4.2.9 Port 12 ........................................................................................................................................ 101
4.2.10 Port 13 ........................................................................................................................................ 101
4.2.11 Port 14 ........................................................................................................................................ 102
4.2.12 Port 15 ........................................................................................................................................ 102
4.3 Registers Controlling Port Function ..................................................................................... 103
4.3.1 Port mode registers (PMxx) ........................................................................................................ 105
4.3.2 Port registers (Pxx) ..................................................................................................................... 106
12.7 LIN Communication Operation .............................................................................................. 535
12.7.1 LIN transmission ......................................................................................................................... 535
12.7.2 LIN reception .............................................................................................................................. 538
12.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication .......544
12.8.1 Address field transmission .......................................................................................................... 547
12.8.2 Data transmission ....................................................................................................................... 553
12.8.3 Data reception ............................................................................................................................ 557
25.3.3 Port pins...................................................................................................................................... 808
29.5.1 Serial array unit........................................................................................................................... 870
29.5.2 Serial interface IICA .................................................................................................................... 893
29.6 Analog Characteristics ........................................................................................................... 896
30.5.1 Serial array unit........................................................................................................................... 925
30.5.2 Serial interface IICA .................................................................................................................... 943
30.6 Analog Characteristics ........................................................................................................... 944
Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is
shown below.
Table 2-1. Pin I/O Buffer Power Supplies
(1) 25-pin products
Power Supply Corresponding Pins
VDDPort pins other than P20 to P23
• RESET, REGC
AVDD• P20 to P23
(2) 32-pin products
Power Supply Corresponding Pins
VDDPort pins other than P20 to P24
• RESET, REGC
AVDD• P20 to P24
(3) 48-pin products
Power Supply Corresponding Pins
VDDPort pins other than P20 to P27, P150
• RESET, REGC
AVDD• P20 to P27, P150
(4) 64-pin products
Power Supply Corresponding Pins
EVDD0Port pins other than P20 to P27, P121 to P124, P137, and P150 to P154
VDD• P121 to P124, P137
• RESET, REGC
AVDD• P20 to P27, and P150 to P154
R01UH0305EJ0200 Rev.2.00 19
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.
2.1.1 25-pin products
<R>
Function
Name
P02 7-3-2
P03 8-3-2
P10
P11
P12 7-3-2
P20 ANI0/AVREFP
P21 ANI1/AVREFM
P22 ANI2/(KR2)
P23
P30 ANI27/INTP3/
P31
P40 7-1-1 I/O Input port TOOL0
P50 7-3-2 ANI26/INTP1/SI11/
P51 7-3-1
P60
P61
Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-
2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
Pin
I/O After Reset Alternate Function Function
Type
I/O Analog input port
ANI17/TI00/TxD1/
(KR0)
ANI16/TO00/RxD1/
(KR1)
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P03 can be set to TTL input buffer.
Output of P02 and P03 can be set to N-ch open-drain
DD tolerance).
Note 1
.
8-3-2
I/O Analog input port
ANI18/SCK00/SCL00
ANI20/SI00/RxD0/
TOOLRxD/SDA00
ANI21/SO00/TxD0/
TOOLTxD
output (V
Can be set to analog input
Port 1.
3-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P10 and P11 can be set to TTL input buffer.
Output of P10 to P12 can be set to N-ch open-drain
DD tolerance).
Note 1
.
4-3-1 I/O Analog input port
output (V
Can be set to analog input
Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input
Note 2
.
ANI3/(KR3)
7-3-1 I/O Analog input port
SCK11/SCL11
ANI29/TI03/TO03/
INTP4/PCLBUZ0
Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Can be set to analog input
Note 1
.
Port 4.
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
I/O Analog input port
SDA11
Port 5.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
ANI25/INTP2/SO11
software setting at input port.
Output of P50 can be set to N-ch open-drain output
DD tolerance).
12-1-1 I/O Input port
SCLA0
SDAA0
(V
Can be set to analog input
Port 6.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Note 1
.
Output of P60 and P61 can be set to N-ch open-drain
output (6 V tolerance).
bit units).
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
(1/2)
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Function
Name
P121 X1
P122
P137 2-1-2 Input Input port INTP0 Port 13.
RESET 2-1-1 Input
Pin
Type
2-2-1 Input Input port
I/O After Reset Alternate Function Function
−−
X2/EXCLK
Port 12.
2-bit input only port.
1-bit input only port.
Input only pin for external reset
When external reset is not used, connect this pin to V
directly or via a resistor.
(2/2)
DD
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
2.1.2 32-pin products
<R>
Function
Name
P02 7-3-2
P03 8-3-2
P10
P11
P12
P13
P14
P15
P20 ANI0/AVREFP
P21 ANI1/AVREFM
P22 ANI2/(KR3)
P23 ANI3/(KR4)
P24
P30 ANI27/INTP3/
P31
P40 7-1-1 I/O Input port TOOL0
Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-
2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
Pin
I/O After Reset Alternate Function Function
Type
I/O Analog input
port
ANI17/TI00/TxD1/
(KR1)
ANI16/TO00/RxD1/
(KR2)
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P03 can be set to TTL input buffer.
Output of P02 and P03 can be set to N-ch open-drain
DD tolerance).
DD tolerance).
Note 1
.
8-3-2
I/O Analog input
port
7-3-2
8-3-2
ANI18/SCK00/
SCL00/(KR0)
ANI20/SI00/RxD0/
TOOLRxD/SDA00/
(KR1)
ANI21/SO00/TxD0/
TOOLTxD/(KR2)
ANI22/TxD2/SO20/
(KR3)
ANI23/RxD2/SI20/
output (V
Can be set to analog input
Port 1.
6-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P10, P11, P14, and P15 can be set to TTL input
buffer.
Output of P10 to P15 can be set to N-ch open-drain
output (V
Can be set to analog input.
SDA20/(KR4)
ANI24/PCLBUZ1/
SCK20/SCL20/(KR5)
4-3-1 I/O Analog input
port
Port 2.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input
Note 2
.
ANI4/(KR5)
7-3-1 I/O Analog input
port
SCK11/SCL11
ANI29/TI03/TO03/
INTP4/PCLBUZ0
Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Can be set to analog input
Note 1
.
Port 4.
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
bit units.
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
(1/2)
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Function
Name
P50 7-3-2 Analog input port ANI26/INTP1/SI11/
P51 7-1-1
P60
P61
P62
P70 7-3-1 I/O Analog input port ANI28/KR0 Port 7.
P120 7-3-1 I/O Analog input port ANI19/(KR0)
P121 X1
P122
P137 2-1-2 Input Input port INTP0 Port 13
Pin Type I/O After Reset Alternate Function Function
I/O
SDA11
Input port INTP2/SO11
Port 5.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Output of P50 can be set to N-ch open-drain output
DD tolerance).
12-1-1 I/O Input port
SCLA0
SDAA0
(V
P50 can be set to analog input
Port 6.
3-bit I/O port.
−
Input/output can be specified in 1-bit units.
Note
Output of P60 to P62 can be set to N-ch open-drain
output (6 V tolerance).
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Can be set to analog input
Note
.
Port 12.
2-2-1 Input Input port
X2/EXCLK
1-bit I/O port and 2-bit input only port.
P120 can be set to analog input
For only P120, input/output can be specified.
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting at input port.
1bit input only port.
Note
.
(2/2)
RESET 2-1-1 Input
−−
Input only pin for external reset
When external reset is not used, connect this pin to V
directly or via a resistor.
Note Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-bit
units).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
DD
R01UH0305EJ0200 Rev.2.00 23
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
2.1.3 48-pin products
<R>
Function
Name
P02 7-3-2
P03 8-3-2
P10
P11
P12
P13
P14
P15
P16 8-1-1
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-
2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
Pin
I/O After Reset Alternate Function Function
Type
I/O Analog input port
ANI17/TI00/TxD1/
(KR0)
ANI16TO00/RxD1/
(KR1)
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P03 can be set to TTL input buffer.
Output of P02 and P03 can be set to N-ch open-drain
DD tolerance).
DD tolerance).
Note 1
.
Note 1
8-3-2
7-3-2
8-3-2
I/O
Analog input port
ANI18/SCK00/
SCL00/(KR0)
ANI20/SI00/RxD0/
TOOLRxD/SDA00/
(KR1)
ANI21/SO00/TxD0/
TOOLTxD/(KR2)
ANI22/TxD2/SO20/
(KR3)
ANI23/RxD2/SI20/
output (V
Can be set to analog input
Port 1.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P10, P11, and P14 to P16 can be set to TTL
input buffer.
Output of P10 to P15 can be set to N-ch open-drain
output (V
P10 to P15 can be set to analog input
SDA20/(KR4)
ANI24/PCLBUZ1/
SCK20/SCL20/(KR5)
Input port
4-3-1 I/O Analog input port
TI01/TO01/INTP5
ANI0/AV
ANI1/AV
REFP
REFM
ANI2/(KR2)
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input
Note 2
.
ANI3/(KR3)
ANI4/(KR4)
ANI5/(KR5)
ANI6
ANI7
7-3-1 I/O Analog input port
ANI27/INTP3/
RTC1HZ/SCK11/
SCL11
ANI29/TI03/TO03/
INTP4
Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Can be set to analog input
Note 1
.
bit units).
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
.
(1/2)
R01UH0305EJ0200 Rev.2.00 24
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RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Function
Name
P40 7-1-1 Input port
P41 7-3-1
P50 7-3-2 ANI26/INTP1/SI11/
P51 7-3-1
P60
P61
P62
P63
P70 7-3-1 Analog input port
P71 7-1-2
P72
P73
P74 7-1-2
P75 7-1-1
P120 7-3-1 I/O Analog input port
P121
P122
P123
P124
P130 1-1-1 Output Output port
P137 2-1-2 Input Input port INTP0
P140 7-1-1 Input port
P150 4-3-1
RESET 2-1-1 Input
Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-
2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Pin
I/O After Reset Alternate Function Function
Type
I/O
Analog input port
I/O Analog input port
12-1-1 I/O Input port
I/O
Input port
7-1-1
2-2-1 Input Input port
I/O
Analog input port ANI18
−−
bit units).
TOOL0
ANI30/TI07/TO07
SDA11
ANI25/INTP2/SO11
SCLA0
SDAA0
−
−
ANI28/KR0/SCK21/
SCL21
KR1/SI21/SDA21
KR2/SO21
KR3/SO01
KR4/INTP8/SI01/
SDA01
KR5/INTP9/SCK01/
SCL01
ANI19
X1
X2/EXCLK
XT1
XT2/EXCLKS
−
PCLBUZ0/INTP6
Port 4.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
P41 can be set to analog input
Note 1
.
Port 5.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Output of P50 can be set to N-ch open-drain output
DD tolerance).
(V
Can be set to analog input
Note 1
.
Port 6.
4-bit I/O port.
Input/output can be specified in 1-bit units.
N-ch open-drain output (6 V tolerance).
Port 7.
6-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Output of P71 and P74 can be set to N-ch open-drain
output (V
P70 can be set to analog input
DD tolerance).
Note 1
.
Port 12.
1-bit I/O port and 4-bit input only port.
For only P120, input/output can be specified.
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting at input port.
P120 can be set to analog input
Note 1
.
Port 13.
1-bit output port and 1-bit input only port.
Port 14.
1-bit I/O port.
Input/output can be specified.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Port 15
1-bit I/O port.
Input/output can be specified.
Can be set to analog input
Note 2
.
Input only pin for external reset
When external reset is not used, connect this pin to V
directly or via a resistor.
(2/2)
DD
R01UH0305EJ0200 Rev.2.00 25
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
2.1.4 64-pin products
<R>
Function
Name
P00 TI00/(KR0)
P01
P02 7-3-2 ANI17/SO10/TxD1/
P03 8-3-2
P04 8-1-2 SCK10/SCL10/(KR4)
P05 TI05/TO05/KR8
P06
P10
P11
P12 ANI21/SO00/TxD0/
P13
P14 ANI23/RxD2/SI20/
P15
P16 8-1-1
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-
2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
Pin
I/O After Reset Alternate Function Function
Type
8-1-1 Input port
I/O
TO00/(KR1)
Analog input port
(KR2)
ANI16/SI10/RxD1/
SDA10/(KR3)
Input port
7-1-1
Port 0.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P00, P01, P03, and P04 can be set to TTL input
buffer.
Output of P02 to P04 can be set to N-ch open-drain
output (V
DD tolerance).
P02 and P03 can be set to analog input
TI06/TO06/KR9
8-3-2
7-3-2
I/O
Analog input port
ANI18/SCK00/
SCL00/(KR0)
ANI20/SI00/RxD0/
TOOLRxD/SDA00/
(KR1)
TOOLTxD/(KR2)
ANI22/TxD2/SO20/
(KR3)
Port 1.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Input of P10, P11, and P14 to P16 can be set to TTL
input buffer.
Output of P10 to P15 can be set to N-ch open-drain
output (V
P10 to P15 can be set to analog input
DD tolerance).
Note 1
8-3-2
SDA20/(KR4)
ANI24/SCK20/
SCL20/(KR5)
Input port TI01/TO01/INTP5
4-3-1 I/O Analog input port
ANI0/AV
ANI1/AV
REFP
REFM
ANI2/(KR5)
Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input
Note 2
.
ANI3/(KR6)
ANI4/(KR7)
ANI5/(KR8)
ANI6/(KR9)
ANI7
7-3-2 I/O Analog input port
bit units).
ANI27/INTP3/
RTC1HZ/SCK11/
SCL11
ANI29/TI03/TO03/
INTP4
Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Can be set to analog input
Note 1
.
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
Note 1
.
.
(1/3)
R01UH0305EJ0200 Rev.2.00 26
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Function
Name
P40 7-1-1 Input port TOOL0
P41 7-3-1 Analog input port ANI30/8TI07/TO07
P42 TI04/TO04
P43
P50 7-3-2 ANI26/INTP1/SI11/
P51 7-3-1
P60
P61
P62
P63
P70 7-3-1 Analog input port
P71 7-1-2
P72
P73
P74 7-1-2
P75
P76
P77
P120 7-3-1 I/O Analog input port
P121
P122
P123
P124
P130 1-1-1 Output Output port
P137 2-1-2 Input Input port INTP0
P140
P141
Note Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-bit
Pin Type I/O After Reset Alternate FunctionFunction
I/O
Port 4.
4-bit I/O port.
7-1-1
Input port
−
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
P41 can be set to analog input
I/O Analog input port
SDA11
ANI25/INTP2/SO11
Port 5.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Output of P50 can be set to N-ch open-drain output (V
tolerance).
Can be set to analog input
12-1-1 I/O Input port
I/O
Input port
7-1-1
7-1-1
SCLA0
SDAA0
−
−
ANI28/KR0/SCK21/
SCL21
KR1/SI21/SDA21
KR2/SO21
KR3/SO01
KR4/INTP8/SI01/
SDA01
KR5/INTP9/SCK01/
Port 6.
4-bit I/O port.
Input/output can be specified in 1-bit units.
N-ch open-drain output (6 V tolerance).
Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
Output of P71 and P74 can be set to N-ch open-drain
output (V
DD tolerance).
P70 can be set to analog input
SCL01
KR6/INTP10
KR7/INTP11
Port 12.
1-bit I/O port and 4-bit input only port.
For only P120, input/output can be specified.
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting at input port.
P120 can be set to analog input
Port 13.
2-2-1 Input Input port
ANI19
X1
X2/EXCLK
XT1
XT2/EXCLKS
−
1-bit output port and 1-bit input only port.
7-1-1 I/O Input port
PCLBUZ0/INTP6
PCLBUZ1/INTP7
Port 14.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting at input port.
units).
Note
Note
.
.
Note
.
Note
.
(2/3)
DD
R01UH0305EJ0200 Rev.2.00 27
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Function
Name
P150
P151
P152
P153
P154
RESET 2-1-1 Input
Note Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
Pin Type I/O After Reset Alternate FunctionFunction
4-3-1 I/O Analog input port
−−
ANI8
ANI9/(KR6)
ANI10/(KR7)
ANI11/(KR8)
ANI12/(KR9)
Port 15.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input
Input only pin for external reset
When external reset is not used, connect this pin to V
directly or via a resistor.
Note
.
register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).
TOOL0 I/O Data I/O for flash memory programmer/debugger
Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows.
Table 2-2. Relationships Between P40/TOOL0 and Operation Mode After Reset Release
<25-pin, 32-pin 48-pin>
−
Positive power supply for port pin other than P20 to P27, P150 and RESET,
REGC pin.
<64-pin >
Positive power supply for P121 to P124, P137 and RESET, REGC pin.
Positive power supply for ports (other than P20 to P27, P121 to P124, P137,
−
P150 to P154)
Positive power supply for P20 to P27, P150 to P154, and A/D converter
−
A/D converter reference potential (− side) input
Make AV
<25-pin, 32-pin, 48-pin>
−
<64-pin>
Ground potential for ports (other than P20 to P27, P121 to P124, P137, P150 to
−
P154)
Make EV
Ground potential for A/D converter, P20 to P27, and P150 to P154. Use this pin
−
with the same potential as EV
UART reception pin for the external device connection used during flash memory
programming
UART transmission pin for the external device connection used during flash
memory programming
REFM pin the same potential as AVSS and VSS pin.
Ground potential for port pin other than P20 to P27, P150 and RESET, REGC
pin.
Ground potential for P121 to P124, P137 and RESET, REGC pin.
SS0 pin the same potential as VSS pin.
SS0, and VSS.
P40/TOOL0 Operating Mode
EVDD0Normal operation mode
0 V Flash memory programming mode
For details, see 25.4 Serial Programming Method.
Remark Use bypass capacitors (about 0.1
the shortest distance to V
DD to VSS, EVDD0 to EVSS0 lines.
μ
F) as noise and latch up countermeasures with relatively thick wires at
R01UH0305EJ0200 Rev.2.00 34
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
<R>
Table 2-3 shows the connections of unused pins.
Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function.
<R>
Pin Name I/O Recommended Connection of Unused Pins
P00 to P06
P10 to P16
P20 to P27
P30, P31
P40/TOOL0
P41 to P43
P50, P51
P60 to P63
P70 to P77
P120
P121 to P124 Input Independently connect to VDD or VSS via a resistor.
P130 Output Leave open.
P137 Input Independently connect to VDD or VSS via a resistor.
P140, P141
P150 to P154
RESET Input Connect directly or via a resistor to VDD.
REGC
Remark With products not provided with an EVDD0, or EVSS0pin, replace EVDD0 with VDD, or replace EVSS0 with VSS.
Table 2-3. Connection of Unused Pins
I/O
I/O
−
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to AV
Output: Leave open.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to EV
Output: Set the port’s output latch to 0 and leave the pins open, or set the port’s
output latch to 1 and independently connect the pins to EV
a resistor.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to EV
Output: Leave open.
Input: Independently connect to AV
Output: Leave open.
Connect to VSS via capacitor (0.47 to 1 μF).
DD0 or EVSS0 via a resistor.
DD or AVSS via a resistor.
DD0 or EVSS0 via a resistor.
DD0 or leave open.
DD0 or EVSS0 via a resistor.
DD0 or EVSS0 via a resistor.
DD0 or EVSS0 via
DD0 or EVSS0 via a resistor.
DD0 or EVSS0 via a resistor.
DD0 or EVSS0 via a resistor.
DD or AVSS via a resistor.
R01UH0305EJ0200 Rev.2.00 35
Jul 04, 2013
(
)
RL78/G1A CHAPTER 2 PIN FUNCTIONS
2.4 Block Diagrams of Pins
<R>
Figures 2-1 to 2-13 show the block diagrams of the pins described in 2.1.1 25-pin products to 2.1.4 64-pin products.
<R>
Internal bus
Figure 2-1. Pin Block Diagram for Pin Type 1-1-1
RD
WR
PORT
Output latch
Pmn
EV
DD
P-ch
Pmn
N-ch
<R>
Figure 2-2. Pin Block Diagram for Pin Type 2-1-1
RESET
Figure 2-3. Pin Block Diagram for Pin Type 2-1-2
<R>
Alternate
function
RD
Internal bus
Remark For alternate functions, see 2.1 Port Function.
EV
SS
RESET
Pmn
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Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Internal bus
Clock generator
RD
RD
Figure 2-4. Pin Block Diagram for Pin Type 2-2-1
OSCSEL/
OSCSELS
Alternate
function
CMC
EXCLK, OSCSEL/
EXCLKS, OSCSELS
Alternate
function
CMC
N-ch
P122/X2/EXCLK/Alternate function
P124/XT2/EXCLKS/Alternate function
P-ch
Remark For alternate functions, see 2.1 Port Function.
P121/X1/Alternate function
P123/XT1/Alternate function
R01UH0305EJ0200 Rev.2.00 37
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WRADPC
RD
WRPORT
Internal bus
WRPM
Figure 2-5. Pin Block Diagram for Pin Type 4-3-1
ADPC
ADPC3 to ADPC0
0: Analog input
1: Digital I/O
1
0
Output latch
(Pmn)
PM register
(PMmn)
V
VSS
DD
P-ch
Pmn
N-ch
P-ch
A/D converter
N-ch
R01UH0305EJ0200 Rev.2.00 38
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
RD
WR
PORT
Internal bus
WR
PM
Figure 2-6. Pin Block Diagram for Pin Type 7-1-1
PU register
(PUmn)
Alternate
function
1
0
Output latch
(Pmn)
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
(PMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 39
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
RD
WR
PORT
Internal bus
WR
PM
Figure 2-7. Pin Block Diagram for Pin Type 7-1-2
PU register
(PUmn)
Alternate
function
1
0
Output latch
(Pmn)
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
(PMmn)
WR
POM
POM register
(POMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 40
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
WR
PMC
RD
WR
PORT
Internal bus
WR
PM
Figure 2-8. Pin Block Diagram for Pin Type 7-3-1
PU register
(PUmn)
PMC register
(PMCmn)
Alternate
function
1
0
Output latch
(Pmn)
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
(PMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
A/D converter
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
P-ch
N-ch
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 41
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
WR
PMC
RD
WR
PORT
Internal bus
WR
PM
Figure 2-9. Pin Block Diagram for Pin Type 7-3-2
PU register
(PUmn)
PMC register
(PMCmn)
Alternate
function
1
0
Output latch
(Pmn)
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
WR
POM
(PMmn)
POM register
(POMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
A/D converter
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
P-ch
N-ch
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 42
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
WR
PIM
RD
WR
PORT
Internal bus
WR
PM
Figure 2-10. Pin Block Diagram for Pin Type 8-1-1
PU register
(PUmn)
PIM register
(PIMmn)
Alternate
function
1
0
Output latch
(Pmn)
CMOS
TTL
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
(PMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 43
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
WR
PU
WR
PIM
RD
WR
PORT
Internal bus
WR
PM
Figure 2-11. Pin Block Diagram for Pin Type 8-1-2
PU register
(PUmn)
PMC register
(PMCmn)
Alternate
function
1
0
Output latch
(Pmn)
CMOS
TTL
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
(PMmn)
WR
POM
POM register
(POMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 44
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R> <R>
WR
PU
WR
PIM
WR
PMC
RD
Internal bus
WR
PORT
WR
PM
Figure 2-12. Pin Block Diagram for Pin Type 8-3-2
PU register
(PUmn)
PIM register
(PMCmn)
PMC register
(PMCmn)
Alternate
function
1
0
Output latch
(Pmn)
CMOS
TTL
EV
DD
P-ch
EV
DD
P-ch
Pmn
PM register
WR
POM
(PMmn)
POM register
(POMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
A/D converter
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
P-ch
N-ch
EV
N-ch
SS
R01UH0305EJ0200 Rev.2.00 45
Jul 04, 2013
RL78/G1A CHAPTER 2 PIN FUNCTIONS
<R>
Figure 2-13. Pin Block Diagram for Pin Type 12-1-1
Alternate
function
RD
WR
PORT
Output latch
(Pmn)
WR
PM
Internal bus
PM register
(PMmn)
Alternate function
(SAU)
Alternate function
(other than SAU)
Remarks 1. For alternate functions, see 2.1 Port Function.
2. SAU: Serial array unit
1
0
Pmn
N-ch
EV
SS
R01UH0305EJ0200 Rev.2.00 46
Jul 04, 2013
RL78/G1A CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the RL78/G1A can access a 1 MB address space. Figures 3-1 to 3-4 show the memory maps.
R01UH0305EJ0200 Rev.2.00 47
Jul 04, 2013
RL78/G1A CHAPTER 3 CPU ARCHITECTURE
Data memory
space
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FF700H
FF6FFH
F4000H
F3FFFH
F2000H
F1FFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
Figure 3-1. Memory Map (R5F10ExA (x = 8, B, G))
Special function register (SFR)
General-purpose register
Special function register (2nd SFR)
256 bytes
32 bytes
Notes 1, 2
RAM
2 KB
Reserved
Mirror
8 KB
Data flash memory
4 KB
Reserved
2 KB
03FFFH
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
01080H
0107FH
Program area
On-chip debug security
ID setting area
10 bytes
Option byte area
CALLT table area
64 bytes
Vector table area
128 bytes
Note 3
Note 3
4 bytes
01FFFH
Boot cluster 1
01000H
00FFFH
Program area
On-chip debug security
ID setting area
10 bytes
Option byte area
CALLT table area
64 bytes
Vector table area
128 bytes
Note 3
Note 3
4 bytes
Boot cluster 0
Program
memory
space
04000H
03FFFH
00000H
Reserved
Code flash memory
16 KB
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as
branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be
allocated to the area between addresses FFE20H and FFEDFH.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details,
see 22.3.3 RAM parity error detection function.
Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as
branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be
allocated to the area between addresses FFE20H and FFEDFH.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details,
see 22.3.3 RAM parity error detection function.
Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as
branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be
allocated to the area between addresses FFE20H and FFEDFH. Also, use of the area FF300H to FF309H
is prohibited, because this area is used for each library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details,
see 22.3.3 RAM parity error detection function.
Notes 1. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses used as
branch destinations for vectored interrupts or as sources or destinations of DMA transfers must not be
allocated to the area between addresses FFE20H and FFEDFH. Also, use of the area FEF00H to FF309H
is prohibited, because this area is used for each library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details,
see 22.3.3 RAM parity error detection function.
Note 4
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Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block
numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash
Memory.
0FFFFH
0FC00H
0FBFFH
Block 3FH
007FFH
00400H
003FFH
00000H
(R5F10ExE (x = 8, B, G, L))
Block 01H
Block 00H
1 KB
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory
Address Value Block NumberAddress Value Block Number
This register sets the flash memory space for mirroring to area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-5. Format of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PMC 0 0 0 0 0 0 0 MAA
MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1 Setting is prohibited
Cautions 1. Be sure to clear bit 0 (MAA) of this register to 0 (default value).
2. After setting the PMC register, wait for at least one instruction and access the mirror area.
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3.1.3 Internal data memory space
The RL78/G1A products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number Internal RAM
R5F10ExA (x = 8, B, G)
R5F10ExC (x = 8, B, G, L)
R5F10ExD (x = 8, B, G, L)
R5F10ExE (x = 8, B, G, L)
The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited to use
the general-purpose register area for fetching instructions). Four general-purpose register banks consisting of eight 8-bit
registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area.
The internal RAM is used as stack memory.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
2. During self programming and data flash rewriting, the stack, data buffer, and RAM addresses
used as branch destinations for vectored interrupts or as sources or destinations of DMA
transfers must not be allocated to the area between addresses FFE20H and FFEDFH.
3. During self programming and data flash rewriting, the RAM area in the products below is
prohibited. Because this area is used for each library.
R5F10ExD (x = 8, B, G, L): FF300H to FF309H
R5F10ExE (x = 8, B, G, L): FEF00H to FF309H
2048 × 8 bits (FF700H to FFEFFH)
3072 × 8 bits (FF300H to FFEFFH)
4096 × 8 bits (FEF00H to FFEFFH)
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table
3-5 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see
Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assigned.
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3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
RL78/G1A, based on operability and other considerations. In particular, special addressing methods designed for the
functions of the special function registers (SFR) and general-purpose registers are available for use. Figure 3-6 shows
correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for
Processing Data Addresses.
<R>
FFFFFH
FFF20H
FFF1FH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFE20H
FFE1FH
Figure 3-6. Correspondence Between Data Memory and Addressing
Special function register (SFR)
General-purpose register
256 bytes
32 bytes
RAM
2 to 4 KB
SFR addressing
Register addressing
Short direct
addressing
F2000H
F1FFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
Mirror area
Data flash memory
4 KB
Reserved
Special function register (2nd SFR)
2 KB
Reserved
Code flash memory
16 to 64 KB
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
00000H
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3.2 Processor Registers
The RL78/G1A products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched.
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the 16 lower-order bits
of the program counter. The four higher-order bits of the program counter are cleared to 0000.
Figure 3-7. Format of Program Counter
19
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH
PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset
signal generation sets the PSW register to 06H.
Figure 3-8. Format of Program Status Word
70
IEZRBS1ACRBS0ISP0CY
ISP1PSW
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and maskable interrupt request acknowledgment is
controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation or comparison result is zero or equal, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is
stored.
0
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(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 16.3.3) can not be acknowledged. Actual vectored interrupt request
acknowledgment is controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon
rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as
the stack area.
Figure 3-9. Format of Stack Pointer
0
<R>
<R>
<R>
15
SP15 SP14 SP13 SP12 SP11 SP10
SP
SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP10
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is
incremented after read (restore) from the stack memory.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instruction or a stack area.
3. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch
destination of vector interrupt processing, and a DMA transfer destination/transfer source to the
area FFE20H to FFEDFH when performing self-programming and rewriting the data flash memory.
4. Use of the RAM areas of the following products is prohibited when performing self-programming
and rewriting the data flash memory, because these areas are used for each library.
R5F10ExA (x = 8, B, G): FFE20H to FFEDFH
R5F10ExC (x = 8, B, G, L): FFE20H to FFEDFH
R5F10ExD (x = 8, B, G, L): FFE20H to FFEDFH, FF300H to FF309H
R5F10ExE (x = 8, B, G, L): FFE20H to FFEDFH, FEF00H to FF309H
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-
register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupt processing for each bank.
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
Figure 3-10. Configuration of General-Purpose Registers
(a) Function name
16-bit processing8-bit processing
FFEFFH
FFEF8H
FFEF0H
FFEE8H
FFEE0H
Register bank 0
Register bank 1
Register bank 2
Register bank 3
HL
DE
BC
AX
15070
H
L
D
E
B
C
A
X
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3.2.3 ES and CS registers
The ES register and CS register are used to specify the higher address for data access and when a branch instruction
is executed (register direct addressing), respectively.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-11. Configuration of ES and CS Registers
ES
4
6
70
0000ES3ES2ES1ES0
5
3
21
5
6
<R>
CS
70
0000CS3CS2CS1CS0
Though the data area which can be accessed with 16-bit addresses is the 64 KB from F0000H to FFFFFH, using the
ES register as well extends this to the 1 MB from 00000H to FFFFFH.
Figure 3-12. Extension of Data Area Which Can Be Accessed
!addr16 F 0000H - FFFFH
<R>
ES:!addr16
ES:!addr16
0H - FH 0000H - FFFFH
FFFFFH
!addr16
F0000H
EFFFFH
Special function register
(SFR) 256 bytes
Special function register
(2nd SFR) 2 Kbytes
4
3
21
Data memory space
Code flash memory
00000H
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3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (sfr.bit).
When the bit name is defined: <Bit name> When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>
• 8-bit manipulation
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation
can also be specified with an address.
• 16-bit manipulation
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When
specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
FFF36H Key return mode control register 1 KRM1 R/W
FFF37H Key return mode control register 0 KRM0 R/W
FFF38H External interrupt rising edge
enable register 0
FFF39H External interrupt falling edge
enable register 0
FFF3AH External interrupt rising edge
enable register 1
FFF3BH External interrupt falling edge
enable register 1
FFF44H TXD1/
FFF45H
FFF46H RXD1/
FFF47H
FFF48H TXD2/
FFF49H
FFF4AH RXD2/
FFF4BH
FFF50H IICA shift register 0 IICA0 R/W
FFF51H IICA status register 0 IICS0 R
FFF52H IICA flag register 0 IICF0 R/W
FFF64H
FFF65H
FFF66H
FFF67H
FFF68H
FFF69H
FFF6AH
FFF6BH
FFF6CH
FFF6DH
FFF6EH
FFF6FH
Serial data register 02
Serial data register 03
Serial data register 10
Serial data register 11
Timer data register 02 TDR02 R/W
Timer data register 03
Timer data register 04 TDR04 R/W
Timer data register 05 TDR05 R/W
Timer data register 06 TDR06 R/W
Timer data register 07 TDR07 R/W
Symbol R/W
EGP0 R/W
EGN0 R/W
EGP1 R/W
EGN1 R/W
SDR02 R/W
SIO10
−
SDR03 R/W
SIO11
−
SDR10 R/W
SIO20
−
SDR11 R/W
SIO21
−
TDR03L
TDR03H
TDR03 R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √
− −
− √
− −
− √
− −
− √
− −
− √ −
√ √ −
√ √ −
− − √
− √
− √
− − √
− − √
− − √
− − √
√
√
√
√
√
After Reset
00H
00H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
0000H
00H
00H
00H
0000H
00H
00H
0000H
0000H
0000H
0000H
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Table 3-5. SFR List (3/5)
Special Function Register (SFR) Name
FFF90H
FFF91H
FFF92H Second count register SEC R/W
FFF93H Minute count register MIN R/W
FFF94H Hour count register HOUR R/W
FFF95H Week count register WEEK R/W
FFF96H Day count register DAY R/W
FFF97H Month count register MONTH R/W
FFF98H Year count register YEAR R/W
FFF99H Watch error correction register SUBCUD R/W
FFF9AH Alarm minute register ALARMWM R/W
FFF9BH Alarm hour register ALARMWH R/W
FFF9CH Alarm week register ALARMWW R/W
FFF9DH Real-time clock control register 0 RTCC0 R/W
FFF9EH Real-time clock control register 1 RTCC1 R/W
FFFA0H Clock operation mode control
FFFA1H Clock operation status control
FFFA2H Oscillation stabilization time
FFFA3H Oscillation stabilization time
FFFA4H System clock control register CKC R/W
FFFA5H Clock output select register 0 CKS0 R/W
FFFA6H Clock output select register 1 CKS1 R/W
Interval timer control register ITMC R/W
register
register
counter status register
select register
Symbol R/W
CMC R/W
CSC R/W
OSTC R
OSTS R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
− − √
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
After Reset
0FFFH
00H
00H
Note
12H
00H
01H
01H
00H
00H
00H
12H
00H
00H
00H
00H
C0H
00H
07H
00H
00H
00H
Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1
after reset.
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Table 3-5. SFR List (4/5)
Special Function Register (SFR) Name
Symbol R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
FFFA8H Reset control flag register RESF R
FFFA9H Voltage detection register LVIM R/W
FFFAAH Voltage detection level registerLVIS R/W
FFFABH Watchdog timer enable registerWDTE R/W
FFFACH CRC input register CRCIN R/W
FFFB0H DMA SFR address register 0 DSA0 R/W
FFFB1H DMA SFR address register 1 DSA1 R/W
FFFB2H DRA0LR/W
FFFB3H
FFFB4H DRA1LR/W
FFFB5H
FFFB6H DBC0LR/W
FFFB7H
FFFB8H DBC1LR/W
FFFB9H
DMA RAM address register 0
DMA RAM address register 1
DMA byte count register 0
DMA byte count register 1
DRA0H
DRA1H
DBC0H
DBC1H
DRA0
R/W
DRA1
R/W
DBC0
R/W
DBC1
R/W
FFFBAH DMA mode control register 0 DMC0 R/W
FFFBBH DMA mode control register 1 DMC1 R/W
FFFBCH DMA operation control register 0 DRC0 R/W
FFFBDH DMA operation control register 1 DRC1 R/W
− √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
− √
− √
− √
− √
− √
− √
− √
− √
√ √ −
√ √ −
√ √ −
√ √ −
Notes 1. The reset values of the registers vary depending on the reset source as shown below.
<R>
<R>
Reset Source
RESET Input
Reset by
POR
Register
RESF
TRAP Set (1) Held
Cleared (0)
WDTRF Held Set (1) Held
RPERF Held Set (1) Held
IAWRF Held Set (1)
LVIRF
LVIM
LVISEN Cleared (0)
LVIOMSK
Held
LVIF
LVIS Cleared (00H/01H/81H)
Reset by
Execution of
Illegal
Reset by
WDT
Reset by
RAM parity
error
Instruction
Held Set (1)
2. The reset value of the WDTE register is determined by the setting of the option byte.
√
√
√
√
After Reset
Undefined
Note 1
00H
00H/01H/81H
1AH/9AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Reset by
illegal-
memory
access
Note 1
Note 1
Note 2
Held
Held
Reset by
LVD
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Table 3-5. SFR List (5/5)
Special Function Register (SFR) Name
FFFD0H IF2L R/W
FFFD1H
FFFD4H MK2LR/W
FFFD5H
FFFD8H PR02LR/W
FFFD9H
FFFDCH PR12LR/W
FFFDDH
FFFE0H IF0L R/W
FFFE1H
FFFE2H IF1L R/W
FFFE3H
FFFE4H MK0LR/W
FFFE5H
FFFE6H MK1LR/W
FFFE7H
FFFE8H PR00LR/W
FFFE9H
FFFEAH PR01LR/W
FFFEBH
FFFECH PR10LR/W
FFFEDH
FFFEEH PR11LR/W
FFFEFH
FFFF0H
FFFF1H
FFFF2H
FFFF3H
FFFF4H
FFFF5H
FFFF6H
FFFF7H
FFFFEH Processor mode control
Interrupt request flag register 2
Interrupt mask flag register 2
Priority specification flag
register 02
Priority specification flag
register 12
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt mask flag register 0
Interrupt mask flag register 1
Priority specification flag
register 00
Priority specification flag
register 01
Priority specification flag
register 10
Priority specification flag
register 11
Multiplication/division data
register A (L)
Multiplication/division data
register A (H)
Multiplication/division data
register B (H)
Multiplication/division data
register B (L)
register
Symbol R/W
IF2
IF2H
MK2
MK2H
PR02
PR02H
PR12
PR12H
IF0
IF0H
IF1
IF1H
MK0
MK0H
MK1
MK1H
PR00
PR00H
PR01
PR01H
PR10
PR10H
PR11
PR11H
MDAL R/W
MDAH R/W
MDBH R/W
MDBL R/W
PMC R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
√√
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
− − √
− − √
− − √
− − √
√ √ −
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
√
√
√
√
√
√
√
√
√
√
√
√
After Reset
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
0000H
0000H
0000H
0000H
00H
R01UH0305EJ0200 Rev.2.00 71
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
3.2.5 Extended special function registers (2nd SFRs)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe as follows for the 1-bit manipulation instruction operand (!addr16.bit)
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>
• 8-bit manipulation
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs (2
Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
F00F5H RAM parity error control register RPECTL R/W
F00FEH BCD adjust result register BCDADJ R
F0100H
F0101H
F0102H SSR01L
F0103H
F0104H SSR02L
F0105H
F0106H SSR03L
F0107H
F0108H SIR00L
F0109H
F010AH SIR01L
F010BH
F010CH SIR02L
F010DH
F010EH SIR03L
F010FH
Serial status register 00
Serial status register 01
Serial status register 02
Serial status register 03
Serial flag clear trigger register
00
Serial flag clear trigger register
01
Serial flag clear trigger register
02
Serial flag clear trigger register
03
Symbol R/W
GAIDIS R/W
GDIDIS R/W
HIOTRM R/W
HOCODIV R/W
MDCL R/W
MDCH R/W
MDUC R/W
OSMC R/W
SSR00L
SSR00 R
−
SSR01 R
−
SSR02 R
−
SSR03 R
−
SIR00 R/W
−
SIR01 R/W
−
SIR02 R/W
−
SIR03 R/W
−
Manipulable Bit Range Address
1-bit8-bit16-bit
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− − √
− − √
√ √ −
√ √ −
− √ −
√ √ −
− √ −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
√
√
√
√
√
√
√
√
After Reset
00H
00H
00H
Undefined
Undefined
0000H
0000H
00H
00H
00H
00H
Undefined
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Note 1
Note 2
Notes 1. The value after a reset is adjusted at the time of shipment.
2. The value after a reset is a value set in FRQSEL2 to FRQSEL0 of the option byte (000C2H).
R01UH0305EJ0200 Rev.2.00 74
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (3/6)
Special Function Register (SFR) Name
F0110H
F0111H
F0112H
F0113H
F0114H
F0115H
F0116H
F0117H
F0118H
F0119H
F011AH
F011BH
F011CH
F011DH
F011EH
F011FH
F0120H SE0L
F0121H
F0122H SS0L
F0123H
F0124H ST0L
F0125H
F0126H SPS0L
F0127H
F0128H
F0129H
F012AH SOE0L
F012BH
F0134H SOL0L
F0135H
F0138H Serial standby control register 0
F0140H SSR10L
F0141H
F0142H SSR11L
F0143H
F0148H SIR10L
F0149H
F014AH SIR11L
F014BH
Serial mode register 00 SMR00 R/W
Serial mode register 01 SMR01 R/W
Serial mode register 02 SMR02 R/W
Serial mode register 03 SMR03 R/W
Serial communication operation
setting register 00
Serial communication operation
setting register 01
Serial communication operation
setting register 02
Serial communication operation
setting register 03
Serial channel enable status
register 0
Serial channel start register 0
Serial channel stop register 0
Serial clock select register 0
Serial output register 0 SO0 R/W
Serial output enable register 0
Serial output level register 0
Serial status register 10
Serial status register 11
Serial flag clear trigger register
10
Serial flag clear trigger register
11
Symbol R/W
SCR00 R/W
SCR01 R/W
SCR02 R/W
SCR03 R/W
−
−
−
−
−
−
SSC0L
−
−
−
−
−
SE0 R
SS0 R/W
ST0 R/W
SPS0 R/W
SOE0 R/W
SOL0 R/W
SSC0 R/W
SSR10R
SSR11R
SIR10 R/W
SIR11 R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
− − √
− − √
− − √
− − √
− − √
− − √
− − √
− − √
√ √
− −
√ √
− −
√ √
− −
− √
− −
− − √
√ √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
√
√
√
√
√
√
√
√
√
√
√
After Reset
0020H
0020H
0020H
0020H
0087H
0087H
0087H
0087H
0000H
0000H
0000H
0000H
0F0FH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
R01UH0305EJ0200 Rev.2.00 75
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (4/6)
<R>
Special Function Register (SFR) Name
F0150H
F0151H
F0152H
F0153H
F0158H
F0159H
F015AH
F015BH
F0160H SE1L
F0161H
F0162H SS1L
F0163H
F0164H ST1L
F0165H
F0166H SPS1L
F0167H
F0168H
F0169H
F016AH SOE1L
F016BH
F0174H SOL1L
F0175H
F0180H
F0181H
F0182H
F0183H
F0184H
F0185H
F0186H
F0187H
F0188H
F0189H
F018AH
F018BH
F018CH
F018DH
F018EH
F018FH
Serial mode register 10 SMR10 R/W
Serial mode register 11 SMR11 R/W
Serial communication operation
setting register 10
Serial communication operation
setting register 11
Serial channel enable status
register 1
Serial channel start register 1
Serial channel stop register 1
Serial clock select register 1
Serial output register 1 SO1 R/W
Serial output enable register 1
Serial output level register 1
Timer counter register 00 TCR00 R
Timer counter register 01 TCR01 R
Timer counter register 02 TCR02 R
Timer counter register 03 TCR03 R
Timer counter register 04 TCR04 R
Timer counter register 05 TCR05 R
Timer counter register 06 TCR06 R
Timer counter register 07 TCR07 R
Symbol R/W
SCR10 R/W
SCR11 R/W
−
−
−
−
−
−
SE1 R
SS1 R/W
ST1 R/W
SPS1 R/W
SOE1 R/W
SOL1 R/W
Manipulable Bit Range Address
1-bit8-bit16-bit
− − √
− − √
− − √
− − √
√ √
− −
√ √
− −
√ √
− −
− √
− −
− − √
√ √
− −
− √
− −
− − √
− − √
− − √
− − √
− − √
− − √
− − √
− − √
√
√
√
√
√
√
After Reset
0020H
0020H
0087H
0087H
0000H
0000H
0000H
0000H
0303H
0000H
0000H
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
R01UH0305EJ0200 Rev.2.00 76
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (5/6)
Special Function Register (SFR) Name
F0190H
F0191H
F0192H
F0193H
F0194H
F0195H
F0196H
F0197H
F0198H
F0199H
F019AH
F019BH
F019CH
F019DH
F019EH
F019FH
F01A0H TSR00L
F01A1H
F01A2H TSR01L
F01A3H
F01A4H TSR02L
F01A5H
F01A6H TSR03L
F01A7H
F01A8H TSR04L
F01A9H
F01AAH TSR05L
F01ABH
F01ACH TSR06L
F01ADH
F01AEH TSR07L
F01AFH
Timer mode register 00 TMR00 R/W
Timer mode register 01 TMR01 R/W
Timer mode register 02 TMR02 R/W
Timer mode register 03 TMR03 R/W
Timer mode register 04 TMR04 R/W
Timer mode register 05 TMR05 R/W
Timer mode register 06 TMR06 R/W
Timer mode register 07 TMR07 R/W
Timer status register 00
Timer status register 01
Timer status register 02
Timer status register 03
Timer status register 04
Timer status register 05
Timer status register 06
Timer status register 07
Symbol R/W
−
−
−
−
−
−
−
−
TSR00R
TSR01R
TSR02R
TSR03R
TSR04R
TSR05R
TSR06R
TSR07R
Manipulable Bit Range Address
1-bit8-bit16-bit
− − √
− − √
− − √
− − √
− − √
− − √
− − √
− − √
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
− √
− −
√
√
√
√
√
√
√
√
After Reset
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
R01UH0305EJ0200 Rev.2.00 77
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Extended SFR (2nd SFR) List (6/6)
Special Function Register (SFR) Name
F01B0H TE0L
F01B1H
F01B2H TS0L
F01B3H
F01B4H TT0L
F01B5H
F01B6H
F01B7H
F01B8H TO0L
F01B9H
F01BAH TOE0L
F01BBH
F01BCH TOL0L
F01BDH
F01BEH TOM0L
F01BFH
F0230H IICA control register 00
F0231H IICA control register 01
F0232H IICA low-level width setting
F0233H IICA high-level width setting
F0234H Slave address register 0 SVA0R/W
F02F0H Flash memory CRC control
F02F2H Flash memory CRC operation
F02FAH CRC data register CRCDR/W
Timer channel enable status
register 0
Timer channel start register 0
Timer channel stop register 0
Timer clock select register 0 TPS0 R/W
Timer output register 0
Timer output enable register 0
Timer output level register 0
Timer output mode register 0
register 0
register 0
register
result register
Symbol R/W
TE0 R
−
TS0 R/W
−
TT0 R/W
−
TO0 R/W
−
TOE0 R/W
−
TOL0R/W
−
TOM0 R/W
−
IICCTL00
IICCTL01
IICWL0R/W
IICWH0R/W
CRC0
CTL
PGCR
CL
R/W
R/W
R/W
R/W
√ √ −
√ √ −
− √ −
− √ −
− √ −
√ √ −
− − √
− − √
Remark For SFRs in the SFR area, see Table 3-5 SFR List.
Manipulable Bit Range Address
1-bit8-bit16-bit
√ √
− −
√ √
− −
√ √
− −
− − √
− √
− −
√ √
− −
− √
− −
− √
− −
√
√
√
√
√
√
√
00H F0230H
00H F0231H
FFH F0232H
FFH F0233H
00H F0234H
00H F02F0H
0000H F02F2H
0000H F02FAH
After Reset
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
R01UH0305EJ0200 Rev.2.00 78
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is applied only to branch instructions.
Figure 3-13. Outline of Relative Addressing
PC
Instruction code
OP code
DISPLACE
8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-14. Example of CALL !!addr20/BR !!addr20
PC
Instruction code
OP code
Low Addr.
High Addr.
Seg Addr.
Figure 3-15. Example of CALL !addr16/BR !addr16
PC
PC
S
PC
H
PC
L
Instruction code
OP code
0000
Low Addr.
High Addr.
R01UH0305EJ0200 Rev.2.00 79
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RL78/G1A CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT
instructions.
In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-16. Outline of Table Indirect Addressing
OP code
0000000010
Table address
0
0000
PC
PCPCHPC
S
High Addr.
Low Addr.
Memory
L
R01UH0305EJ0200 Rev.2.00 80
Jul 04, 2013
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