Renesas F-ZTAT H8 Series, F-ZTAT H8/300H Series, F-ZTAT H8/3052B Series, F-ZTAT HD64F3052BTE, F-ZTAT HD64F3052BF Hardware Manual

REJ09B0302-0300

The revision list can be viewed directly by
clicking the title page.

The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.

H8/3052B F-ZTAT™

16

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8 Family/H8/300H Series

H8/3052B HD64F3052BTE

HD64F3052BF

Rev. 3.00
Revision Date: Mar 21, 2006

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third­party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.

Rev. 3.00 Mar 21, 2006 page ii of xxviii

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass­through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.

Rev. 3.00 Mar 21, 2006 page iii of xxviii

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Main Revisions for This Edition

The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.

5. Contents

6Overview

7. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.

8. List of Registers

9. Electrical Characteristics

10. Appendix

Rev. 3.00 Mar 21, 2006 page iv of xxviii

Preface

The H8/3052BF is a group of high-performance microcontrollers that integrate system supporting
functions together with an H8/300H CPU core.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.

The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been
expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to
reduce power consumption in battery-powered applications: individual modules can be placed in
standby, and the frequency of the system clock supplied to the chip can be divided down under
software control.

The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.

With these features, the H8/3052BF can be used to implement compact, high-performance
systems easily.

The H8/3052BF has an F-ZTAT* version with on-chip flash memory that can be programmed

on-board. These versions enable users to respond quickly and flexibly to changing application
specifications.

This manual describes the H8/3052BF hardware. For details of the instruction set, refer to the
H8/300H Series Software Manual.

Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp.

Rev. 3.00 Mar 21, 2006 page v of xxviii

Rev. 3.00 Mar 21, 2006 page vi of xxviii

Main Revisions for this Edition

Item Page Revisions (See Manual for Details)

All  Nortification of change in company name amended

(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.

Products deleted

H8/3052F-ZTAT (HD64F3052F and HD64F3052TE) and
H8/3052F-ZTAT B mask 3 V versions (HD64F3052BVF
and HD64F3052BVTE) deleted

1.1 Overview

Table 1.1 Features

1.2 Block Diagram

Figure 1.1 Block
Diagram

5 Table amended

Product lineup

Product Type Product Code P ackage (Package Code)

H8/3052F-ZTAT
B mask version

6 Figure amended

5V version HD64F3052BF

HD64F3052BTE

CC

VCLVCCV

100-pin QFP (FP-100B)
100-pin TQFP (TFP-100B)

1.3.1 Pin Arrangement

Figure 1.2 Pin
Arrangement (FP-100B
or TFP-100B, Top View)

1.3.2 Pin Assignments in
Each Mode

Table 1.2 Pin
Assignments in Each
Mode (FP-100B or TFP­100B)

7 Figure amended

123

*

0

1

8

9

CL

V

3

3

TIOCA /TP /PB

TIOCB /TP /PB

1

0.1 µF

Note: * An external capacitor must be connected to the V

8, 11, 12 Table and note amended

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

1
87

Notes: 1. An external capacitor must be connected when this pin functions as the VCL pin.

V
P8

IRQ

*

CL

/RFSH/

0

1

0

1

*

V

CL

P80/RFSH/

IRQ

0

V

CL

P80/RFSH/

IRQ

Rev. 3.00 Mar 21, 2006 page vii of xxviii

pin.

CL

Pin Name

1

*

0

1

*

V

CL

P80/RFSH/

IRQ

0

1

*

V

CL

P80/RFSH/

IRQ

0

1

*

V

CL

P80/RFSH/

IRQ

0

1

*

V

CL

P80/IRQ

0

Item Page Revisions (See Manual for Details)

1.3.3 Pin Functions

Table 1.3 Pin Functions

13, 17 Table amended and note deleted

Type Symbol Pin No.

Power V

CC

35, 68

V

SS

V

CL

6.3.6 Interconnections

138 Figure amended

with Memory (Example)

A to A

Figure 6.18

19 1

Interconnections with
Memory (Example)

7.3.4 Interval Timer 176 Description amended

Timing of Setting of Compare Match Flag and Clearing by
Compare Match: The CMF flag in
compare match signal output when the RTCOR and
RTCNT values match.

8.4.4 Repeat Mode

214 Table amended

Table 8.8 Register
Functions in Repeat Mode

Register

70
ETCRH

11, 22, 44,
57, 65, 92

1

EPROM

A to A

0

18

I/O to I/O

8

15

I/O to I/O

0

7

CE
OE

Activated by
SCI 0 Receive­Data-Full
Interrupt

Transfer
counter

RTMCSR is set to 1 by a

Function

Other
Activation

Transfer
counter

Rev. 3.00 Mar 21, 2006 page viii of xxviii

70

ETCRL

Hold transfer
count

Hold transfer
count

Item Page Revisions (See Manual for Details)

n

9.1 Overview

Table 9.1 Port Functions

9.11.3 Pin Functions

Table 9.19 Port A Pin
Functions

13.3.3 Multiprocessor

247 Figure amended

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port A 8-bit I/O port

Schmitt

inputs output

PA7/TP7/
TIOCB

PA

6

TIOCA
PA5/TP5/
TIOCB
PA4/TP4/
TIOCA

287 Table amended

TIOCB

output

PA

5

1

input

TIOCB

Pin
function

479 Figure amended

/TP6/

PA
out-

2/A20

2/A21

1/A22

1/A23

put

1

5

input

/CS

4

/CS

5

/CS

6

TP

5

out-

put

*

Output (TP7) from
programmable
timing pattern
controller (TPC),
input or output
(TIOCB

) for 16-bit

2

integrated timer unit
(ITU), and generic
input/output

TPC output (TP6 to
TP

), ITU input and

4

output (TIOCA
TIOCB
CS
and generic input/
output

, TIOCA1),

1

to CS6 output,

4

CS

TIOCB

5

out-

output

put

,

2

Address output
(A

)

20

TPC output (TP
TP

), ITU input and

4

output (TIOCA
TIOCB
address output (A
to A21), CS4 to CS
output, and generic
input/output

PA

PA

5

1

input

out-

put

TIOCB

Communication

Stop

Figure 13.13 Example of
SCI Receive Operation

Start

Data (da

bit

bit

1

0 D0

(8-Bit Data with
Multiprocessor Bit and
One Stop Bit)

, TIOCA1),

1

TP

5

out-

put

input

1

Address

TPC
output
(TP

),

7

ITU input
or output
(TIOCB
and
generic
input/
output

to

TPC

6

output
(TP

,

to

2

6

), ITU

TP

4

input and

23

output

6

(TIOCA
TIOCB
TIOCA

to

CS

4

CS

6

output,
and
generic
input/
output

A

CS

5

22

out-

out-

put

put

*

),

2

,

2

,

1

),

1

5

output
(A

)

20

TPC
output
(TP

to

6

), ITU

TP

4

input and
output
(TIOCA
TIOCB
TIOCA
address
output
(A

to

23

A

), CS

21

to CS
output,
and
generic
input/out
put

TIOCB

output

6

,

2

,

1

),

1

4

1

TPC
output
(TP7),
ITU input
or output
(TIOCB
and
generic
input/
output

TPC
output
(TP
TP

4

input and
output
(TIOCA
TIOCB
TIOCA
and
generic
input/
output

PA

5

input

TIOCB

to

6

), ITU

PA
out-

),

2

,

2

,

1

),

1

5

put

i

1

13.3.4 Synchronous
Operation

Figure 13.16 Sample
Flowchart for Serial
Transmitting

482 Figure amended

1. SCI initialization: the transmit data output function
of the TxD pin is selected automatically.

RXI interrupt handler
reads RDR data and
clears RDRF flag to 0

a. Own ID does not match data

Rev. 3.00 Mar 21, 2006 page ix of xxviii

Item Page Revisions (See Manual for Details)

K

14.3.4 Register Settings

Table 14.3 Register
Settings in Smart Card

506 Table amended

Register Address

SMR H'FFB0 GM 0 1 O/E 1 0 CKS1 C

1

*

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi

Interface

18.8.2 Software
Protection

593 Note amended

2. When not erasing, clear all EBR1, EBR2 bits to
Table 18.11 Software
Protection

18.7.3 Notes on
Program/Program-Verify
Procedure

Table 18.9 Additional-

587

Table amended

Result of Verify-Read
after Write Pulse

X'

Application (V)

(Y)
Result of Operation Comments

Programming Data
Computation Table

18.10.1 Socket Adapters
and Memory Map

Table 18.12 H8/3052BF
Socket Adapter Product
Codes

19.2.1 Connecting a
Crystal Resonator

600 Table amended

Product Code Package Socket Adapter Product Code Manufacturer

HD64F3052BF 100-pin QFP

HD64F3052BTE 100-pin TQFP

HD64F3052BF 100-pin QFP

HD64F3052BTE 100-pin TQFP

(FP-100B)

(TFP-100B)

(FP-100B)

(TFP-100B)

609 Description amended

Circuit Configuration: A crystal resonator can be

ME3064ESHF1H Minato Electronics

ME3064ESNF1H

HF306BQ100D4001 Data IO Japan

HF306BT100D4001

connected as in the example in figure 19.2. The damping
resistance Rd should be selected according to table 19.1

Use capacitors with the characteristics listed in table

(1).

19.1 (2) for external capacitors CL1 and CL2. An AT-cut

parallel-resonance crystal should be used.

19.2.2 External Clock

611 Figure amended

Input

Figure 19.5 External
Clock Input (Examples)

EXTAL

XTAL

74HC04

H'00.

External clock input

Rev. 3.00 Mar 21, 2006 page x of xxviii

b. Complementary clock input at XTAL pin

Item Page Revisions (See Manual for Details)

20.4.3 Selection of
Waiting Time for Exit from
Software Standby Mode

Table 20.3 Clock

625 Table amended

DIV1 DIV0 STS2 STS1 STS0

010008192

Waiting
Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz

0.91 1.02 1.4 1.6 2.0 2.7 4.1

states

Frequency and Waiting
Time for Clock to Settle

Section 21 Electrical

631 to 658 “Preliminary” deleted

Characteristics

21.1 Absolute Maximum
Ratings

Table 21.1 Absolute
Maximum Ratings

21.2.1 DC

631 Table and note amended

Item Symbol Value Unit

Power supply voltage V
Programming voltage

(FWE)
Analog power supply voltage AV
Notes: Connect an external capacitor to the V

pin and ground.

HD64F3052B V

Deleted

–0.3 to +7.0 V

CC

–0.3 to VCC + 0.3 V

in

–0.3 to +7.0 V

CC

pin. Connect an external capacitor between this

CL

Characteristics

Table 21.2 (2) DC
Characteristics

Table 21.3 Permissible
Output Currents

634 Conditions amended

Conditions: V

= 5.0 V ±10%, AVCC = 5.0 V ±10%, V

CC

4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to
+75°C

21.2.2 AC Characteristics

636, 637 Condition A, Condition B, and note deleted

Table 21.4 Bus Timing

Table 21.5 Refresh

637 Condition A, Condition B, and note deleted

Controller Bus Timing

Table 21.6 Control Signal
Timing

638

Condition A and Condition B deleted

Table and notes amended

Item

Interrupt pulse width
(NMI,

IRQ2 to IRQ0 when exiting

software standby mode)

REF

=

Rev. 3.00 Mar 21, 2006 page xi of xxviii

Item Page Revisions (See Manual for Details)

21.2.2 AC Characteristics

Table 21.7 Timing of On-

639 Condition A and Condition B deleted

Table and notes amended

Chip Supporting Modules

21.2.3 A/D Conversion
Characteristics

Item Symbol Min Max Unit

DMAC

ITU

640Condition A and Condition B deleted

Table and notes amended

DREQ setup time t
DREQ hold time t
TEND delay time 1 t
TEND delay time 2 t

Timer output delay time t
Timer input setup time t
Timer clock input setup time t
Timer clock

pulse width

Single edge t
Both edges t

DRQS

DRQH

TED1

TED2

TOCD

TICS

TCKS

TCKWH

TCKWL

20 —
10 —

— 50
— 50
— 50

40 —
40 —

1.5 — t

2.5 — t

Table 21.8 A/D Converter
Characteristics

Item Min Typ Max

Conversion time 5.36 ——
Notes: 1 The value is for φ ≤ 13 MHz.

2 The value is for φ > 13 MHz.

21.2.4 D/A Conversion

641 Condition A and Condition B deleted

Characteristics

Table 21.9 D/A Converter
Characteristics

21.2.5 Flash Memory
Characteristics

642, 643 Condition A and Condition B deleted

Table and notes amended
Table 21.10 Flash
Memory Characteristics

A.1 Instruction List

Table A.1 Instruction Set

2. Arithmetic instructions

663 Table amended

Item Symbol Min Typ Max Unit Notes

Reprogramming count N
Data retention period T

Notes:

6. Minimum cycle value which guarantees all characteristics after reprogramming.
(Reprogram cycles from 1 to minimum value are guaranteed.)

7. Reference characteristics at 25˚C. (This is a indication that reprogram operation can
normally function up to this figure.)

8. Data retention characteristics when reprogaram performed correctly within
specification value including minimum data retention period.

Mnemonic Operation

DAA Rd Rd8 decimal adjust

Operand Size

B2— 2

→ Rd8

*

100

WEC

8

*

10

DRP

Addressing Mode and

Instruction Length (bytes)

#xxRn@ERn

@(d, ERn)

Conditions

Conditions

Conditions

6

7

*

10.000

— Times

——Years

Condition Code

@–ERn/@ERn+

@aa

@(d, PC)

@@aa

—

IHNZVC

ns

ns

cyc

scyc

↔↔↔

Test
Conditions

Figure 21.16

Figure 21.24,
Figure 21.25

Figure 21.20

Figure 21.21

No. of

States

Normal

*

↔

*1

Advanced

Rev. 3.00 Mar 21, 2006 page xii of xxviii

Item Page Revisions (See Manual for Details)

E.2 Timing of Recovery

807 Figure amended
from Hardware Standby
Mode

STBY

Figure E.1 Timing of
Recovery from Hardware
Standby Mode (2)

RES

Appendix F Product
Code Lineup

Table F.1 H8/3052B F­ZTAT Product Code
Lineup

Appendix G Package
Dimensions

Figure G.1 Package
Dimensions (FP-100B)

Figure G.2 Package
Dimensions (TFP-100B)

Appendix H Differences
from H8/3048F-ZTAT

Table H.1 Differences
between H8/3052

B F­ZTAT and H8/3048F­ZTAT

808 Table amended

Product Type Product Code Mark Code

H8/3052 F-ZTAT
B mask version

5 V version

813 Figure amended

814 Figure amended

811 to 814 Table amended

Item H8/3048F-ZTAT H8/3052B F-ZTAT

Pin specifications Pin 1 V

Pin 10 VPP/RESO Pin 10 FWE

Package

HD64F3052BTE HD64F3052BTE 100-pin TQFP (TFP-100B)
HD64F3052BF HD64F3052BF 100-pin QFP (FP-100B)

CC

(Package Code)

5 V Operation
Pin 1 → V

CL

Connected to VSS, with external
connection of 0.1 µF capacitor

Rev. 3.00 Mar 21, 2006 page xiii of xxviii

Rev. 3.00 Mar 21, 2006 page xiv of xxviii

Contents

Section 1 Overview............................................................................................................. 1

1.1 Overview........................................................................................................................... 1

1.2 Block Diagram .................................................................................................................. 6

1.3 Pin Description.................................................................................................................. 7

1.3.1 Pin Arrangement .................................................................................................. 7

1.3.2 Pin Assignments in Each Mode ........................................................................... 8

1.3.3 Pin Functions ....................................................................................................... 13

Section 2 CPU ...................................................................................................................... 19

2.1 Overview........................................................................................................................... 19

2.1.1 Features................................................................................................................ 19

2.1.2 Differences from H8/300 CPU ............................................................................ 20

2.2 CPU Operating Modes ...................................................................................................... 21

2.3 Address Space................................................................................................................... 22

2.4 Register Configuration...................................................................................................... 23

2.4.1 Overview.............................................................................................................. 23

2.4.2 General Registers................................................................................................. 24

2.4.3 Control Registers ................................................................................................. 25

2.4.4 Initial CPU Register Values................................................................................. 26

2.5 Data Formats..................................................................................................................... 27

2.5.1 General Register Data Formats ............................................................................ 27

2.5.2 Memory Data Formats ......................................................................................... 29

2.6 Instruction Set ................................................................................................................... 30

2.6.1 Instruction Set Overview ..................................................................................... 30

2.6.2 Instructions and Addressing Modes..................................................................... 31

2.6.3 Tables of Instructions Classified by Function...................................................... 32

2.6.4 Basic Instruction Formats .................................................................................... 42

2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 43

2.7 Addressing Modes and Effective Address Calculation..................................................... 44

2.7.1 Addressing Modes ............................................................................................... 44

2.7.2 Effective Address Calculation.............................................................................. 47

2.8 Processing States............................................................................................................... 51

2.8.1 Overview.............................................................................................................. 51

2.8.2 Program Execution State...................................................................................... 52

2.8.3 Exception-Handling State .................................................................................... 52

2.8.4 Exception-Handling Sequences ........................................................................... 54

2.8.5 Bus-Released State............................................................................................... 55

Rev. 3.00 Mar 21, 2006 page xv of xxviii

2.8.6 Reset State............................................................................................................ 55

2.8.7 Power-Down State ............................................................................................... 55

2.9 Basic Operational Timing ................................................................................................. 56

2.9.1 Overview.............................................................................................................. 56

2.9.2 On-Chip Memory Access Timing........................................................................ 56

2.9.3 On-Chip Supporting Module Access Timing....................................................... 57

2.9.4 Access to External Address Space....................................................................... 58

Section 3 MCU Operating Modes .................................................................................. 59

3.1 Overview........................................................................................................................... 59

3.1.1 Operating Mode Selection ................................................................................... 59

3.1.2 Register Configuration......................................................................................... 60

3.2 Mode Control Register (MDCR)....................................................................................... 60

3.3 System Control Register (SYSCR) ................................................................................... 61

3.4 Operating Mode Descriptions ........................................................................................... 63

3.4.1 Mode 1 ................................................................................................................. 63

3.4.2 Mode 2 ................................................................................................................. 63

3.4.3 Mode 3 ................................................................................................................. 63

3.4.4 Mode 4 ................................................................................................................. 63

3.4.5 Mode 5 ................................................................................................................. 63

3.4.6 Mode 6 ................................................................................................................. 64

3.4.7 Mode 7 ................................................................................................................. 64

3.5 Pin Functions in Each Operating Mode ............................................................................ 64

3.6 Memory Map in Each Operating Mode ............................................................................ 65

Section 4 Exception Handling ......................................................................................... 69

4.1 Overview........................................................................................................................... 69

4.1.1 Exception Handling Types and Priority............................................................... 69

4.1.2 Exception Handling Operation............................................................................. 69

4.1.3 Exception Sources and Vector Table ................................................................... 70

4.2 Reset ................................................................................................................................. 72

4.2.1 Overview.............................................................................................................. 72

4.2.2 Reset Sequence .................................................................................................... 72

4.2.3 Interrupts after Reset............................................................................................ 75

4.3 Interrupts........................................................................................................................... 76

4.4 Trap Instruction................................................................................................................. 77

4.5 Stack Status after Exception Handling.............................................................................. 77

4.6 Notes on Use of the Stack ................................................................................................. 78

Rev. 3.00 Mar 21, 2006 page xvi of xxviii

Section 5 Interrupt Controller .......................................................................................... 79

5.1 Overview........................................................................................................................... 79

5.1.1 Features................................................................................................................ 79

5.1.2 Block Diagram..................................................................................................... 80

5.1.3 Pin Configuration................................................................................................. 81

5.1.4 Register Configuration......................................................................................... 81

5.2 Register Descriptions ........................................................................................................82

5.2.1 System Control Register (SYSCR)...................................................................... 82

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 83

5.2.3 IRQ Status Register (ISR).................................................................................... 89

5.2.4 IRQ Enable Register (IER) .................................................................................. 90

5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 91

5.3 Interrupt Sources............................................................................................................... 92

5.3.1 External Interrupts ............................................................................................... 92

5.3.2 Internal Interrupts................................................................................................. 93

5.3.3 Interrupt Exception Vector Table ........................................................................ 93

5.4 Interrupt Operation............................................................................................................ 97

5.4.1 Interrupt Handling Process................................................................................... 97

5.4.2 Interrupt Exception Handling Sequence .............................................................. 102

5.4.3 Interrupt Response Time...................................................................................... 103

5.5 Usage Notes ...................................................................................................................... 104

5.5.1 Contention between Interrupt Generation and Disabling..................................... 104

5.5.2 Instructions that Inhibit Interrupts........................................................................ 105

5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 105

5.5.4 Notes on Use of External Interrupts..................................................................... 105

Section 6 Bus Controller.................................................................................................... 109

6.1 Overview........................................................................................................................... 109

6.1.1 Features................................................................................................................ 109

6.1.2 Block Diagram..................................................................................................... 110

6.1.3 Pin Configuration................................................................................................. 111

6.1.4 Register Configuration......................................................................................... 112

6.2 Register Descriptions ........................................................................................................ 112

6.2.1 Bus Width Control Register (ABWCR)............................................................... 112

6.2.2 Access State Control Register (ASTCR) ............................................................. 113

6.2.3 Wait Control Register (WCR).............................................................................. 114

6.2.4 Wait State Controller Enable Register (WCER).................................................. 115

6.2.5 Bus Release Control Register (BRCR) ................................................................ 116

6.2.6 Chip Select Control Register (CSCR).................................................................. 118

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6.3 Operation........................................................................................................................... 119

6.3.1 Area Division....................................................................................................... 119

6.3.2 Chip Select Signals .............................................................................................. 121

6.3.3 Data Bus............................................................................................................... 122

6.3.4 Bus Control Signal Timing .................................................................................. 123

6.3.5 Wait Modes.......................................................................................................... 131

6.3.6 Interconnections with Memory (Example) .......................................................... 137

6.3.7 Bus Arbiter Operation.......................................................................................... 139

6.4 Usage Notes ...................................................................................................................... 142

6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM...................................... 142

6.4.2 Register Write Timing ......................................................................................... 142

6.4.3 BREQ Input Timing............................................................................................. 144

6.4.4 Transition to Software Standby Mode ................................................................. 144

Section 7 Refresh Controller ............................................................................................ 145

7.1 Overview........................................................................................................................... 145

7.1.1 Features................................................................................................................ 145

7.1.2 Block Diagram..................................................................................................... 147

7.1.3 Pin Configuration................................................................................................. 148

7.1.4 Register Configuration......................................................................................... 148

7.2 Register Descriptions ........................................................................................................ 149

7.2.1 Refresh Control Register (RFSHCR)................................................................... 149

7.2.2 Refresh Timer Control/Status Register (RTMCSR) ............................................ 152

7.2.3 Refresh Timer Counter (RTCNT)........................................................................ 153

7.2.4 Refresh Time Constant Register (RTCOR) ......................................................... 154

7.3 Operation........................................................................................................................... 155

7.3.1 Overview.............................................................................................................. 155

7.3.2 DRAM Refresh Control....................................................................................... 157

7.3.3 Pseudo-Static RAM Refresh Control................................................................... 172

7.3.4 Interval Timer ...................................................................................................... 176

7.4 Interrupt Source................................................................................................................. 182

7.5 Usage Notes ...................................................................................................................... 182

Section 8 DMA Controller................................................................................................ 185

8.1 Overview........................................................................................................................... 185

8.1.1 Features................................................................................................................ 185

8.1.2 Block Diagram..................................................................................................... 186

8.1.3 Functional Overview............................................................................................ 187

8.1.4 Pin Configuration................................................................................................. 189

8.1.5 Register Configuration......................................................................................... 189

Rev. 3.00 Mar 21, 2006 page xviii of xxviii

8.2 Register Descriptions (Short Address Mode).................................................................... 191

8.2.1 Memory Address Registers (MAR) ..................................................................... 192

8.2.2 I/O Address Registers (IOAR)............................................................................. 193

8.2.3 Execute Transfer Count Registers (ETCR).......................................................... 194

8.2.4 Data Transfer Control Registers (DTCR) ............................................................ 195

8.3 Register Descriptions (Full Address Mode)...................................................................... 198

8.3.1 Memory Address Registers (MAR) ..................................................................... 198

8.3.2 I/O Address Registers (IOAR)............................................................................. 199

8.3.3 Execute Transfer Count Registers (ETCR).......................................................... 199

8.3.4 Data Transfer Control Registers (DTCR) ............................................................ 201

8.4 Operation........................................................................................................................... 206

8.4.1 Overview.............................................................................................................. 206

8.4.2 I/O Mode.............................................................................................................. 208

8.4.3 Idle Mode............................................................................................................. 210

8.4.4 Repeat Mode ........................................................................................................ 213

8.4.5 Normal Mode....................................................................................................... 217

8.4.6 Block Transfer Mode ........................................................................................... 220

8.4.7 DMAC Activation................................................................................................ 225

8.4.8 DMAC Bus Cycle................................................................................................ 227

8.4.9 DMAC Multiple-Channel Operation ................................................................... 233

8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 234

8.4.11 NMI Interrupts and DMAC.................................................................................. 235

8.4.12 Aborting a DMA Transfer.................................................................................... 236

8.4.13 Exiting Full Address Mode.................................................................................. 237

8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 238

8.5 Interrupts........................................................................................................................... 239

8.6 Usage Notes ...................................................................................................................... 240

8.6.1 Note on Word Data Transfer................................................................................ 240

8.6.2 DMAC Self-Access ............................................................................................. 240

8.6.3 Longword Access to Memory Address Registers ................................................ 240

8.6.4 Note on Full Address Mode Setup....................................................................... 240

8.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 240

8.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 242

8.6.7 Memory and I/O Address Register Values .......................................................... 242

8.6.8 Bus Cycle when Transfer Is Aborted................................................................... 243

Section 9 I/O Ports .............................................................................................................. 245

9.1 Overview........................................................................................................................... 245

9.2 Port 1................................................................................................................................. 249

9.2.1 Overview.............................................................................................................. 249

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9.2.2 Register Configuration......................................................................................... 250

9.3 Port 2................................................................................................................................. 252

9.3.1 Overview.............................................................................................................. 252

9.3.2 Register Configuration......................................................................................... 253

9.4 Port 3................................................................................................................................. 256

9.4.1 Overview.............................................................................................................. 256

9.4.2 Register Configuration......................................................................................... 256

9.5 Port 4................................................................................................................................. 258

9.5.1 Overview.............................................................................................................. 258

9.5.2 Register Configuration......................................................................................... 259

9.6 Port 5................................................................................................................................. 262

9.6.1 Overview.............................................................................................................. 262

9.6.2 Register Configuration......................................................................................... 263

9.7 Port 6................................................................................................................................. 266

9.7.1 Overview.............................................................................................................. 266

9.7.2 Register Configuration......................................................................................... 267

9.8 Port 7................................................................................................................................. 270

9.8.1 Overview.............................................................................................................. 270

9.8.2 Register Configuration......................................................................................... 271

9.9 Port 8................................................................................................................................. 272

9.9.1 Overview.............................................................................................................. 272

9.9.2 Register Configuration......................................................................................... 273

9.10 Port 9................................................................................................................................. 277

9.10.1 Overview.............................................................................................................. 277

9.10.2 Register Configuration......................................................................................... 278

9.11 Port A ................................................................................................................................ 281

9.11.1 Overview.............................................................................................................. 281

9.11.2 Register Configuration......................................................................................... 283

9.11.3 Pin Functions ....................................................................................................... 285

9.12 Port B ................................................................................................................................ 293

9.12.1 Overview.............................................................................................................. 293

9.12.2 Register Configuration......................................................................................... 295

9.12.3 Pin Functions ....................................................................................................... 297

Section 10 16-Bit Integrated Timer Unit (ITU).......................................................... 303

10.1 Overview........................................................................................................................... 303

10.1.1 Features................................................................................................................ 303

10.1.2 Block Diagrams ................................................................................................... 306

10.1.3 Pin Configuration................................................................................................. 311

10.1.4 Register Configuration......................................................................................... 312

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10.2 Register Descriptions ........................................................................................................ 315

10.2.1 Timer Start Register (TSTR)................................................................................ 315

10.2.2 Timer Synchro Register (TSNC) ......................................................................... 316

10.2.3 Timer Mode Register (TMDR) ............................................................................ 318

10.2.4 Timer Function Control Register (TFCR)............................................................ 321

10.2.5 Timer Output Master Enable Register (TOER) ................................................... 323

10.2.6 Timer Output Control Register (TOCR).............................................................. 325

10.2.7 Timer Counters (TCNT) ...................................................................................... 326

10.2.8 General Registers (GRA, GRB)........................................................................... 327

10.2.9 Buffer Registers (BRA, BRB) ............................................................................. 328

10.2.10 Timer Control Registers (TCR) ........................................................................... 329

10.2.11 Timer I/O Control Register (TIOR) ..................................................................... 331

10.2.12 Timer Status Register (TSR)................................................................................ 333

10.2.13 Timer Interrupt Enable Register (TIER).............................................................. 335

10.3 CPU Interface.................................................................................................................... 337

10.3.1 16-Bit Accessible Registers ................................................................................. 337

10.3.2 8-Bit Accessible Registers ................................................................................... 339

10.4 Operation........................................................................................................................... 340

10.4.1 Overview.............................................................................................................. 340

10.4.2 Basic Functions.................................................................................................... 341

10.4.3 Synchronization ................................................................................................... 350

10.4.4 PWM Mode.......................................................................................................... 351

10.4.5 Reset-Synchronized PWM Mode......................................................................... 355

10.4.6 Complementary PWM Mode ............................................................................... 358

10.4.7 Phase Counting Mode.......................................................................................... 367

10.4.8 Buffering.............................................................................................................. 369

10.4.9 ITU Output Timing .............................................................................................. 376

10.5 Interrupts ........................................................................................................................... 378

10.5.1 Setting of Status Flags.......................................................................................... 378

10.5.2 Clearing of Status Flags ....................................................................................... 380

10.5.3 Interrupt Sources and DMA Controller Activation.............................................. 381

10.6 Usage Notes ...................................................................................................................... 382

Section 11 Programmable Timing Pattern Controller............................................... 397

11.1 Overview........................................................................................................................... 397

11.1.1 Features................................................................................................................ 397

11.1.2 Block Diagram..................................................................................................... 398

11.1.3 Pin Configuration................................................................................................. 399

11.1.4 Register Configuration......................................................................................... 400

11.2 Register Descriptions ........................................................................................................ 401

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11.2.1 Port A Data Direction Register (PADDR) ........................................................... 401

11.2.2 Port A Data Register (PADR).............................................................................. 401

11.2.3 Port B Data Direction Register (PBDDR) ........................................................... 402

11.2.4 Port B Data Register (PBDR) .............................................................................. 402

11.2.5 Next Data Register A (NDRA)............................................................................ 403

11.2.6 Next Data Register B (NDRB)............................................................................. 405

11.2.7 Next Data Enable Register A (NDERA).............................................................. 407

11.2.8 Next Data Enable Register B (NDERB) .............................................................. 408

11.2.9 TPC Output Control Register (TPCR) ................................................................. 409

11.2.10 TPC Output Mode Register (TPMR) ................................................................... 411

11.3 Operation........................................................................................................................... 413

11.3.1 Overview.............................................................................................................. 413

11.3.2 Output Timing...................................................................................................... 414

11.3.3 Normal TPC Output............................................................................................. 415

11.3.4 Non-Overlapping TPC Output............................................................................. 417

11.3.5 TPC Output Triggering by Input Capture ............................................................ 419

11.4 Usage Notes ...................................................................................................................... 420

11.4.1 Operation of TPC Output Pins............................................................................. 420

11.4.2 Note on Non-Overlapping Output........................................................................ 420

Section 12 Watchdog Timer............................................................................................. 423

12.1 Overview........................................................................................................................... 423

12.1.1 Features................................................................................................................ 423

12.1.2 Block Diagram..................................................................................................... 424

12.1.3 Register Configuration......................................................................................... 424

12.2 Register Descriptions ........................................................................................................ 425

12.2.1 Timer Counter (TCNT)........................................................................................ 425

12.2.2 Timer Control/Status Register (TCSR)................................................................ 426

12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 428

12.2.4 Notes on Register Access..................................................................................... 429

12.3 Operation........................................................................................................................... 430

12.3.1 Watchdog Timer Operation ................................................................................. 430

12.3.2 Interval Timer Operation ..................................................................................... 431

12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 432

12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 433

12.4 Interrupts ........................................................................................................................... 434

12.5 Usage Notes ...................................................................................................................... 434

Section 13 Serial Communication Interface ................................................................ 435

13.1 Overview........................................................................................................................... 435

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13.1.1 Features................................................................................................................ 435

13.1.2 Block Diagram..................................................................................................... 437

13.1.3 Pin Configuration................................................................................................. 438

13.1.4 Register Configuration......................................................................................... 438

13.2 Register Descriptions ........................................................................................................ 439

13.2.1 Receive Shift Register (RSR) .............................................................................. 439

13.2.2 Receive Data Register (RDR) .............................................................................. 439

13.2.3 Transmit Shift Register (TSR) ............................................................................. 440

13.2.4 Transmit Data Register (TDR)............................................................................. 440

13.2.5 Serial Mode Register (SMR)................................................................................ 441

13.2.6 Serial Control Register (SCR).............................................................................. 444

13.2.7 Serial Status Register (SSR) ................................................................................ 448

13.2.8 Bit Rate Register (BRR) ...................................................................................... 452

13.3 Operation........................................................................................................................... 462

13.3.1 Overview.............................................................................................................. 462

13.3.2 Operation in Asynchronous Mode ....................................................................... 464

13.3.3 Multiprocessor Communication........................................................................... 473

13.3.4 Synchronous Operation........................................................................................ 480

13.4 SCI Interrupts.................................................................................................................... 488

13.5 Usage Notes ...................................................................................................................... 489

Section 14 Smart Card Interface ..................................................................................... 495

14.1 Overview........................................................................................................................... 495

14.1.1 Features................................................................................................................ 495

14.1.2 Block Diagram..................................................................................................... 496

14.1.3 Pin Configuration................................................................................................. 497

14.1.4 Register Configuration......................................................................................... 497

14.2 Register Descriptions ........................................................................................................ 498

14.2.1 Smart Card Mode Register (SCMR).................................................................... 498

14.2.2 Serial Status Register (SSR) ................................................................................ 499

14.2.3 Serial Mode Register (SMR)................................................................................ 501

14.2.4 Serial Control Register (SCR).............................................................................. 502

14.3 Operation........................................................................................................................... 503

14.3.1 Overview.............................................................................................................. 503

14.3.2 Pin Connections ................................................................................................... 503

14.3.3 Data Format ......................................................................................................... 505

14.3.4 Register Settings .................................................................................................. 506

14.3.5 Clock.................................................................................................................... 508

14.3.6 Transmitting and Receiving Data......................................................................... 510

14.4 Usage Notes ...................................................................................................................... 517

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Section 15 A/D Converter................................................................................................. 521

15.1 Overview........................................................................................................................... 521

15.1.1 Features................................................................................................................ 521

15.1.2 Block Diagram..................................................................................................... 522

15.1.3 Pin Configuration................................................................................................. 523

15.1.4 Register Configuration......................................................................................... 524

15.2 Register Descriptions ........................................................................................................ 525

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 525

15.2.2 A/D Control/Status Register (ADCSR) ............................................................... 526

15.2.3 A/D Control Register (ADCR) ............................................................................ 528

15.3 CPU Interface.................................................................................................................... 529

15.4 Operation........................................................................................................................... 530

15.4.1 Single Mode (SCAN = 0) .................................................................................... 530

15.4.2 Scan Mode (SCAN = 1)....................................................................................... 532

15.4.3 Input Sampling and A/D Conversion Time.......................................................... 534

15.4.4 External Trigger Input Timing............................................................................. 535

15.5 Interrupts ........................................................................................................................... 536

15.6 Usage Notes ...................................................................................................................... 536

Section 16 D/A Converter................................................................................................. 543

16.1 Overview........................................................................................................................... 543

16.1.1 Features................................................................................................................ 543

16.1.2 Block Diagram..................................................................................................... 544

16.1.3 Pin Configuration................................................................................................. 545

16.1.4 Register Configuration......................................................................................... 545

16.2 Register Descriptions ........................................................................................................ 546

16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 546

16.2.2 D/A Control Register (DACR) ............................................................................ 546

16.2.3 D/A Standby Control Register (DASTCR).......................................................... 548

16.3 Operation........................................................................................................................... 549

16.4 D/A Output Control .......................................................................................................... 550

Section 17 RAM .................................................................................................................. 551

17.1 Overview........................................................................................................................... 551

17.1.1 Block Diagram..................................................................................................... 552

17.1.2 Register Configuration......................................................................................... 553

17.2 System Control Register (SYSCR) ................................................................................... 553

17.3 Operation........................................................................................................................... 554

Section 18 ROM .................................................................................................................. 555

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18.1 Features ............................................................................................................................. 555

18.2 Overview........................................................................................................................... 556

18.2.1 Block Diagram..................................................................................................... 556

18.2.2 Mode Transitions ................................................................................................. 556

18.2.3 On-Board Programming Modes........................................................................... 559

18.2.4 Flash Memory Emulation in RAM ...................................................................... 561

18.2.5 Differences between Boot Mode and User Program Mode ................................. 562

18.2.6 Block Configuration............................................................................................. 563

18.3 Pin Configuration.............................................................................................................. 564

18.4 Register Configuration...................................................................................................... 564

18.5 Register Descriptions ........................................................................................................ 565

18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 565

18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 568

18.5.3 Erase Block Register 1 (EBR1) ........................................................................... 571

18.5.4 Erase Block Register 2 (EBR2) ........................................................................... 571

18.5.5 RAM Control Register (RAMCR)....................................................................... 572

18.6 On-Board Programming Modes........................................................................................ 574

18.6.1 Boot Mode ........................................................................................................... 574

18.6.2 User Program Mode............................................................................................. 580

18.7 Programming/Erasing Flash Memory ............................................................................... 582

18.7.1 Program Mode ..................................................................................................... 584

18.7.2 Program-Verify Mode.......................................................................................... 585

18.7.3 Notes on Program/Program-Verify Procedure..................................................... 585

18.7.4 Erase Mode.......................................................................................................... 589

18.7.5 Erase-Verify Mode............................................................................................... 589

18.8 Protection .......................................................................................................................... 591

18.8.1 Hardware Protection ............................................................................................ 591

18.8.2 Software Protection.............................................................................................. 593

18.8.3 Error Protection.................................................................................................... 594

18.8.4 NMI Input Disable Conditions............................................................................. 595

18.9 Flash Memory Emulation in RAM.................................................................................... 597

18.10 Flash Memory PROM Mode............................................................................................. 599

18.10.1 Socket Adapters and Memory Map...................................................................... 599

18.10.2 Notes on Use of PROM Mode ............................................................................. 600

18.11 Notes on Flash Memory Programming/Erasing................................................................ 601

Section 19 Clock Pulse Generator .................................................................................. 607

19.1 Overview........................................................................................................................... 607

19.1.1 Block Diagram..................................................................................................... 608

19.2 Oscillator Circuit............................................................................................................... 609

Rev. 3.00 Mar 21, 2006 page xxv of xxviii

19.2.1 Connecting a Crystal Resonator........................................................................... 609

19.2.2 External Clock Input............................................................................................ 611

19.3 Duty Adjustment Circuit................................................................................................... 613

19.4 Prescalers .......................................................................................................................... 613

19.5 Frequency Divider............................................................................................................. 613

19.5.1 Register Configuration......................................................................................... 614

19.5.2 Division Control Register (DIVCR) .................................................................... 614

19.5.3 Usage Notes ......................................................................................................... 615

Section 20 Power-Down State ......................................................................................... 617

20.1 Overview........................................................................................................................... 617

20.2 Register Configuration...................................................................................................... 619

20.2.1 System Control Register (SYSCR) ...................................................................... 619

20.2.2 Module Standby Control Register (MSTCR)....................................................... 621

20.3 Sleep Mode ....................................................................................................................... 623

20.3.1 Transition to Sleep Mode..................................................................................... 623

20.3.2 Exit from Sleep Mode.......................................................................................... 623

20.4 Software Standby Mode.................................................................................................... 624

20.4.1 Transition to Software Standby Mode ................................................................. 624

20.4.2 Exit from Software Standby Mode ...................................................................... 624

20.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 625

20.4.4 Sample Application of Software Standby Mode.................................................. 627

20.4.5 Note...................................................................................................................... 627

20.5 Hardware Standby Mode .................................................................................................. 628

20.5.1 Transition to Hardware Standby Mode................................................................ 628

20.5.2 Exit from Hardware Standby Mode ..................................................................... 628

20.5.3 Timing for Hardware Standby Mode ................................................................... 628

20.6 Module Standby Function................................................................................................. 629

20.6.1 Module Standby Timing ...................................................................................... 629

20.6.2 Read/Write in Module Standby............................................................................ 629

20.6.3 Usage Notes ......................................................................................................... 629

20.7 System Clock Output Disabling Function......................................................................... 630

Section 21 Electrical Characteristics.............................................................................. 631

21.1 Absolute Maximum Ratings ............................................................................................. 631

21.2 Electrical Characteristics................................................................................................... 632

21.2.1 DC Characteristics ............................................................................................... 632

21.2.2 AC Characteristics ............................................................................................... 636

21.2.3 A/D Conversion Characteristics........................................................................... 640

21.2.4 D/A Conversion Characteristics........................................................................... 641

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21.2.5 Flash Memory Characteristics.............................................................................. 642

21.3 Operational Timing ........................................................................................................... 643

21.3.1 Bus Timing .......................................................................................................... 643

21.3.2 Refresh Controller Bus Timing............................................................................ 647

21.3.3 Control Signal Timing ......................................................................................... 652

21.3.4 Clock Timing ....................................................................................................... 654

21.3.5 TPC and I/O Port Timing..................................................................................... 654

21.3.6 ITU Timing.......................................................................................................... 655

21.3.7 SCI Input/Output Timing..................................................................................... 656

21.3.8 DMAC Timing..................................................................................................... 657

Appendix A Instruction Set .............................................................................................. 659

A.1 Instruction List .................................................................................................................. 659

A.2 Operation Code Map......................................................................................................... 674

A.3 Number of States Required for Execution ........................................................................ 677

Appendix B Internal I/O Register................................................................................... 687

B.1 Addresses .......................................................................................................................... 687

B.2 Function ............................................................................................................................ 695

Appendix C I/O Port Block Diagrams........................................................................... 776

C.1 Port 1 Block Diagram ....................................................................................................... 776

C.2 Port 2 Block Diagram ....................................................................................................... 777

C.3 Port 3 Block Diagram ....................................................................................................... 778

C.4 Port 4 Block Diagram ....................................................................................................... 779

C.5 Port 5 Block Diagram ....................................................................................................... 780

C.6 Port 6 Block Diagrams...................................................................................................... 781

C.7 Port 7 Block Diagrams...................................................................................................... 785

C.8 Port 8 Block Diagrams...................................................................................................... 786

C.9 Port 9 Block Diagrams...................................................................................................... 789

C.10 Port A Block Diagrams ..................................................................................................... 793

C.11 Port B Block Diagrams ..................................................................................................... 797

Appendix D Pin States ....................................................................................................... 801

D.1 Port States in Each Mode .................................................................................................. 801

D.2 Pin States at Reset ............................................................................................................. 804

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

E.1 Timing of Transition to Hardware Standby Mode............................................................ 807

........................................................................... 807

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E.2 Timing of Recovery from Hardware Standby Mode......................................................... 807

Appendix F Product Code Lineup .................................................................................. 808

Appendix G Package Dimensions .................................................................................. 809

Appendix H Differences from H8/3048F-ZTAT ....................................................... 811

Rev. 3.00 Mar 21, 2006 page xxviii of xxviii

Section 1 Overview

Section 1 Overview

1.1 Overview

The H8/3052BF is a group of microcontrollers (MCUs) that integrate system supporting functions
together with an H8/300H CPU core having an original Renesas Technology architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.

The H8/3052BF has 512 kbytes of ROM and 8 kbytes of RAM.

Seven MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 7) include one single-chip mode and six expanded modes.

The H8/3052BF has an F-ZTAT™* version with on-chip flash memory that can be programmed
on-board.

Table 1.1 summarizes the features of the H8/3052BF.

Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp.

Rev. 3.00 Mar 21, 2006 page 1 of 814

REJ09B0302-0300

Section 1 Overview

Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

• General-register machine
 Sixteen 16-bit general registers

(also usable as + eight 16-bit registers or eight 32-bit registers)

• High-speed operation
 Maximum clock rate: 25 MHz
 Add/subtract: 80 ns
 Multiply/divide: 560 ns
 16-Mbyte address space

• Instruction features
 8/16/32-bit data transfer, arithmetic, and logic instructions
 Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16

bits)

 Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16

bits)

 Bit accumulator function
 Bit manipulation instructions with register-indirect specification of bit

positions

Memory

Interrupt
controller

• Flash memory: 512 kbytes

• RAM: 8 kbytes

• Seven external interrupt pins: NMI, IRQ

• 30 internal interrupts

• Three selectable interrupt priority levels

to IRQ

0

5

Rev. 3.00 Mar 21, 2006 page 2 of 814
REJ09B0302-0300

Feature Description

Bus controller

Refresh
controller

DMA controller
(DMAC)

• Address space can be partitioned into eight areas, with independent bus

specifications in each area

• Chip select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state access selectable for each area

• Selection of four wait modes

• Bus arbitration function

• DRAM refresh
 Directly connectable to 16-bit-wide DRAM
 CAS-before-RAS refresh
 Self-refresh mode selectable

• Pseudo-static RAM refresh
 Self-refresh mode selectable

• Usable as an interval timer

• Short address mode
 Maximum four channels available
 Selection of I/O mode, idle mode, or repeat mode
 Can be activated by compare match/input capture A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from
SCI channel 0, or external requests

• Full address mode
 Maximum two channels available
 Selection of normal mode or block transfer mode
 Can be activated by compare match/input capture A interrupts from ITU

channels 0 to 3, external requests, or auto-request

Section 1 Overview

Rev. 3.00 Mar 21, 2006 page 3 of 814

REJ09B0302-0300

Section 1 Overview

Feature Description

16-bit integrated
timer unit (ITU)

Programmable
timing pattern
controller (TPC)

Watchdog timer
(WDT),
1 channel

Serial
communication
interface (SCI),
2 channels

A/D converter

• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or

10 pulse inputs

• 16-bit timer counter (channels 0 to 4)

• Two multiplexed output compare/input capture pins (channels 0 to 4)

• Operation can be synchronized (channels 0 to 4)

• PWM mode available (channels 0 to 4)

• Phase counting mode available (channel 2)

• Buffering available (channels 3 and 4)

• Reset-synchronized PWM mode available (channels 3 and 4)

• Complementary PWM mode available (channels 3 and 4)

• DMAC can be activated by compare match/input capture A interrupts

(channels 0 to 3)

• Maximum 16-bit pulse output, using ITU as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

• Output data can be transferred by DMAC

• Reset signal can be generated by overflow

• Usable as an interval timer

• Selection of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface functions added (SCI0 only)

• Resolution: 10 bits

• Eight channels, with selection of single or scan mode

• Variable analog conversion voltage range

• Sample-and-hold function

• A/D conversion can be externally triggered

Rev. 3.00 Mar 21, 2006 page 4 of 814
REJ09B0302-0300

Feature Description

D/A converter

• Resolution: 8 bits

• Two channels

• D/A outputs can be sustained in software standby mode

I/O ports

• 70 input/output pins

• 9 input-only pins

Operating
modes

• Seven MCU operating modes

Mode Address Space Address Pins Initial Bus Width Max. Bus Width

Mode 1 1 Mbyte A

Mode 2 1 Mbyte A19 to A

Mode 3 16 Mbytes A23 to A

Mode 4 16 Mbytes A23 to A

Mode 5 1 Mbyte A19 to A

Mode 6 16 Mbytes A23 to A

Mode 7 1 Mbyte — — —

• On-chip ROM is disabled in modes 1 to 4

Power-down
state

• Sleep mode

• Software standby mode

• Hardware standby mode

• Module standby function

• Programmable system clock frequency division

Other features

• On-chip clock pulse generator

19

to A

Section 1 Overview

0

0

0

0

0

0

8 bits 16 bits

16 bits 16 bits

8 bits 16 bits

16 bits 16 bits

8 bits 16 bits

8 bits 16 bits

Product lineup

Product Type Product Code Package (Package Code)

H8/3052F-ZTAT
B mask version

5V version HD64F3052BF

HD64F3052BTE

100-pin QFP (FP-100B)

100-pin TQFP (TFP-100B)

Rev. 3.00 Mar 21, 2006 page 5 of 814

REJ09B0302-0300

Section 1 Overview

1.2 Block Diagram

Figure 1.1 shows an internal block diagram.

generator

Clock pulse

ROM

(flash memory)

RAM

16-bit integrated

timer unit

(ITU)

Programmable

timing pattern

controller (TPC)

SS

MD
MD
MD

EXTAL

XTAL

STBY

RES
FWE

P66/LWR

P6

/HWR

5

P6

4

P6

3

P6

/BACK

2

P6

/BREQ

1

P6

/WAIT

0

P84/CS
P83/CS1/IRQ
P82/CS2/IRQ
P81/CS3/IRQ

P80/RFSH/IRQ

NMI

/RD

/AS

VCLVCCVCCVSSVSSVSSVSSVSSV

2
1
0

φ

Interrupt controller

Port 6

0
3
2

Port 8

1
0

15

14

13

12

11

10

/D

/D

/D

7

6

5

P3

P3

P3

9

/D

/D

/D

/D

4

3

2

1

P3

P3

P3

P3

Port 3 Port 4

Address bus

Data bus (upper)

Data bus (lower)

H8/300H CPU

DMA controller

(DMAC)

Refresh

controller

Watchdog timer

(WDT)

Serial communication

interface

×

(SCI) 2 channels

A/D converter

D/A converter

8

/D

0

P3

7

6

/D

/D

7

6

P4

P4

Bus controller

5

4

3

2

1

/D

/D

5

4

P4

P4

0

/D

/D

/D

/D

3

2

1

0

P4

P4

P4

P4

P53/A

19

P52/A

18

P51/A

Port 5Port 9

17

P50/A

16

P27/A

15

P26/A

14

P25/A

13

P24/A

12

P23/A

Port 2

11

P22/A

10

P21/A

9

P20/A

8

P17/A

7

P16/A

6

P15/A

5

P14/A

4

P13/A

Port 1

3

P12/A

2

P11/A

1

P10/A

0

P95/SCK1/IRQ
P94/SCK0/IRQ
P93/RxD
P92/RxD
P91/TxD
P90/TxD

5

4
1
0

1
0

Port B

7

4

4

4

4

3

/TIOCB

/TIOCA

11

/TP

/TP

3

PB

PB

10
2

/TIOCB

/TIOCA

9

/TP

/TP

1

PB

PB

3

8
0

/CS

0

/ADTRG

1

/DREQ

14

/DREQ

/TP

15

6

/TP

PB

7

PB

/TOCXB

/TOCXA

13

12

/TP

/TP

5

4

PB

PB

Figure 1.1 Block Diagram

Rev. 3.00 Mar 21, 2006 page 6 of 814
REJ09B0302-0300

20

/A

/CS

2

/A

/TIOCB

7

/TP

/TIOCA

7

PA

/TP
PA

4

21
2

6
6

Port A

5

/CS

/CS

22

/A

/A

1

/TIOCB

/TIOCA

5

/TP

/TP

5

PA

PA

6

23
1

4
4

/TCLKD

/TCLKC

0

0

/TIOCB

/TIOCA

3

2

/TP

/TP

3

2

PA

PA

/TCLKB

/TCLKA

1

0

/TEND

/TEND

1

0

/TP

/TP

1

0

PA

PA

Port 7

1

0

5

4

3

2

1

SS

CC

REF

/DA

/DA

/AN

7

/AN
P7

/AN

6

5

4

P7

P7

/AN

7

6

P7

V

AV

AV

/AN
P7

0

/AN

/AN

/AN

3

2

1

0

P7

P7

P7

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1.2 shows the pin arrangement of the H8/3052BF.

Section 1 Overview

AV

V

P7 /AN

0

P7 /AN

1

P7 /AN

2

P7 /AN

3

P7 /AN

4

P7 /AN

5

P7 /AN /DA

676

P7 /AN /DA

7

AV

P8 /RFSH/IRQ

P8 /CS /IRQ

1

3

P8 /CS /IRQ

2

2

P8 /CS /IRQ

3

1

P8 /CS

40

PA /TP /TEND /TCLKA

00

PA /TP /TEND /TCLKB

11

PA /TP /TIOCA /TCLKC

22 0

PA /TP /TIOCB /TCLKD

33 0

PA /TP /TIOCA /A /CS

44 1

PA /TP /TIOCB /A /CS

55 122

PA /TP /TIOCA /A

66 221

PA /TP /TIOCB /A

0
1

23

/CS

7

7

2

1

0.1 µF

REF

V

210

654

3

CC

MDMDMD

P6 /LWR

P6 /HWR

P6 /RD

P6 /ASVXTAL

75747372717069686766656463626160595857565554535251

76

CC

77
78

0

79

1

80

2

81

3

82

4

83

5

84

0

85

1

86

SS

87

00

88

1

89

2

90

3

91
92

SS

93

SS

EXTALVNMI

Top view

(FP-100B, TFP-100B)

RES

STBYφP6 /BACK

210

P6 /BREQ

P6 /WAITVP5 /A

94
95
96
97

6

98

5

99

4

100

20

12345678910111213141516171819202122232425

0123456

*

CL

V

8

9

1011121314

3 3444

TIOCA /TP /PB

TIOCB /TP /PB

TIOCA /TP /PB

TIOCB /TP /PB

7

FWE

15

0

1

4

/DREQ /TP /PB

TOCXA /TP /PB

TOCXB /TP /PB

7

CS

012345012

SS

V

010101012

TxD /P9

TxD /P9

RxD /P9

RxD /P9

4

5

IRQ /SCK /P9

IRQ /SCK /P9

D /P4

ADTRG/DREQ /TP /PB

1918171615
32107

SS

P5 /A

3SS456

3

D /P4

D /P4

D /P4

P5 /A

V

P5 /A

P2 /A

456

D /P4

D /P4

14
6

P2 /A

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

D /P4

A /P2

13

A /P2

12

A /P2

11

A /P2

10

A /P2

9

A /P2
V

SS

A /P1

7

A /P1

6

A /P1

5

A /P1

4

A /P1

3

A /P1

2

A /P1

1

A /P1

0

V

CC

D /P3

15

D /P3

14

D /P3

13

D /P3

12

D /P3

11

D /P3

10

D /P3

9

D /P3

8

D /P4

7

5

4

3
2

018

7
6

5
4
3
2
1
0

7
6
5
4
3

2
1
0

7

Note: * An external capacitor must be connected to the V

Figure 1.2 Pin Arrangement (FP-100B or TFP-100B, Top View)

pin.

CL

Rev. 3.00 Mar 21, 2006 page 7 of 814

REJ09B0302-0300

Section 1 Overview

1.3.2 Pin Assignments in Each Mode

Table 1.2 lists the pin assignments in each mode.

Table 1.2 Pin Assignments in Each Mode (FP-100B or TFP-100B)

Pin Name

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

1

1

2PB

3PB

4PB

5PB

6PB

7PB

8PB

*

V

CL

/TP8/

0

TIOCA

/TP9/

1

TIOCB

/TP10/

2

TIOCA

/TP11/

3

TIOCB

/TP12/

4

TOCXA

/TP13/

5

TOCXB

/TP14/

6

3

3

4

4

4

4

DREQ0/
CS

7

9PB

/TP15/

7

DREQ1/
ADTRG

10 FEW FWE FWE FWE FWE FWE FWE

11 V

SS

12 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD

13 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD

14 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD

15 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD

16 P94/SCK0/

IRQ

4

17 P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

3

PB1/TP9/
TIOCB

3

PB2/TP10/
TIOCA

4

PB3/TP11/
TIOCB

4

PB4/TP12/
TOCXA

4

PB5/TP13/
TOCXB

4

PB6/TP14/

DREQ0/
CS

7

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

3

PB1/TP9/
TIOCB

3

PB2/TP10/
TIOCA

4

PB3/TP11/
TIOCB

4

PB4/TP12/
TOCXA

4

PB5/TP13/
TOCXB

4

PB6/TP14/

DREQ0/
CS

7

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

3

PB1/TP9/
TIOCB

3

PB2/TP10/
TIOCA

4

PB3/TP11/
TIOCB

4

PB4/TP12/
TOCXA

4

PB5/TP13/
TOCXB

4

PB6/TP14/

DREQ0/
CS

7

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

3

PB1/TP9/
TIOCB

3

PB2/TP10/
TIOCA

4

PB3/TP11/
TIOCB

4

PB4/TP12/
TOCXA

4

PB5/TP13/
TOCXB

4

PB6/TP14/

DREQ0/
CS

7

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

3

PB1/TP9/
TIOCB

3

PB2/TP10/
TIOCA

4

PB3/TP11/
TIOCB

4

PB4/TP12/
TOCXA

4

PB5/TP13/
TOCXB

4

PB6/TP14/

DREQ0/
CS

7

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

1

*

V

CL

PB0/TP8/
TIOCA

PB1/TP9/
TIOCB

PB2/TP10/
TIOCA

PB3/TP11/
TIOCB

PB4/TP12/
TOCXA

PB5/TP13/
TOCXB

PB6/TP14/

DREQ

0

PB7/TP15/

DREQ1/
ADTRG

V

SS

P94/SCK0/

IRQ

4

P95/SCK1/

IRQ

5

3

3

4

4

4

4

0

1

0

1

Rev. 3.00 Mar 21, 2006 page 8 of 814
REJ09B0302-0300

Section 1 Overview

Pin Name

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

18

19

20

21

22 V

23

24

25

26

27 D

28 D

29 D

30 D

31 D

32 D

33 D

34 D

35 V

36 A

37 A

38 A

39 A

40 A

41 A

42 A

43 A

44 V

45 A

46 A

P4

0/D0

P4

1/D1

P4

2/D2

P4

3/D3

SS

P44/D

P45/D

P46/D

P4

7/D7

8

9

10

11

12

13

14

15

CC

0

1

2

3

4

5

6

7

SS

8

9

2

*

P40/D

2

*

P41/D

2

*

P42/D

2

*

P43/D

V

2

*

P44/D

4

2

*

P45/D

5

2

*

P46/D

6

2

*

P47/D

D

D

D

D

D

D

D

D

V

A

A

A

A

A

A

A

A

V

A

A

SS

CC

0

1

2

3

4

5

6

7

SS

8

9

3

*

P40/D

0

3

*

P41/D

1

3

*

P42/D

2

3

*

P43/D

3

V

3

*

P44/D

4

3

*

P45/D

5

3

*

P46/D

6

3

*

P47/D

7

8

9

10

11

12

13

14

15

D

D

D

D

D

D

D

D

V

A

A

A

A

A

A

A

A

V

A

A

SS

8

9

10

11

12

13

14

15

CC

0

1

2

3

4

5

6

7

SS

8

9

2

*

P40/D

0

2

*

P41/D

1

2

*

P42/D

2

2

*

P43/D

3

V

2

*

P44/D

4

2

*

P45/D

5

2

*

P46/D

6

2

*

P47/D

7

D

D

D

D

D

D

D

D

V

A

A

A

A

A

A

A

A

V

A

A

SS

8

9

10

11

12

13

14

15

CC

0

1

2

3

4

5

6

7

SS

8

9

3

*

P40/D

0

3

*

P41/D

1

3

*

P42/D

2

3

*

P43/D

3

V

3

*

P44/D

4

3

*

P45/D

5

3

*

P46/D

6

3

*

P47/D

7

D

D

D

D

D

D

D

D

V

P10/A

P11/A

P12/A

P13/A

P14/A

P15/A

P16/A

P17/A

V

P20/A

P21/A

SS

8

9

10

11

12

13

14

15

CC

SS

2

*

P40/D

0

2

*

P41/D

1

2

*

P42/D

2

2

*

P43/D

3

V

2

*

P44/D

4

2

*

P45/D

5

2

*

P46/D

6

2

*

P47/D

7

D

D

D

D

D

D

D

D

V

P10/A

0

P11/A

1

P12/A

2

P13/A

3

P14/A

4

P15/A

5

P16/A

6

P17/A

7

V

P20/A

8

P21/A

9

SS

8

9

10

11

12

13

14

15

CC

SS

2

*

P4

P4

P4

P4

V

P4

P4

P4

P4

P3

P3

P3

P3

P3

P3

P3

P3

V

P1

P1

P1

P1

P1

P1

P1

P1

V

P2

P2

0

1

2

3

SS

4

5

6

7

0

1

2

3

4

5

6

7

CC

0

1

2

3

4

5

6

7

SS

0

1

0

2

*

1

2

*

2

2

*

3

2

*

4

2

*

5

2

*

6

2

*

7

0

1

2

3

4

5

6

7

8

9

Rev. 3.00 Mar 21, 2006 page 9 of 814

REJ09B0302-0300

Section 1 Overview

Pin Name

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

47 A

48 A

49 A

50 A

51 A

52 A

53 A

54 A

55 A

56 A

57 V

58

59

60

10

11

12

13

14

15

16

17

18

19

SS

/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT

P6

0

/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ

P6

1

/BACK P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK

P6

2

A

10

A

11

A

12

A

13

A

14

A

15

A

16

A

17

A

18

A

19

V

SS

A

10

A

11

A

12

A

13

A

14

A

15

A

16

A

17

A

18

A

19

V

SS

A

10

A

11

A

12

A

13

A

14

A

15

A

16

A

17

A

18

A

19

V

SS

P22/A

P23/A

P24/A

P25/A

P26/A

P27/A

P50/A

P51/A

P52/A

P53/A

V

SS

P22/A

10

P23/A

11

P24/A

12

P25/A

13

P26/A

14

P27/A

15

P50/A

16

P51/A

17

P52/A

18

P53/A

19

V

SS

P2

10

11

12

13

14

15

16

17

18

19

P2

P2

P2

P2

P2

P5

P5

P5

P5

V

P6

P6

P6

2

3

4

5

6

7

0

1

2

3

SS

0

1

2

61 φφφφφφφ

62

63

STBY STBY STBY STBY STBY STBY STBY

RES RES RES RES RES RES RES

64 NMI NMI NMI NMI NMI NMI NMI

65 V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

66 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL

67 XTAL XTAL XTAL XTAL XTAL XTAL XTAL

68 V

69

70

71

72

CC

AS AS AS AS AS AS

RD RD RD RD RD RD

HWR HWR HWR HWR HWR HWR

LWR LWR LWR LWR LWR LWR

73 MD

74 MD

75 MD

0

1

2

V

CC

MD

MD

MD

V

CC

0

1

2

MD

MD

MD

0

1

2

V

CC

MD

MD

MD

V

CC

0

1

2

MD

MD

MD

0

1

2

V

MD

MD

MD

CC

V

CC

P6

3

P6

4

P6

5

P6

6

0

1

2

MD

MD

MD

0

1

2

Rev. 3.00 Mar 21, 2006 page 10 of 814
REJ09B0302-0300

Section 1 Overview

Pin Name

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

76 AV

77 V

CC

REF

78 P70/AN

79 P71/AN

80 P72/AN

81 P73/AN

82 P74/AN

83 P75/AN

84 P76/AN6/

DA

0

85 P77/AN7/

DA

1

86 AV

87

88

89

90

91

92 V

P8

IRQ

P8

IRQ

P8

IRQ

P8

IRQ

P8

SS

SS

/RFSH/

0

0

/CS3/

1

1

/CS2/

2

2

/CS1/

3

3

/CS

4

93 PA0/TP0/

TEND0/

TCLKA

94 PA1/TP1/

TEND1/

TCLKB

95 PA2/TP2/

TIOCA

0

TCLKC

0

1

2

3

4

5

0

/

AV

CC

V

REF

P70/AN

0

P71/AN

1

P72/AN

2

P73/AN

3

P74/AN

4

P75/AN

5

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/RFSH/

IRQ

0

P81/CS3/

IRQ

1

P82/CS2/

IRQ

2

P83/CS1/

IRQ

3

P84/CS

0

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA

/

0

TCLKC

AV

CC

V

REF

P70/AN

0

P71/AN

1

P72/AN

2

P73/AN

3

P74/AN

4

P75/AN

5

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/RFSH/

IRQ

0

P81/CS3/

IRQ

1

P82/CS2/

IRQ

2

P83/CS1/

IRQ

3

P84/CS

0

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA

/

0

TCLKC

AV

CC

V

REF

P70/AN

0

P71/AN

1

P72/AN

2

P73/AN

3

P74/AN

4

P75/AN

5

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/RFSH/

IRQ

0

P81/CS3/

IRQ

1

P82/CS2/

IRQ

2

P83/CS1/

IRQ

3

P84/CS

0

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA

/

0

TCLKC

AV

CC

V

REF

P70/AN

0

P71/AN

1

P72/AN

2

P73/AN

3

P74/AN

4

P75/AN

5

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/RFSH/

IRQ

0

P81/CS3/

IRQ

1

P82/CS2/

IRQ

2

P83/CS1/

IRQ

3

P84/CS

0

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA

/

0

TCLKC

AV

CC

V

REF

P70/AN

0

P71/AN

1

P72/AN

2

P73/AN

3

P74/AN

4

P75/AN

5

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/RFSH/

IRQ

0

P81/CS3/

IRQ

1

P82/CS2/

IRQ

2

P83/CS1/

IRQ

3

P84/CS

0

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA

/

0

TCLKC

AV

CC

V

REF

P70/AN

P71/AN

P72/AN

P73/AN

P74/AN

P75/AN

P76/AN6/
DA

0

P77/AN7/
DA

1

AV

SS

P80/IRQ

P81/IRQ

P82/IRQ

P83/IRQ

P8

4

V

SS

PA0/TP0/

TEND0/

TCLKA

PA1/TP1/

TEND1/

TCLKB

PA

/TP2/

2

TIOCA
TCLKC

0

1

2

3

4

5

0

1

2

3

/

0

Rev. 3.00 Mar 21, 2006 page 11 of 814

REJ09B0302-0300

Section 1 Overview

Pin Name

Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

96 PA3/TP3/

TIOCB
TCLKD

97 PA4/TP4/

TIOCA

CS

6

98 PA5/TP5/

TIOCB

CS

5

99 PA6/TP6/

TIOCA

CS

4

100 PA7/TP7/

TIOCB

0

1

1

2

2

/

/

/

/

PA

/TP3/

3

TIOCB
TCLKD

PA4/TP4/
TIOCA

CS

6

PA5/TP5/
TIOCB

CS

5

PA6/TP6/
TIOCA

CS

4

PA7/TP7/
TIOCB

0

1

1

2

2

/

/

/

/

PA

/TP3/

3

TIOCB

0

TCLKD

PA4/TP4/
TIOCA

1

CS

6

PA5/TP5/
TIOCB

1

CS

5

PA6/TP6/
TIOCA

2

CS

4

A

20

/

/

/

/

PA

/TP3/

3

TIOCB

0

TCLKD

PA4/TP4/
TIOCA

1

CS

6

PA5/TP5/
TIOCB

1

CS

5

PA6/TP6/
TIOCA

2

CS

4

A

20

/

/

/

/

PA

/TP3/

3

TIOCB
TCLKD

PA4/TP4/
TIOCA

CS

6

PA5/TP5/
TIOCB

CS

5

PA6/TP6/
TIOCA

CS

4

PA7/TP7/
TIOCB

0

1

1

2

2

/

/

/

/

PA

/TP3/

3

TIOCB
TCLKD

PA4/TP4/
TIOCA
A23/CS

PA5/TP5/
TIOCB
A22/CS

PA6/TP6/
TIOCA
A21/CS

A

20

/

0

/

1

6

/

1

5

/

2

4

PA
TIOCB
TCLKD

PA4/TP4/
TIOCA

PA5/TP5/
TIOCB

PA6/TP6/
TIOCA

PA7/TP7/
TIOCB

Notes: 1. An external capacitor must be connected when this pin functions as the VCL pin.

2. In modes 1, 3, 5, and 6 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected
after a reset, but they can be changed by software.

3. In modes 2 and 4 the D

to D7 functions of pins P40/D0 to P47/D7 are selected after a

0

reset, but they can be changed by software.

/TP3/

3

/

0

1

1

2

2

Rev. 3.00 Mar 21, 2006 page 12 of 814
REJ09B0302-0300

Section 1 Overview

1.3.3 Pin Functions

Table 1.3 summarizes the pin functions.

Table 1.3 Pin Functions

Type Symbol Pin No. I/O Name and Function

Power V

CC

V

SS

V

CL

Clock XTAL 67 Input For connection to a crystal resonator.

EXTAL 66 Input For connection to a crystal resonator or

φ 61 Output System clock: Supplies the system clock

Operating mode

MD2 to MD075 to 73 Input Mode 2 to mode 0: For setting the

control

35, 68 Input Power: For connection to the power supply.

Connect all V

pins to the system power

CC

supply.

11, 22, 44,
57, 65, 92

Input Ground: For connection to ground (0 V).

Connect all V

pins to the 0-V system

SS

power supply.

1 Input Connect an external capacitor between this

pin and GND (0 V).

V

CL

0.1 µF

For examples of crystal resonator and
external clock input, see section 19, Clock
Pulse Generator.

input of an external clock signal. For
examples of crystal resonator and external
clock input, see section 19, Clock Pulse
Generator.

to external devices.

operating mode, as follows. Inputs at these
pins must not be changed during operation.

MD

MD

2

MD0Operating Mode

1

000—

0 0 1 Mode 1

0 1 0 Mode 2

0 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

1 1 0 Mode 6

1 1 1 Mode 7

Rev. 3.00 Mar 21, 2006 page 13 of 814

REJ09B0302-0300

Section 1 Overview

Type Symbol Pin No. I/O Name and Function

System control RES 63 Input Reset input: When driven low, this pin

resets the chip

FWE 10 Input Flash write enable: Allows program mode

setting.

STBY 62 Input Standby: When driven low, this pin forces a

transition to hardware standby mode

BREQ 59 Input Bus request: Used by an external bus

master to request the bus right

BACK 60 Output Bus request acknowledge: Indicates that

the bus has been granted to an external bus
master

Interrupts NMI 64 Input Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ5 to IRQ017, 16,

Address bus A23 to A

0

90 to 87

97 to 100,

Input Interrupt request 5 to 0: Maskable

interrupt request pins

Output Address bus: Outputs address signals
56 to 45,
43 to 36

Data bus D15 to D

Bus control CS7 to CS08, 97 to 99,

0

34 to 23,
21 to 18

Input/

Data bus: Bidirectional data bus

output

Output Chip select: Select signals for areas 7 to 0
88 to 91

AS 69 Output Address strobe: Goes low to indicate valid

address output on the address bus

RD 70 Output Read: Goes low to indicate reading from

the external address space

HWR 71 Output High write: Goes low to indicate writing to

the external address space; indicates valid
data on the upper data bus (D

to D8).

15

LWR 72 Output Low write: Goes low to indicate writing to

the external address space; indicates valid
data on the lower data bus (D7 to D0).

WAIT 58 Input Wait: Requests insertion of wait states in

bus cycles during access to the external
address space

Rev. 3.00 Mar 21, 2006 page 14 of 814
REJ09B0302-0300

Type Symbol Pin No. I/O Name and Function

Refresh
controller

RFSH 87 Output Refresh: Indicates a refresh cycle
CS

3

88 Output Row address strobe RAS

strobe signal for DRAM connected to area 3

RD 70 Output Column address strobe CAS

address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.

Write enable WE

WE: Write enable signal for

WEWE

DRAM connected to area 3; used with
2CAS DRAM.

HWR 71 Output Upper write UW

UW: Write enable signal for

UWUW

DRAM connected to area 3; used with 2WE
DRAM.

Upper column address strobe UCAS

Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.

LWR 72 Output Lower write LW

LW: Write enable signal for

LWLW

DRAM connected to area 3; used with 2WE
DRAM.

Lower column address strobe LCAS

Column address strobe signal for DRAM
connected to area 3; used with 2CAS
DRAM.

DMA controller
(DMAC)

DREQ1,
DREQ

TEND
TEND

1

0

9, 8 Input DMA request 1 and 0: DMAC activation

0

,

94, 93 Output Transfer end 1 and 0: These signals

requests

indicate that the DMAC has ended a data
transfer

timer unit (ITU)

TCLKD to
TCLKA

TIOCA
TIOCA

96 to 93 Input Clock input D to A: External clock inputs16-bit integrated

to

4, 2, 99,

4

97, 95

0

Input/
output

Input capture/output compare A4 to A0:

GRA4 to GRA0 output compare or input
capture, or PWM output

TIOCB4 to
TIOCB

0

5, 3, 100,
98, 96

Input/
output

Input capture/output compare B4 to B0:

GRB4 to GRB0 output compare or input
capture, or PWM output

TOCXA

TOCXB

6 Output Output compare XA4: PWM output

4

7 Output Output compare XB4: PWM output

4

Section 1 Overview

RAS: Row address

RASRAS

CAS: Column

CASCAS

UCAS:

UCASUCAS

LCAS:

LCASLCAS

Rev. 3.00 Mar 21, 2006 page 15 of 814

REJ09B0302-0300

Section 1 Overview

Type Symbol Pin No. I/O Name and Function

Programmable
timing pattern

to TP09 to 2,

TP

15

100 to 93

Output TPC output 15 to 0: Pulse output

controller (TPC)

Serial
communication
interface (SCI)

TxD1, TxD013, 12 Output Transmit data (channels 0 and 1):

SCI data output

, RxD015, 14 Input Receive data (channels 0 and 1):

RxD

1

SCI data input

SCK1, SCK017, 16 Input/

output

Serial clock (channels 0 and 1):

SCI clock input/output

A/D converter AN7 to AN085 to 78 Input Analog 7 to 0: Analog input pins

ADTRG 9 Input A/D trigger: External trigger input for

starting A/D conversion

D/A converter DA1, DA

85, 84 Output Analog output: Analog output from the D/A

0

converter

A/D and D/A
converters

AV

CC

76 Input Power supply pin for the A/D and D/A

converters. Connect to the system power
supply (+5 V) when not using the A/D and
D/A converters.

AV

SS

86 Input Ground pin for the A/D and D/A converters.

Connect to system ground (0 V).

V

REF

77 Input Reference voltage input pin for the A/D and

D/A converters. Connect to the system
power supply (+5 V) when not using the A/D
and D/A converters.

I/O ports P17 to P1043 to 36 Input/

output

Port 1: Eight input/output pins.
The direction of each pin can be selected in
the port 1 data direction register (P1DDR).

P27 to P2052 to 45 Input/

output

Port 2: Eight input/output pins.
The direction of each pin can be selected in
the port 2 data direction register (P2DDR).

P37 to P3034 to 27 Input/

output

Port 3: Eight input/output pins.
The direction of each pin can be selected in
the port 3 data direction register (P3DDR).

P47 to P4026 to 23,

21 to 18

Input/

output

Port 4: Eight input/output pins.
The direction of each pin can be selected in
the port 4 data direction register (P4DDR).

Rev. 3.00 Mar 21, 2006 page 16 of 814
REJ09B0302-0300

Type Symbol Pin No. I/O Name and Function

I/O ports P5

to P5056 to 53 Input/

3

output

Port 5: Four input/output pins. The direction
of each pin can be selected in the port 5
data direction register (P5DDR).

P66 to P6072 to 69,

60 to 58

Input/
output

Port 6: Seven input/output pins. The
direction of each pin can be selected in the
port 6 data direction register (P6DDR).

P77 to P7085 to 78 Input Port 7: Eight input pins

P84 to P8091 to 87 Input/

output

Port 8: Five input/output pins. The direction
of each pin can be selected in the port 8
data direction register (P8DDR).

P95 to P9017 to 12 Input/

output

Port 9: Six input/output pins. The direction
of each pin can be selected in the port 9
data direction register (P9DDR).

PA7 to PA0100 to 93 Input/

output

Port A: Eight input/output pins. The
direction of each pin can be selected in the
port A data direction register (PADDR).

PB7 to PB09 to 2 Input/

output

Port B: Eight input/output pins. The
direction of each pin can be selected in the
port B data direction register (PBDDR).

Section 1 Overview

Rev. 3.00 Mar 21, 2006 page 17 of 814

REJ09B0302-0300

Section 1 Overview

Rev. 3.00 Mar 21, 2006 page 18 of 814
REJ09B0302-0300

Section 2 CPU

Section 2 CPU

2.1 Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

2.1.1 Features

The H8/300H CPU has the following features.

• Upward compatibility with H8/300 CPU

Can execute H8/300 Series object programs

• General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• Sixty-two basic instructions
 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions

• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, or @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8, PC) or @(d:16, PC)]
 Memory indirect [@@aa:8]

• 16-Mbyte linear address space

• High-speed operation
 All frequently-used instructions execute in two to four states
 Maximum clock frequency: 25 MHz
 8/16/32-bit register-register add/subtract: 80 ns
 8 × 8-bit register-register multiply: 560 ns
 16 ÷ 8-bit register-register divide: 560 ns

Rev. 3.00 Mar 21, 2006 page 19 of 814

REJ09B0302-0300

Section 2 CPU

 16 × 16-bit register-register multiply: 0.88 µs
 32 ÷ 16-bit register-register divide: 0.88 µs

• Two CPU operating modes
 Normal mode (not available in the H8/3052BF)
 Advanced mode

• Low-power mode

Transition to power-down state by SLEEP instruction

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H has the following enhancements.

• More general registers

Eight 16-bit registers have been added.

• Expanded address space
 Advanced mode supports a maximum 16-Mbyte address space.
 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

(Normal mode is not available in the H8/3052BF.)

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.

• Enhanced instructions
 Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
 Signed multiply/divide instructions and other instructions have been added.

Rev. 3.00 Mar 21, 2006 page 20 of 814
REJ09B0302-0300

Section 2 CPU

2.2 CPU Operating Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.

The H8/3052BF can be used only in advanced mode. (Information from this point on will apply to
advanced mode unless otherwise stated.)

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program
and data areas combined

Maximum 16 Mbytes, program
and data areas combined

Figure 2.1 CPU Operating Modes

Rev. 3.00 Mar 21, 2006 page 21 of 814

REJ09B0302-0300

Section 2 CPU

2.3 Address Space

The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3052BF has various
operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting
the full 16 Mbytes.

Figure 2.2 shows the address ranges of the H8/3052BF. For further details see section 3.6,
Memory Map in Each Operating Mode.

The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.

H'00000

H'FFFFF

H'000000

H'FFFFFF

a. 1-Mbyte modes b. 16-Mbyte modes

Figure 2.2 Memory Map

Rev. 3.00 Mar 21, 2006 page 22 of 814
REJ09B0302-0300

Section 2 CPU

2.4 Register Configuration

2.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.

General Registers (ERn)

0707015
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7

Control Registers (CR)

PC

E0
E1
E2
E3
E4
E5
E6
E7

23 0

(SP)

R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H

R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L

Legend:

Stack pointer

SP:

Program counter

PC:

Condition code register

CCR:

Interrupt mask bit

I:

User bit or interrupt mask bit

UI:

Half-carry flag

H:

User bit

U:

Negative flag

N:

Zero flag

Z:

Overflow flag

V:

Carry flag

C:

CCR

Figure 2.3 CPU Internal Registers

Rev. 3.00 Mar 21, 2006 page 23 of 814

7

6543210

IUIHUNZVC

REJ09B0302-0300

Section 2 CPU

2.4.2 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.

Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

ER0 to ER7

Figure 2.4 Usage of General Registers

Rev. 3.00 Mar 21, 2006 page 24 of 814
REJ09B0302-0300

E registers

(extended registers)

E0 to E7

RH registers

R0H to R7H

R registers

R0 to R7

RL registers

R0L to R7L

Section 2 CPU

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.

Free area

SP (ER7)

Stack area

Figure 2.5 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).

Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.

Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.

• Bit 7—Interrupt Mask Bit (I)

Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting.
The I bit is set to 1 at the start of an exception-handling sequence.

• Bit 6—User Bit or Interrupt Mask Bit (UI)

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions. This bit can also be used as an interrupt mask bit. For details see section 5,
Interrupt Controller.

• Bit 5—Half-Carry Flag (H)

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed,
this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the
ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a

Rev. 3.00 Mar 21, 2006 page 25 of 814

REJ09B0302-0300

Section 2 CPU

carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and
cleared to 0 otherwise.

• Bit 4—User Bit (U)

Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions.

• Bit 3—Negative Flag (N)

Indicates the most significant bit (sign bit) of data.

• Bit 2—Zero Flag (Z)

Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

• Bit 1—Overflow Flag (V)

Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.

• Bit 0—Carry Flag (C)

Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

 Add instructions, to indicate a carry
 Subtract instructions, to indicate a borrow
 Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.

2.4.4 Initial CPU Register Values

In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. The initial
value of the stack pointer (ER7) is undefined. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.

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Section 2 CPU

2.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.6 shows the data formats in general registers.

Data Type Data Format

1-bit data

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

Byte data

General
Register

RnH

RnL

RnH

RnL

RnH

RnL

70

6543210

7

Don’t care

43

70

Don’t care

70

MSB LSB

Don’t care

Figure 2.6 General Register Data Formats (1)

70
76543210

Lower digitUpper digit

7

70

MSB LSB

Don’t care

Don’t care

43

Lower digitUpper digit

Don’t care

0

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Section 2 CPU

Word data

Word data

Longword data

Legend:
ERn:

General register

En:

General register E

Rn:

General register R

RnH:

General register RH

RnL:

General register RL

MSB:

Most significant bit

LSB:

Least significant bit

General
RegisterData Type Data Format

Rn

15 0

En

MSB LSB

31 16

ERn

MSB

Figure 2.6 General Register Data Formats (2)

15 0

MSB LSB

15 0

LSB

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Section 2 CPU

2.5.2 Memory Data Formats

Figure 2.7 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.

AddressData Type Data Format

70

1-bit data

76543210Address L

Byte data

Word data

Longword data

Address L

Address 2M
Address 2M + 1

Address 2N
Address 2N + 1

MSB LSB

MSB

LSB

MSB

Address 2N + 2
Address 2N + 3

LSB

Figure 2.7 Memory Data Formats

When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.

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Section 2 CPU

2.6 Instruction Set

2.6.1 Instruction Set Overview

The H8/300H CPU has 62 types of instructions, which are classified in table 2.1.

Table 2.1 Instruction Classification

Function Instruction Types

1

Data transfer MOV, PUSH

*

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,

DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,
EXTU

Logic operations AND, OR, XOR, NOT 4

Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,

BXOR, BIXOR, BLD, BILD, BST, BIST

3

Branch Bcc

*

, JMP, BSR, JSR, RTS 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9

Block data transfer EEPMOV 1

Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.

PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.

2. Not available in the H8/3052BF.

3. Bcc is a generic branching instruction.

, POP

1

*

, MOVTPE

2

*

, MOVFPE

2

*

3

18

14

Total 62 types

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2.6.2 Instructions and Addressing Modes

Table 2.2 indicates the instructions available in the H8/300H CPU.

Table 2.2 Instructions and Addressing Modes

Addressing Modes

Function Instruction

#xx

Rn

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Data
transfer

operations

Logic
operations

Shift instructions —BWL———————————

Bit manipulation — B B — — — B — — — — — —

Branch Bcc, BSR ————————— ——

System
control

Block data transfer ————————————BW

Legend:
B: Byte
W: Word
L: Longword
Note: * Not available in the H8/3052BF.

MOV BWL BWL BWL BWL BWL BW L B BWL BWL — — — —

POP, PUSH ————————————WL

MOVFPE*,
MOVTPE

ADD, CMP BWLBWL———————————Arithmetic

SUB WLBWL———————————

ADDX, SUBX B B ———————————

ADDS, SUBS — L ———————————

INC, DEC —BWL———————————

DAA, DAS — B———————————

MULXU, MULXS,
DIVXU, DIVXS

NEG —BWL———————————

EXTU, EXTS —WL———————————

AND, OR, XORBWLBWL———————————

NOT —BWL———————————

JMP, JSR — — ————— —— —

RTS ————————————

TRAPA ————————————

RTE ————————————

SLEEP ————————————

LDC B BWWWW—WW————

STC —B WWWW—WW————

ANDC, ORC,
XORC

NOP ————————————

*

——————— B —————

—BW———————————

B ————————————

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Section 2 CPU

2.6.3 Tables of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.

Operation Notation

Rd General register (destination)

Rs General register (source)

Rn General register

ERn General register (32-bit register or address register)

(EAd) Destination operand

(EAs) Source operand

CCR Condition code register

N N (negative) flag of CCR

Z Z (zero) flag of CCR

V V (overflow) flag of CCR

C C (carry) flag of CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
¬ NOT (logical complement)

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).

*

*

*

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Table 2.3 Data Transfer Instructions

Section 2 CPU

Instruction Size

MOV B/W/L (EAs) → Rd, Rs → (EAd)

MOVFPE B (EAs) → Rd

MOVTPE B Rs → (EAs)

POP W/L @SP+ → Rn

PUSH W/L Rn → @–SP

Note: * Size refers to the operand size.

B: Byte
W: Word
L: Longword

*

Function

Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.

Cannot be used in the H8/3052BF.

Cannot be used in the H8/3052BF.

Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L
@SP+, ERn.

Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L
ERn, @–SP.

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Section 2 CPU

Table 2.4 Arithmetic Operation Instructions

Instruction Size

ADD, SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

ADDX, SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

INC, DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

ADDS, SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

DAA, DAS B Rd decimal adjust → Rd

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

*

Function

Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Immediate byte
data cannot be subtracted from data in a general register. Use the
SUBX or ADD instruction.)

Performs addition or subtraction with carry or borrow on data in two
general registers, or on immediate data and data in a general
register.

Increments or decrements a general register by 1 or 2. (Byte
operands can be incremented or decremented by 1 only.)

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.

Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

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Section 2 CPU

Instruction Size

DIVXU B/W Rd ÷ Rs → Rd

DIVXS B/W Rd ÷ Rs → Rd

CMP B/W/L Rd – Rs, Rd – #IMM

NEG B/W/L 0 – Rd → Rd

EXTS W/L Rd (sign extension) → Rd

EXTU W/L Rd (zero extension) → Rd

Note: * Size refers to the operand size.

B: Byte
W: Word
L: Longword

*

Function

Performs unsigned division on data in two general registers: either

16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16
bits → 16-bit quotient and 16-bit remainder.

Performs signed division on data in two general registers: either 16

bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.

Compares data in a general register with data in another general
register or with immediate data, and sets CCR according to the
result.

Takes the two’s complement (arithmetic complement) of data in a
general register.

Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by extending the sign bit.

Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by padding with zeros.

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Section 2 CPU

Table 2.5 Logic Operation Instructions

Instruction Size

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

NOT B/W/L ¬ Rd → Rd

Note: * Size refers to the operand size.

B: Byte
W: Word
L: Longword

*

Function

Performs a logical AND operation on a general register and another
general register or immediate data.

Performs a logical OR operation on a general register and another
general register or immediate data.

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

Takes the one’s complement of general register contents.

Table 2.6 Shift Instructions

Instruction Size

SHAL,
SHAR

SHLL,
SHLR

ROTL,
ROTR

ROTXL,
ROTXR

Note: * Size refers to the operand size.

B: Byte
W: Word
L: Longword

*

B/W/L Rd (shift) → Rd

B/W/L Rd (shift) → Rd

B/W/L Rd (rotate) → Rd

B/W/L Rd (rotate) → Rd

Function

Performs an arithmetic shift on general register contents.

Performs a logical shift on general register contents.

Rotates general register contents.

Rotates general register contents through the carry bit.

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Table 2.7 Bit Manipulation Instructions

Section 2 CPU

Instruction Size

BSET B 1 → (<bit-No.> of <EAd>)

BCLR B 0 → (<bit-No.> of <EAd>)

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

BTST B ¬ (<bit-No.> of <EAd>) → Z

BAND B C ∧ (<bit-No.> of <EAd>) → C

BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C

*

Function

Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.

Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.

Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower 3 bits of
a general register.

Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower 3 bits of a general register.

ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.

ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

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Section 2 CPU

Instruction Size

BOR B C ∨ (<bit-No.> of <EAd>) → C

BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C

BLD B (<bit-No.> of <EAd>) → C

BILD B ¬ (<bit-No.> of <EAd>) → C

BST B C → (<bit-No.> of <EAd>)

BIST B C → ¬ (<bit-No.> of <EAd>)

Note: * Size refers to the operand size.

B: Byte

*

Function

ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.

ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Exclusive-ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.

Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.

The bit number is specified by 3-bit immediate data.

Transfers a specified bit in a general register or memory operand to
the carry flag.

Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.

The bit number is specified by 3-bit immediate data.

Transfers the carry flag value to a specified bit in a general register
or memory operand.

Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.

The bit number is specified by 3-bit immediate data.

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Section 2 CPU

Table 2.8 Branching Instructions

Instruction Size Function

Bcc — Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1

Bcc (BHS) Carry clear (high or same) C = 0

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address

BSR — Branches to a subroutine at a specified address

JSR — Branches to a subroutine at a specified address

RTS — Returns from a subroutine

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Section 2 CPU

Table 2.9 System Control Instructions

Instruction Size

TRAPA — Starts trap-instruction exception handling

RTE — Returns from an exception-handling routine

SLEEP — Causes a transition to the power-down state

LDC B/W (EAs) → CCR

STC B/W CCR → (EAd)

ANDC B CCR ∧ #IMM → CCR

ORC B CCR ∨ #IMM → CCR

XORC B CCR ⊕ #IMM → CCR

NOP — PC + 2 → PC

Note: * Size refers to the operand size.

B: Byte
W: Word

*

Function

Moves the source operand contents to the condition code register.
The condition code register size is one byte, but in transfer from
memory, data is read by word access.

Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is
written by word access.

Logically ANDs the condition code register with immediate data.

Logically ORs the condition code register with immediate data.

Logically exclusive-ORs the condition code register with immediate
data.

Only increments the program counter.

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Table 2.10 Block Transfer Instruction

Instruction Size Function

EEPMOV.B — if R4L ≠ 0 then

repeat @ER5+ → @ER6+, R4L – 1 → R4L

until R4L = 0

else next;

EEPMOV.W — if R4 ≠ 0 then

repeat @ER5+ → @ER6+, R4 – 1 → R4

until R4 = 0

else next;

Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6.

R4L or R4: Size of block (bytes)
ER5: Starting source address
ER6: Starting destination address

Execution of the next instruction begins as soon as the transfer is
completed.

Section 2 CPU

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Section 2 CPU

2.6.4 Basic Instruction Formats

The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).

Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.

Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).

Condition Field: Specifies the branching condition of Bcc instructions.

Figure 2.8 shows examples of instruction formats.

Operation field only

op

Operation field and register fields

op rn rm

Operation field, register fields, and effective address extension

op rn rm

EA (disp)

Operation field, effective address extension, and condition field

op cc EA (disp)

Figure 2.8 Instruction Formats

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NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm

BRA d:8

Section 2 CPU

2.6.5 Notes on Use of Bit Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.

The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.

Step Description

1 Read Read data (byte unit) at the specified address

2 Bit manipulation Modify the specified bit in the read data

3 Write Write the modified data (byte unit) to the specified address

In the following example, a BCLR instruction is executed on the data direction register (DDR) of
port 4.

and P46 are set as input pins, and are inputting low-level and high-level signals, respectively.

P4

7

P4

to P40 are set as output pins, and are in the low-level output state.

5

In this example, the BCLR instruction is used to make P4

an input port.

0

Before Execution of BCLR Instruction

P4

7

Input/output Input Input Output Output Output Output Output Output

DDR 00111111

DR 10000000

P4

P4

6

5

P4

4

P4

P4

3

P4

2

P4

1

0

Execution of BCLR Instruction

BCLR #0, @P4DDR ; Execute BCLR instruction on DDR

After Execution of BCLR Instruction

P4

7

Input/output Output Output Output Output Output Output Output Input

DDR 1 1 111110

DR 10000000

P4

P4

6

5

P4

4

P4

P4

3

P4

2

P4

1

0

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Section 2 CPU

Explanation of BCLR Instruction

To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write­only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to DDR to complete the BCLR instruction.

As a result, P4
are set to 1, making P4

DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

0

and P46 output pins.

7

The BCLR instruction can be used to clear flags in the internal I/O registers to 0. In an interrupt­handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the
flag ahead of time.

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program­counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)

4 Register indirect with post-increment

Register indirect with pre-decrement

5 Absolute address @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8, PC)/@(d:16, PC)

8 Memory indirect @@aa:8

@ERn+

@–ERn

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Section 2 CPU

Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.

Register Indirect—@ERn: The register field of the instruction code specifies an address register
(ERn), the lower 24 bits of which contain the address of the operand.

Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.

Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.

• Register indirect with pre-decrement—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.

Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible
address ranges.

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Section 2 CPU

Table 2.12 Absolute Address Access Ranges

Absolute Address 1-Mbyte Modes 16-Mbyte Modes

8 bits (@aa:8) H'FFF00 to H'FFFFF

(1048320 to 1048575)

16 bits (@aa:16) H'00000 to H'07FFF,

H'F8000 to H'FFFFF
(0 to 32767, 1015808 to 1048575)

24 bits (@aa:24) H'00000 to H'FFFFF

(0 to 1048575)

H'FFFF00 to H'FFFFFF
(16776960 to 16777215)

H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32767, 16744448 to 16777215)

H'000000 to H'FFFFFF
(0 to 16777215)

Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.

Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign­extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.

Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.9. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.

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Section 2 CPU

Specified by @aa:8

Reserved

Branch address

Figure 2.9 Memory-Indirect Branch Address Specification

When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.

2.7.2 Effective Address Calculation

Table 2.13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.

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Section 2 CPU

Table 2.13 Effective Address Calculation

No.

Addressing Mode and
Instruction Format

Effective Address
Calculation

1 Register direct (Rn)

op rm rn

2 Register indirect (@ERn)

31 0

rop

3 Register indirect with displacement

@(d:16, ERn)/@(d:24, ERn)

31 0

op r

disp

Sign extension disp

4 Register indirect with post-increment

or pre-decrement

Register indirect with post-increment
@ERn+

31 0

General register contents

General register contents

General register contents

Effective Address

Operand is general
register contents

23

23 0

23

0

0

op

r

Register indirect with pre-decrement
@–ERn

op

r

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REJ09B0302-0300

1, 2, or 4

31 0

General register contents

1, 2, or 4

1 for a byte operand, 2 for a word
operand, 4 for a longword operand

23 0

Section 2 CPU

Addressing Mode and
Instruction Format

No.

5 Absolute address

@aa:8

op abs

@aa:16

op

@aa:24

op

abs

6 Immediate

#xx:8, #xx:16, or #xx:32

op

abs

IMM

Effective Address
Calculation

Effective Address

23

23

Sign

exten-

sion

23

H'FFFF

08 7

016 15

0

Operand is immediate
data

7 Program-counter relative

@(d:8, PC) or @(d:16, PC)

op disp

23

Sign

exten-

sion

PC contents

disp

0

23

0

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Section 2 CPU

Addressing Mode and

No.

Instruction Format

8 Memory indirect @@aa:8

· Normal mode

op

abs

· Advanced mode

op

abs

Effective Address
Calculation

23 8 7

H'0000

15

Memory contents

23 8 7

H'0000

31

Memory contents

abs

abs

Effective Address

0

0

0

0

0

0

23

23

16 15

H'00

0

0

Legend:
r, rm, rn: Register field
op: Operation field
disp: Displacement
IMM: Immediate data
abs: Absolute address

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Section 2 CPU

2.8 Processing States

2.8.1 Overview

The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2.10 classifies the processing
states. Figure 2.12 indicates the state transitions.

Processing states Program execution state

The CPU executes program instructions in sequence

Exception-handling state

A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception

Bus-released state

The external bus has been released in response to a bus request
signal from a bus master other than the CPU

Reset state

The CPU and all on-chip supporting modules are initialized and halted

Power-down state

The CPU is halted to conserve power

Sleep mode

Software standby mode

Hardware standby mode

Figure 2.10 Processing States

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Section 2 CPU

2.8.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.

Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.

Table 2.14 Exception Handling Types and Priority

Type of

Priority

High

↑






Low

Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or

Exception Detection Timing Start of Exception Handling

Reset Synchronized with clock Exception handling starts immediately

when RES changes from low to high

Interrupt End of instruction

execution or end of
exception handling

Trap instruction When TRAPA instruction

is executed

immediately after reset exception handling.

*

When an interrupt is requested,
exception handling starts at the end of
the current instruction or current
exception-handling sequence

Exception handling starts when a trap
(TRAPA) instruction is executed

Figure 2.11 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.

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Exception
sources

Section 2 CPU

Reset

External interrupts

Interrupt

Internal interrupts (from on-chip supporting modules)

Trap instruction

Figure 2.11 Classification of Exception Sources

End of bus release

Bus request

End of bus
release

Bus-released state

End of
exception
handling

Exception-handling state

RES = High

Reset state

Notes: 1.2.From any state except hardware standby mode, a transition to the reset state occurs

whenever goes low.
From any state, a transition to hardware standby mode occurs when goes low.

*1

RES

Program execution state

Bus
request

Exception

Interrupt

NMI, IRQ , IRQ ,
or IRQ interrupt

STBY = High, = Low

01

2

RES

SLEEP
instruction
with SSBY = 0

Sleep mode

SLEEP instruction
with SSBY = 1

Software standby mode

Hardware standby mode

Power-down state

STBY

*2

Figure 2.12 State Transitions

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Section 2 CPU

2.8.4 Exception-Handling Sequences

Reset Exception Handling: Reset exception handling has the highest priority. The reset state is

entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.

Figure 2.13 shows the stack after the exception-handling sequence.

SP–4
SP–3
SP–2
SP–1

SP (ER7)

Legend:
CCR:

Condition code register

SP:

Stack pointer

Notes: 1.2.PC is the address of the first instruction executed after the return from the

exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.

Stack area

Before exception
handling starts

SP (ER7)

SP+1
SP+2
SP+3
SP+4

Pushed on stack

After exception
handling ends

Figure 2.13 Stack Structure after Exception Handling

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CCR

PC

Even
address

Section 2 CPU

2.8.5 Bus-Released State

In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU are the DMA controller, the refresh controller, and an external
bus master. While the bus is released, the CPU halts except for internal operations. Interrupt
requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation.

2.8.6 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details see section 12,
Watchdog Timer.

2.8.7 Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.

Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.

For further information see section 20, Power-Down State.

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Section 2 CPU

2.9 Basic Operational Timing

2.9.1 Overview

The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the

system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.

2.9.2 On-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.14 shows the on-chip memory access cycle. Figure 2.15 indicates the pin
states.

Bus cycle

φ

Internal address bus

Internal read signal
Internal data bus

(read access)

Internal write signal
Internal data bus

(write access)

Figure 2.14 On-Chip Memory Access Cycle

T state

1

Address

Read data

Write data

T state

2

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Section 2 CPU

T

1

T

2

φ

Address bus

RD HWR LWR

, , ,AS

High

Address

High impedance

D to D

15 0

Figure 2.15 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.16 shows the on-chip supporting module access
timing. Figure 2.17 indicates the pin states.

Bus cycle

Read
access

Write
access

φ

Address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

T state

1

T state

2

Address

Read data

Write data

Figure 2.16 Access Cycle for On-Chip Supporting Modules

Rev. 3.00 Mar 21, 2006 page 57 of 814

T state

3

REJ09B0302-0300

Section 2 CPU

T

3

φ

Address bus

RD HWR LWR

, , ,AS

D to D

15 0

High

T

1

T

2

Address

High impedance

Figure 2.17 Pin States during Access to On-Chip Supporting Modules

2.9.4 Access to External Address Space

The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.

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Section 3 MCU Operating Modes

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection

The H8/3052BF has seven operating modes (modes 1 to 7) that are selected by the mode pins
(MD

to MD0) as indicated in table 3.1. The input at these pins determines the size of the address

2

space and the initial bus mode.

Table 3.1 Operating Mode Selection

Mode Pins Description

Operating

3

*

Mode

MD2MD1MD

Address Space

0

Initial Bus

*

Mode

—000— ———

Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled

Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled

Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled

Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled

Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled

Mode 6 1 1 0 Expanded mode 8 bits Enabled Enabled

Mode 7 1 1 1 Single-chip advanced

— Enabled Enabled

mode

Notes: 1. In modes 1 to 6, an 8-bit or 16-bit data bus can be selected on a per-area basis by

settings made in the area bus width control register (ABWCR). For details see section
6, Bus Controller.

2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.

3. These are the operating modes when the FWE pin is at 0. For the operating modes
when the FWE pin is at 1, see section 18, ROM.

1

On-Chip
ROM

On-Chip
RAM

2

*

2

*

2

*

2

*

2

*

2

*

For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is
either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, the
external data bus is 8 bits wide. For details see section 6, Bus Controller.

Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space
of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.

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Section 3 MCU Operating Modes

Modes 5 and 6 are externally expanded modes that enable access to external memory and
peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum
address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes.

Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and Internal I/O
registers, and makes all I/O ports available. Mode 7 supports a 1-Mbyte address space.

The H8/3052BF can be used only in modes 1 to 7. The inputs at the mode pins must select one of
these seven modes. The inputs at the mode pins must not be changed during operation.

3.1.2 Register Configuration

The H8/3052BF has a mode control register (MDCR) that indicates the inputs at the mode pins
(MD

to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.

2

Table 3.2 Registers

Address

H'FFF1 Mode control register MDCR R Undetermined

H'FFF2 System control register SYSCR R/W H'0B

Note: * The lower 16 bits of the address are indicated.

*

Name Abbreviation R/W Initial Value

3.2 Mode Control Register (MDCR)

MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3052BF.

Bit

Initial value
Read/Write

Note: Determined by pins MD to MD .*

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

7

—

1

—

Reserved bits Mode select 2 to 0

6

—

1

—

20

5

—

0

—

4

—

0

—

Reserved bits

—

—

3

0

2

MDS2

*

—

R

Bits indicating the current
operating mode

1

MDS1

— R**

0

MDS0

—

R

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

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Section 3 MCU Operating Modes

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD

to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to

2

MDS0 are read-only bits. The mode pin (MD

to MD0) levels are latched into these bits when

2

MDCR is read.

3.3 System Control Register (SYSCR)

SYSCR is an 8-bit register that controls the operation of the H8/3052BF.

Bit

Initial value
Read/Write

7

SSBY

0

R/W

Software standby

Enables transition to software standby mode

6

STS2

0

R/W

Standby timer select 2 to 0

These bits select the waiting time at
recovery from software standby mode

5

STS1

0

R/W

4

STS0

0

R/W

UE

R/W

User bit enable

Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit

3

1

2

NMIEG

0

R/W

Reserved bit

NMI edge select

Selects the valid edge
of the NMI input

1

—

1

—

RAM enable

Enables or
disables
on-chip RAM

0

RAME

1

R/W

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 20, Power-Down State.)

When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.

Bit 7: SSBY Description

0 SLEEP instruction causes transition to sleep mode (Initial value)

1 SLEEP instruction causes transition to software standby mode

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Section 3 MCU Operating Modes

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so
that the waiting time will be at least 7 ms at the system clock rate. For further information about
waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software
Standby Mode.

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description

000Waiting time = 8,192 states (Initial value)

1 Waiting time = 16,384 states

1 0 Waiting time = 32,768 states

1 Waiting time = 65,536 states

100Waiting time = 131,072 states

1 Waiting time = 1,024 states

1 — Illegal setting

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.

Bit 3: UE Description

0 UI bit in CCR is used as an interrupt mask bit

1 UI bit in CCR is used as a user bit (Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.

Bit 2: NMIEG Description

0 An interrupt is requested at the falling edge of NMI (Initial value)

1 An interrupt is requested at the rising edge of NMI

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized by the rising edge of the RES signal. It is not initialized in software standby mode.

Bit 0: RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

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3.4 Operating Mode Descriptions

3.4.1 Mode 1

Section 3 MCU Operating Modes

Ports 1, 2, and 5 function as address pins A

to A0, permitting access to a maximum 1-Mbyte

19

address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.2 Mode 2

Ports 1, 2, and 5 function as address pins A

to A0, permitting access to a maximum 1-Mbyte

19

address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.

3.4.3 Mode 3

Ports 1, 2, and 5 and part of port A function as address pins A

to A0, permitting access to a

23

maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A
(BRCR). (In this mode A

to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register

23

is always used for address output.)

20

3.4.4 Mode 4

Ports 1, 2, and 5 and part of port A function as address pins A

to A0, permitting access to a

23

maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A

to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always

23

used for address output.)

3.4.5 Mode 5

Ports 1, 2, and 5 can function as address pins A

to A0, permitting access to a maximum 1-Mbyte

19

address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

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Section 3 MCU Operating Modes

3.4.6 Mode 6

Ports 1, 2, and 5 and part of port A function as address pins A

to A0, permitting access to a

23

maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A
A

is always used for address output.)

20

to A21 output, clear bits 7 to 5 of BRCR to 0. (In this mode

23

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.7 Mode 7

This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 7 supports a 1-Mbyte address space.

3.5 Pin Functions in Each Operating Mode

The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3
indicates their functions in each operating mode.

Table 3.3 Pin Functions in Each Mode

Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

2

8

*

0

2

*

0

1

*

0

2

*

0

P17 to P1

P27 to P2

D15 to D

P47 to P4

P53 to P5

A

20

Port 1 A

Port 2 A15 to A

Port 3 D15 to D

Port 4 P47 to P4

Port 5 A19 to A

to A

7

A7 to A

0

A15 to A

8

D15 to D

8

1

*

D7 to D

0

A19 to A

16

A7 to A

0

8

8

1

*

0

16

0

A15 to A

D15 to D

P47 to P4

A19 to A

Port A PA7 to PA4PA7 to PA4PA7 to PA

A

20

8

8

16

1

*

0

3

*

5

A7 to A

A15 to A

D15 to D

D7 to D

A19 to A

,

PA7 to PA
A

20

P17 to P1

0

P27 to P2

8

D15 to D

8

1

*

P47 to P4

0

P53 to P5

16

3

*

,

PA7 to PA4PA7 to PA5,

5

Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function

to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.

as P4

7

2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.

3. Initial state. A

output by writing 0 in bits 7 to 5 of BRCR.

A

21

is always an address output pin. PA7 to PA5 are switched over to A23 to

20

2

*

P17 to P1

0

2

*

P27 to P2

0

P37 to P3

8

1

*

P47 to P4

0

2

*

P53 to P5

0

3

*

PA7 to PA

0

0

0

0

0

4

Rev. 3.00 Mar 21, 2006 page 64 of 814
REJ09B0302-0300

Section 3 MCU Operating Modes

3.6 Memory Map in Each Operating Mode

Figure 3.1 shows a memory map of the H8/3052BF. The address space is divided into eight areas.

The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.

The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte
modes (modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range
specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also
differs.

Rev. 3.00 Mar 21, 2006 page 65 of 814

REJ09B0302-0300

Section 3 MCU Operating Modes

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'00000

H'000FF

H'07FFF

H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000

H'F8000
H'FDF0F

H'FDF10

H'FFF00
H'FFF0F
H'FFF10

H'FFF1B
H'FFF1C

H'FFFFF

Vector area

External address

space

On-chip RAM *

External

address

space

Internal I/O

registers

Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7

(16-Mbyte expanded modes with

H'000000

H'0000FF

16-bit absolute

addresses

Memory-indirect

branch addresses

8-bit absolute addresses

H'007FFF

H'1FFFFF
H'200000

H'3FFFFF
H'400000

H'5FFFFF
H'600000

H'7FFFFF
H'800000

H'9FFFFF
H'A00000

H'BFFFFF
H'C00000

H'DFFFFF
H'E00000

16-bit absolute addresses

H'FF8000
H'FFDF0F

H'FFDF10

H'FFFF00
H'FFFF0F
H'FFFF10

H'FFFF1B
H'FFFF1C

H'FFFFFF

Modes 3 and 4

on-chip ROM disabled)

Vector area

Area 0

Area 1

Area 2

External

address

space

On-chip RAM *

External

address

space

Internal I/O

registers

Area 3

Area 4

Area 5

Area 6

Area 7

16-bit absolute

addresses

Memory-indirect

branch addresses

16-bit absolute addresses

8-bit absolute addresses

Note: External addresses can be accessed by disabling on-chip RAM.*

Figure 3.1 H8/3052BF Memory Map in Each Operating Mode

Rev. 3.00 Mar 21, 2006 page 66 of 814
REJ09B0302-0300

Section 3 MCU Operating Modes

(1-Mbyte expanded mode with

H'00000

H'000FF

H'07FFF

H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000

H'F8000
H'FDF0F

H'FDF10

H'FFF00
H'FFF0F
H'FFF10

H'FFF1B
H'FFF1C

H'FFFFF

Mode 5

on-chip ROM enabled)

Vector area

On-chip ROM

External address

space

On-chip RAM *

External
address

space

Internal I/O

registers

H'000000

H'0000FF

16-bit absolute

addresses

Memory-indirect

branch addresses

Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7

8-bit absolute addresses

H'007FFF

H'07FFFF
H'080000
H'1FFFFF
H'200000

H'3FFFFF
H'400000

H'5FFFFF
H'600000

H'7FFFFF
H'800000

H'9FFFFF
H'A00000

H'BFFFFF
H'C00000

H'DFFFFF
H'E00000

16-bit absolute addresses

H'FF8000

H'FFDF0F
H'FFDF10

H'FFFF00
H'FFFF0F
H'FFFF10

H'FFFF1B
H'FFFF1C

H'FFFFFF

(16-Mbyte expanded mode with

Mode 6

on-chip ROM enabled)

Vector area

On-chip ROM

Area 0

Area 1

Area 2

External
address

space

On-chip RAM *

External
address

space

Internal I/O

registers

Area 3

Area 4

Area 5

Area 6

Area 7

Memory-indirect

branch addresses

8-bit absolute addresses

(single-chip advanced mode)

H'00000

H'000FF

16-bit absolute

addresses

H'07FFF

H'7FFFF

H'F8000

H'FDF10

H'FFF00

H'FFF0F

H'FFF1C

H'FFFFF

16-bit absolute addresses

Mode 7

Vector area

On-chip ROM

On-chip RAM

Internal I/O

registers

16-bit absolute

addresses

Memory-indirect

branch addresses

16-bit absolute addresses

8-bit absolute addresses

Note: External addresses can be accessed by disabling on-chip RAM.*

Figure 3.1 H8/3052BF Memory Map in Each Operating Mode (cont)

Rev. 3.00 Mar 21, 2006 page 67 of 814

REJ09B0302-0300

Section 3 MCU Operating Modes

Rev. 3.00 Mar 21, 2006 page 68 of 814
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Section 4 Exception Handling

Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High

↑




Low

Reset Starts immediately after a low-to-high transition at the

RES pin

Interrupt Interrupt requests are handled when execution of the

current instruction or handling of the current exception is
completed

Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.

1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.

2. The CCR interrupt mask bit is set to 1.

3. A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in that address.

For a reset exception, steps 2 and 3 above are carried out.

Rev. 3.00 Mar 21, 2006 page 69 of 814

REJ09B0302-0300

Section 4 Exception Handling

4.1.3 Exception Sources and Vector Table

The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.

• Reset

Exception
sources

External interrupts:

• Interrupts
Internal interrupts:

• Trap instruction

NMI, IRQ to IRQ

30 interrupts from on-chip
supporting modules

0 5

Figure 4.1 Exception Sources

Rev. 3.00 Mar 21, 2006 page 70 of 814
REJ09B0302-0300

Section 4 Exception Handling

Table 4.2 Exception Vector Table

Exception Source Vector Number Vector Address

Reset 0 H'0000 to H'0003

Reserved for system use 1 H'0004 to H'0007

2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

5 H'0014 to H'0017

6 H'0018 to H'001B

External interrupt (NMI) 7 H'001C to H'001F

Trap instruction (4 sources) 8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

11 H'002C to H'002F

External interrupt IRQ

External interrupt IRQ

External interrupt IRQ

External interrupt IRQ

External interrupt IRQ

External interrupt IRQ

0

1

2

3

4

5

Reserved for system use 18 H'0048 to H'004B

2

Internal interrupts

*

Notes: 1. Lower 16 bits of the address.

2. For the internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector Table.

12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

15 H'003C to H'003F

16 H'0040 to H'0043

17 H'0044 to H'0047

19 H'004C to H'004F

20
to
60

H'0050 to H'0053
to
H'00F0 to H'00F3

1

*

Rev. 3.00 Mar 21, 2006 page 71 of 814

REJ09B0302-0300

Section 4 Exception Handling

4.2 Reset

4.2.1 Overview

A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from low
to high.

The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.

4.2.2 Reset Sequence

The chip enters the reset state when the RES pin goes low.

To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 20 system clock (φ) cycles. See appendix
D.2, Pin States at Reset, for the states of the pins in the reset state.

When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.

• The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit is set to 1 in CCR.

• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution

starts from the address indicated in the vector address.

Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in
modes 2 and 4. Figure 4.4 shows the reset sequence in modes 5 to 7.

Rev. 3.00 Mar 21, 2006 page 72 of 814
REJ09B0302-0300