Renesas FG4-768K Series User Manual

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Page 1

User Manual

Preliminary Document

V850E2/Fx4

32-bit Microcontroller

V850E2/FG4 V850E2/FJ4 V850E2/FK4 V850E2/FL4

µPD70F3548 µPD70F3549 µPD70F3550

µPD70F4000 µPD70F4001 µPD70F4002

µPD70F3551 µPD70F3552 µPD70F3553 µPD70F3554

µPD70F4003 µPD70F4004 µPD70F4005 µPD70F4006

µPD70F3555 µPD70F3556 µPD70F3557 µPD70F3558

µPD70F4007 µPD70F4008 µPD70F4009 µPD70F4010

µPD70F3559 µPD70F3560

µPD70F4011 µPD70F4012

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

R01UH0076ED0103, Rev. 1.03

www.renesas.com

November 07, 2012

Page 2

Under development: Preliminary document. Specifications in this document are tentative and subject to change.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

R01UH0076ED0103 Rev. 1.03 2 Nov 07, 2012

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.

Notice

The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and

measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control

systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control

systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics

Corporation and also includes its majority-owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or

for Renesas Electronics.

R01UH0076ED0103 Rev. 1.03 3 Nov 07, 2012

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual. – The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at power-on The state of the product is undefined at the moment when power is supplied. – The states of internal circuits in the LSI are indeterminate and the states of register settings and

pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins

are not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. – The reserved addresses are provided for the possible future expansion of functions. Do not

access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock signals After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.

– When the clock signal is generated with an external resonator (or from an external oscillator)

during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between products Before changing from one product to another, i.e. to one with a different part number, confirm that

the change will not lead to problems. – The characteristics of MPU/MCU in the same group but having different part numbers may differ

because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

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Under development: Preliminary document. Specifications in this document are tentative and subject to change.

Notice

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General Precautions in the Handling of MPU/MCU Products Table of Contents How to use this manual

Purpose and target readers

Special notations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Additional documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Content of this manual Notation of numbers and symbols Diagrams Trademarks Functional modules descriptions

Further information

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Functional modules abbreviation convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Product specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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Chapter 1 Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.1 V850E2/Fx4 Product Line Overview

1.1.1 V850E2/Fx4 products features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.2 Related Documents

1.3 Ordering Information

1.4 Product Name Register

Chapter 2 Port Functions

2.1 V850E2/Fx4 Port Features

2.2 Overview

2.2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.2.2 Pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.2.3 Pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.2.4 Port control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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2.3 Port Group Configuration Registers

2.3.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.2 Port control registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.3 Port function configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.4 Data input/output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.3.5 Configuration of electrical characteristics registers. . . . . . . . . . . . . . . . . . . . 78

2.4 V850E2/Fx4 Port Group Configuration

2.4.1 Port register protection clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

2.4.2 Common port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2.4.3 V850E2/FG4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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Table of Contents

2.4.4 V850E2/FJ4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.4.5 V850E2/FK4 port functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2.4.6 V850E2/FL4 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

2.4.7 Non-port input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

2.4.8 Alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

2.4.9 Port and pin functions in stand-by modes . . . . . . . . . . . . . . . . . . . . . . . . . . 140

2.4.10 Port and pin functions during and after reset . . . . . . . . . . . . . . . . . . . . . . . 140

2.4.11 Recommended connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . 141

2.5 Port Filters

2.5.1 Port filters assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

2.5.2 Port filters clock supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

2.5.3 Port filters reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

2.6 Port Filters Functional Description

2.6.1 Analog filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

2.6.2 Digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

2.6.3 Filter control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Chapter 3 CPU System Functions

3.1 Overview

3.2 Peripheral Protection Unit

3.3 Timing Supervision Unit

3.4 Memory Protection Unit (MPU)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

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3.5 CPU Access Bus Structures and Latencies

3.5.1 CPU Subsystem modules access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

3.5.2 PBUS modules access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

3.5.3 PBUS Synchronizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

3.5.4 Module wait clocks insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

3.6 CPU Subsystem

3.6.1 Power and clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.6.2 CPU Subsystem busses overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

3.6.3 V850E2/FG4 and V850E2/FJ4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 176

3.6.4 V850E2/FK4 and V850E2/FL4 CPU Subsystem . . . . . . . . . . . . . . . . . . . . 179

3.6.5 V850E2 system manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.7 Data flash wait cycle control

3.8 Operation modes

3.8.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

3.8.2 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

3.8.3 Boundary Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

3.9 Mode pins and JP0 connections

3.9.1 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

3.9.2 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

3.9.3 Flash programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

3.9.4 Boundary scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

3.10 Address Space

3.10.1 CPU data address and physical program address space . . . . . . . . . . . . . . 192

3.10.2 Program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

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3.11 V850E2/Fx4 CPU Address Map

3.11.1 DMA address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

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3.11.2 V850E2/Fx4 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

3.11.3 Memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

3.12 Back-up RAM (BURAM)

3.12.1 Back-up RAM protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

3.13 Write protected Registers

3.13.1 Register protection clusters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

3.13.2 Register protection unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

3.13.3 Register protection and interrupt/emulation break . . . . . . . . . . . . . . . . . . . 211

3.13.4 V850E2/Fx4 write protected registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

3.13.5 V850E2/Fx4 Protection registers overview . . . . . . . . . . . . . . . . . . . . . . . . . 214

3.13.6 Control protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . 216

3.13.7 Clock monitors protection cluster registers details . . . . . . . . . . . . . . . . . . . 218

3.13.8 Port protection clusters registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

3.13.9 Self-programming protection cluster registers details. . . . . . . . . . . . . . . . . 220

3.13.10 OCD control protection cluster registers details . . . . . . . . . . . . . . . . . . . . . 221

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Chapter 4 External Memory Controller (MEMC)

4.1 V850E2/Fx4 MEMC Features

4.2 Overview

4.2.1 Operation mode, connectable memory types . . . . . . . . . . . . . . . . . . . . . . . 223

4.2.2 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

4.2.3 Operation setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

4.2.4 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

4.2.5 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

4.2.6 Programmable wait setting functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

4.2.7 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

4.3 Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

4.4 Bus cycle type setting function

4.4.1 Multiplexed bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

4.5 Bus control function

4.5.1 Chip select output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

4.5.2 Operation enable/operation disable setting function . . . . . . . . . . . . . . . . . . 239

4.5.3 Bus size setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

4.5.4 Data endian setting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

4.6 Wait Functions

4.6.1 Programmable data wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

4.6.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

4.6.3 Data setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

4.6.4 Data hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

4.6.5 Address setup wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

4.6.6 Address hold wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

4.6.7 Idle insertion function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

4.7 Memory Connection Examples

4.7.1 Multiplexed bus mode connection example. . . . . . . . . . . . . . . . . . . . . . . . . 249

4.8 Data Flow

4.8.1 Data flow during byte access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

. . . . . . . . . . . . . . . 222

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Chapter 5 Interrupt Functions

5.1 Exceptions and Interrupts

5.1.1 Exception handler switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

5.2 V850E2/Fx4 Exceptions

5.2.1 Memory error exceptions MEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

5.2.2 System error exceptions SYSERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

5.2.3 Code flash error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

5.3 V850E2/Fx4 Interrupt Requests

5.3.1 V850E2/Fx4 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

5.3.2 V850E2/Fx4 FE level non-maskable interrupt sharing . . . . . . . . . . . . . . . . 301

5.3.3 V850E2/Fx4 TAPA EI level maskable interrupt sharing. . . . . . . . . . . . . . . . 303

5.3.4 V850E2/Fx4 DMA interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

5.4 External Interrupts

5.4.1 Edge Detection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

5.4.2 External interrupts as trigger and wake-up signals. . . . . . . . . . . . . . . . . . . 306

5.5 Interrupt Controller Control Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

. . . . . . . . . . . . . . . . . . . . . . . . . . . 307

5.6 Interrupt Acknowledgment and Restoring

5. 6. 1 FE level non-maskable interrupt FENMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

5. 6. 2 FE level maskable interrupt FEINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

5. 6. 3 EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

5.7 Interrupt Operation

5. 7. 1 Mask function of EI level maskable interrupt INTn . . . . . . . . . . . . . . . . . . . 324

5. 7. 2 Interrupt priority level judgment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

5. 7. 3 Priority mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

5. 7. 4 Pending interrupt report function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

5. 7. 5 In-service priority clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

5.8 Exception Handler Address Switching Function

. . . . . . . . . . . . . . . . . . . . . . . 317

. . . . . . . . . . . . . . . . . 331

Chapter 6 DMA Controller (DMAC)

6.1 V850E2/Fx4 DMA Features

6.2 Definition of Terms

6.3 General

6.3.1 DMA controller (DMAC) function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

6.3.2 DMA trigger factor register (DTFR) function . . . . . . . . . . . . . . . . . . . . . . . . 335

6.3.3 DMA access memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

6.3.4 Prioritization of channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

6.3.5 Stand-by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

6.4 DMAC Function

6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

6.4.2 DMAC setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

6.4.3 Enabling or disabling writing control registers. . . . . . . . . . . . . . . . . . . . . . . 344

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

6.5 DMA Control Registers

6.5.1 DTRC0 – DMA transfer request control register . . . . . . . . . . . . . . . . . . . . . 345

6.5.2 DTRSn – DMA transfer request select register. . . . . . . . . . . . . . . . . . . . . . 346

6.5.3 DSAnL – DMA source address register L. . . . . . . . . . . . . . . . . . . . . . . . . . 347

6.5.4 DSAnH – DMA source address register H . . . . . . . . . . . . . . . . . . . . . . . . . 349

6.5.5 DSCn – DMA source chip select register . . . . . . . . . . . . . . . . . . . . . . . . . . 350

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

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6.5.6 DNSAnL – DMA next source address register L. . . . . . . . . . . . . . . . . . . . . 351

6.5.7 DNSAnH – DMA next source address register H . . . . . . . . . . . . . . . . . . . . 352

6.5.8 DNSCn – DMA next source chip select register . . . . . . . . . . . . . . . . . . . . . 353

6.5.9 DDAnL – DMA destination address register L. . . . . . . . . . . . . . . . . . . . . . . 354

6.5.10 DDAnH – DMA destination address register H . . . . . . . . . . . . . . . . . . . . . . 356

6.5.11 DDCn – DMA destination chip select register. . . . . . . . . . . . . . . . . . . . . . . 357

6.5.12 DNDAnL – DMA next destination address register L . . . . . . . . . . . . . . . . . 358

6.5.13 DNDAnH –DMA next destination address register H . . . . . . . . . . . . . . . . . 359

6.5.14 DNDCn –DMA next destination chip select register . . . . . . . . . . . . . . . . . . 360

6.5.15 DTCn – DMA transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

6.5.16 DNTCn – DMA next transfer count register. . . . . . . . . . . . . . . . . . . . . . . . . 362

6.5.17 DTCCn – DMA transfer count compare register . . . . . . . . . . . . . . . . . . . . . 363

6.5.18 DTCTn – DMA transfer control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

6.5.19 DTSn – DMA transfer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

6.6 DMAC Function Details

6.6.1 DMAC transfer setting flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

6.6.2 DMAC transfer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

6.6.3 DMAC channel priority control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

6.6.4 Valid DMA transfer request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

6.6.5 Next address function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

6.6.6 Aborting/resuming DMA transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

6.6.7 Error response support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

6.6.8 Stand-by support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

6.7 DTFR Function

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

6.8 DTFR Control Registers

6.8.1 DTFRn – DMA trigger factor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

6.8.2 DRQCLR – DMA request clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

6.8.3 DRQSTR – DMA request check register. . . . . . . . . . . . . . . . . . . . . . . . . . . 381

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Chapter 7 Flash Memory

7.1 Code Flash Memory Overview

7.1.1 Code flash memory features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

7.1.2 Code flash memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

7.1.3 Data flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

7.2 Code Flash Memory functional Outline

7.2.1 Code flash memory erasure and rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . 390

7.3 Data Flash Memory

7.3.1 Data flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

7.3.2 Data flash reading and writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

7.4 Flash Programming with Flash Programmer

7.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

7.4.2 Communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

7.4.3 Pin connection with flash programmer PG-FP5 . . . . . . . . . . . . . . . . . . . . . 394

7.4.4 Flash memory programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

7.5 Code Flash Self-Programming

7.5.1 Self-Programming enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

7.5.2 Self-Programming library functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

7.5.3 Self-Programming internal RAM occupancy. . . . . . . . . . . . . . . . . . . . . . . . 404

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

. . . . . . . . . . . . . . . . . . . . . . . . . . 387

. . . . . . . . . . . . . . . . . . . . . 392

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7.5.4 Secure Self-Programming (boot cluster swapping). . . . . . . . . . . . . . . . . . . 405

7.5.5 Interrupt handling during flash Self-Programming. . . . . . . . . . . . . . . . . . . . 409

7.6 Flash Mask Options

7.6.1 OPBT0 - Flash mask option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Chapter 8 Data CRC Function A (DCRA)

8.1 V850E2/Fx4 DCRA Features

8.2 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

8.3 Functional Description

8.4 Registers

8.4.1 DCRA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

8.4.2 DCRA registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Chapter 9 Clock Controller

9.1 Clock Controller Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

. . . . . . . . . . . . . . . . . . . . . . . 412

9.2 General Description of Clock Generation and Control

9.2.1 Clock generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

9.2.2 Clock selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

9.3 Clock Generators

9.3.1 Main Oscillator (MainOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . 431

9.3.2 Sub Oscillator (SubOsc) clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . 434

9.3.3 Low Speed Internal Oscillator (Low Speed IntOsc) clock generator. . . . . . 436

9.3.4 High Speed Internal Oscillator (High Speed IntOsc) clock generator . . . . . 437

9.3.5 Phase-Locked Loop (PLL) clock generators . . . . . . . . . . . . . . . . . . . . . . . . 440

9.4 Clock Selection

9.4.1 Clock domains of Always–On–Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

9.4.2 Clock domains of Isolated–Area-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

9.4.3 Clock domains of Isolated–Area-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

9.5 Clock Domain Figures

9.6 Frequency Output Function (FOUT)

9.6.1 FOUT Clock Divider (FOUTDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

9.7 Clock Monitor A (CLMA)

9.7.1 V850E2/Fx4 CLMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

9.7.2 CLMA enable and start-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

9.7.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

9.7.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

9.7.5 Clock Monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

9.8 Clock Controller Registers

9.8.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.8.2 Clock Controller registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

9.8.3 Clock generators registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

9.8.4 Clock selector control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

. . . . . . . . . . . 424

Chapter 10 Stand-by Controller (STBC)

10.1 V850E2/Fx4 Stand-by Controller Features

10.2 Stand-by Controller functions

10.2.1 Stand-by Controller signal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

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. . . . . . . . . . . . . . . . . . . . . . . . . . 515

. . . . . . . . . . . . . . . . . . . . . . . 515

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10.2.2 Stand-by modes control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

10.2.3 Stand-by modes overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

10.2.4 Clock generators in stand-by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

10.2.5 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

10.2.6 I/O buffer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

10.2.7 Mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

10.3 Stand-by mode entry and exit example flows

10.3.1 STOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

10.3.2 RUN mode (Isolated-Area-1 STOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

10.3.3 DEEPSTOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

10.3.4 RUN mode (Isolated-Area-1 DEEPSTOP) . . . . . . . . . . . . . . . . . . . . . . . . . 547

10.3.5 Precaution: Clock generators and early wake-up . . . . . . . . . . . . . . . . . . . . 551

10.3.6 Application hint: Handling of wake-up events during stand-by mode preparation 553

10.4 Stand-by Controller Registers

10.4.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

10.4.2 Stand-by Controller registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

10.4.3 Stand-by Controller control registers details . . . . . . . . . . . . . . . . . . . . . . . . 558

10.4.4 Wake-up factor controller registers details . . . . . . . . . . . . . . . . . . . . . . . . . 564

10.4.5 Oscillator wake-up mask registers details. . . . . . . . . . . . . . . . . . . . . . . . . . 567

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

. . . . . . . . . . . . . . . . . . . . 535

Chapter 11 Code Protection and Security

11.1 Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

. . . . . . . . . . . . . . . . . . . . . . . 568

11.2 Flash Programmer and Self-Programming Protection

11.3 On-Chip Debug Interface Protection

11.3.1 On-Chip Debug enable flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

11.3.2 On-Chip Debug ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

11.3.3 On-Chip Debug protection levels summary. . . . . . . . . . . . . . . . . . . . . . . . . 571

11.3.4 On-Chip Debug control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Chapter 12 Reset Controller

12.1 Functional Overview

12.2 Functional Description

12.2.1 Reset flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

12.2.2 Power-On Clear reset (POCRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

12.2.3 Low-Voltage Indicator (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

12.2.4 Very-Low-Voltage Indicator (VLVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

12.2.5 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

12.2.6 Watchdog Timers reset (WDTAnRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

12.2.7 Software reset (SWRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

12.2.8 Clock Monitors reset (CLMAnRES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

12.2.9 Debugger reset (DBRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

12.3 Registers

12.3.1 Writing to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

12.3.2 Reset Controller registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

12.3.3 Reset Controller general control registers details. . . . . . . . . . . . . . . . . . . . 589

12.3.4 Software reset control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

12.3.5 Low-Voltage Indicator reset control registers . . . . . . . . . . . . . . . . . . . . . . . 592

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

. . . . . . . . . . . . 569

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12.3.6 Very-Low-Voltage flag control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Chapter 13 OS Timer (OSTM)

13.1 V850E2/Fx4 OSTM Features

13.2 Functional Overview

13.3 Functional Description

13.3.1 Count clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

13.3.2 Interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

13.3.3 Starting and stopping the timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

13.3.4 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

13.3.5 Free-run compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

13.4 OS Timer Registers

13.4.1 OS Timer registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

13.4.2 OS Timer registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Chapter 14 Window Watchdog Timer A (WDTA)

14.1 V850E2/Fx4 WDTA Features

14.2 WDTA Start-up Options

14.2.1 V850E2/Fx4 WDTAn start modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

14.3 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

14.4 Functional Description

14.4.1 WDTA after reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

14.4.2 WDTA trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

14.4.3 Error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

14.4.4 75% interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

14.4.5 Window function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

14.5 Application hint: Evaluation of the Watchdog status

14.6 WDTA registers

14.6.1 WDTA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

14.6.2 WDTA registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

. . . . . . . . . . . . . . . . 611

. . . . . . . . . . . . . 626

Chapter 15 Timer Array Unit A (TAUA)

15.1 V850E2/Fx4 TAUA Features

15.2 TAUA Input Selection

15.2.1 TAUA0 input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

15.3 Functional Overview

15.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

15.4 Functional Description

15.5 General Operating Procedure

15.6 Operation Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

15.7 Concepts of Synchronous Channel Operation

15.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

15.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . . 654

15.8 Simultaneous Rewrite

15.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

15.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

15.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . 658

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

. . . . . . . . . . . . . . . . . . . . . . . . . . . 634

. . . . . . . . . . . . . . . . . . . 652

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15.8.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

15.9 Channel Output Modes

15.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . . 669

15.9.2 Channel output modes controlled independently by TAUAn signals . . . . . . 670

15.9.3 Channel output modes controlled synchronously by TAUAn signals. . . . . . 672

15.10 Start Timing of Operating Modes

15.10.1 Interval Timer Mode, Judge Mode, Capture Mode, Up Down Count Mode. 677

15.10.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678

15.10.3 All other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

15.11 TAUAnTTOUTm Output and INTTAUAnIm Generation when Counter Starts or Restarts

15.12 Interrupt Generation upon Overflow

15.12.1 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

15.12.2 Capture and One Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

15.12.3 Count Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

15.12.4 Capture and Gate Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

15.13 TAUAnTTINm Edge Detection

15.14 Assigning DMA Window Addresses

15.15 Independent Channel Operation Functions

15.16 Independent Channel Interrupt Functions

15.16.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

15.16.2 TAUAnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . 695

15.16.3 Delay Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

15.16.4 One-Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

15.17 Independent Channel Signal Measurement Functions

15.17.1 TAUAnTTINm Input Pulse Interval Measurement Function. . . . . . . . . . . . . 712

15.17.2 TAUAnTTINm Input Signal Width Measurement Function . . . . . . . . . . . . . 720

15.17.3 Overflow Interrupt Output Function

(During TAUAnTTINm Width Measurement). . . . . . . . . . . . . . . . . . . . . . . . 728

15.17.4 TAUAnTTINm Input Period Count Detection Function. . . . . . . . . . . . . . . . . 733

15.17.5 Overflow Interrupt Output Function

(During TAUAnTTINm Input Period Count Detection) . . . . . . . . . . . . . . . . . 739

15.17.6 TAUAnTTINm Input Pulse Interval Judgment Function. . . . . . . . . . . . . . . . 744

15.17.7 TAUAnTTINm Input Signal Width Judgment Function. . . . . . . . . . . . . . . . . 749

15.18 Independent Channel Real-Time Functions

15.18.1 Real-Time Output Function Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

15.18.2 Real-Time Output Function Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

15.19 Independent Channel Simultaneous Rewrite Functions

15.19.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . . 770

15.19.2 Simultaneous Rewrite Trigger Generation Function Type 2 . . . . . . . . . . . . 776

15.20 Independent Channel One-Phase PWM Function

15.20.1 One-Phase PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

15.21 Other Independent Channel Functions

15.21.1 External Event Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

15.21.2 Clock Divide Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

15.21.3 TAUAnTTINm Input Position Detection Function. . . . . . . . . . . . . . . . . . . . . 805

15.22 Synchronous Channel Operation Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

. . . . . . . . . . . . . . . . . . . . . . 687

. . . . . . . . . . . . . . . . . . . . . . . 687

. . . . . . . . . . . . . . . . . . . . . . 754

. . . . . . . . . . . . . . . . . . . . . . . . . . 790

. . . . . . . . . . . . . . . . . . . . . 811

. . . . . . . . . . . 711

. . . . . . . . . . 769

. . . . . . . . . . . . . . . . 782

15.23 Synchronous PWM Signal Functions Triggered at Regular Intervals

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811

15.23.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

15.23.2 Trigger Start PWM Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

15.23.3 Delay Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

15.23.4 AD Conversion Trigger Output Function Type 1 . . . . . . . . . . . . . . . . . . . . . 850

15.24 Synchronous PWM Signal Functions Triggered by an External Signal

852

15.24.1 One-Shot Pulse Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853

15.24.2 Offset Trigger Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

15.25 Synchronous Triangle PWM Functions

15.25.1 Triangle PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

15.25.2 Triangle PWM Output Function with Dead Time . . . . . . . . . . . . . . . . . . . . . 887

15.25.3 AD Conversion Trigger Output Function Type 2 . . . . . . . . . . . . . . . . . . . . . 910

15.26 Synchronous Real-Time Output Functions

15.26.1 Synchronous Real-Time Output Function Type 1 . . . . . . . . . . . . . . . . . . . . 913

15.26.2 Synchronous Real-Time Output Function Type 2 . . . . . . . . . . . . . . . . . . . . 924

15.26.3 Synchronous Real-Time Output Function Type 3 . . . . . . . . . . . . . . . . . . . . 935

. . . . . . . . . . . . . . . . . . . . . . . . . . 875

. . . . . . . . . . . . . . . . . . . . . . 912

15.27 Synchronous Non-Complementary and Complementary Functions

946

15.27.1 Non-Complementary Modulation Output Function Type 1 . . . . . . . . . . . . . 947

15.27.2 Non-Complementary Modulation Output Function Type 2 . . . . . . . . . . . . . 960

15.27.3 Complementary Modulation Output Function . . . . . . . . . . . . . . . . . . . . . . . 974

15.28 Other Synchronous Channel Functions

15.28.1 Interrupt Culling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

15.29 Registers

15.29.1 TAUAn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

15.29.2 TAUAn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

15.29.3 TAUAn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006

15.29.4 TAUAn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

15.29.5 TAUAn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1022

15.29.6 TAUAn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1023

15.29.7 TAUAn DMA window registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026

15.29.8 TAUAn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001

. . . . . . . . . . . . . . . . . . . . . . . . . 992

Chapter 16 Timer Array Unit B (TAUB)

16.1 V850E2/Fx4 TAUB Features

16.2 TAUB Input Selection

16.2.1 TAUB1TTIN[7:0] input selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034

16.3 Functional Overview

16.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036

16.4 Functional Description

16.5 General Operating Procedure

16.6 Operation Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042

16.7 Concepts of Synchronous Channel Operation

16.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043

16.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1045

16.8 Simultaneous Rewrite

16.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041

. . . . . . . . . . . . . . . . . . . . . . . . . . 1029

. . . . . . . . . . . . . . . . . . 1043

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16.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

16.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1049

16.8.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

16.9 Channel Output Modes

16.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1058

16.9.2 Channel output modes controlled independently by TAUBn signals. . . . . 1059

16.9.3 Channel output modes controlled synchronously by TAUBn signals. . . . . 1060

16.10 Start Timing of Operating Modes

16.10.1 Interval Timer Mode, Judge Mode, Capture Mode, Up Down Count Mode 1063

16.10.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064

16.10.3 All other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

16.11 TAUBnTTOUTm toggle and INTTAUBnIm Generation when Counter start is triggered (MD0-bit)

16.12 TAUBnTTINm Edge Detection

16.13 Independent Channel Operation Functions

16.14 Independent Channel Interrupt Functions

16.14.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

16.14.2 TAUBnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . 1077

16.14.3 One-Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083

16.15 Independent Channel Signal Measurement Functions

16.15.1 TAUBnTTINm Input Pulse Interval Measurement Function. . . . . . . . . . . . 1089

16.15.2 TAUBnTTINm Input Signal Width Measurement Function . . . . . . . . . . . . 1097

16.15.3 Overflow Interrupt Output Function

(During TAUBnTTINm Width Measurement). . . . . . . . . . . . . . . . . . . . . . . 1105

16.15.4 TAUBnTTINm Input Period Count Detection Function . . . . . . . . . . . . . . . 1110

16.15.5 Overflow Interrupt Output Function

(During TAUBnTTINm Input Period Count Detection) . . . . . . . . . . . . . . . . 1116

16.15.6 TAUBnTTINm Input Pulse Interval Judgment Function. . . . . . . . . . . . . . . 1121

16.15.7 TAUBnTTINm Input Signal Width Judgment Function. . . . . . . . . . . . . . . . 1126

16.16 Independent Channel Simultaneous Rewrite Functions

16.16.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . 1132

16.17 Other Independent Channel Functions

16.17.1 External Event Count Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139

16.17.2 Clock Divide Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146

16.17.3 TAUBnTTINm Input Position Detection Function. . . . . . . . . . . . . . . . . . . . 1153

16.18 Synchronous Channel Operation Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067

. . . . . . . . . . . . . . . . . . . . . 1068

. . . . . . . . . . . . . . . . . . . . . . 1068

. . . . . . . . . . 1088

. . . . . . . . . 1131

. . . . . . . . . . . . . . . . . . . . . . . . . 1138

. . . . . . . . . . . . . . . . . . . . 1159

16.19 Synchronous PWM Signal Functions Triggered at Regular Intervals

1159

16.19.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160

16.19.2 Delay Pulse Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171

16.19.3 AD Conversion Trigger Output Function Type 1 . . . . . . . . . . . . . . . . . . . . 1187

16.20 Synchronous PWM Signal Functions Triggered by an External Signal

1189

16.20.1 One-Shot Pulse Output Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190

16.21 Synchronous Triangle PWM Functions

16.21.1 Triangle PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203

16.21.2 Triangle PWM Output Function with Dead Time . . . . . . . . . . . . . . . . . . . . 1214

16.21.3 AD Conversion Trigger Output Function Type 2 . . . . . . . . . . . . . . . . . . . . 1237

. . . . . . . . . . . . . . . . . . . . . . . . . 1202

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16.22 Registers

16.22.1 TAUBn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239

16.22.2 TAUBn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240

16.22.3 TAUBn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242

16.22.4 TAUBn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252

16.22.5 TAUBn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1255

16.22.6 TAUBn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1256

16.22.7 TAUBn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259

Chapter 17 Timer Array Unit C (TAUC)

17.1 V850E2/Fx4 TAUC Features

17.2 Functional Overview

17.2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267

17.3 Functional Description

17.4 General Operating Procedure

17.5 Operation Modes

17.6 Concepts of Synchronous Channel Operation

17.6.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271

17.6.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1273

17.7 Simultaneous Rewrite

17.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274

17.7.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275

17.7.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1276

17.7.4 Types of simultaneous rewrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277

17.8 Channel Output Modes

17.8.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1283

17.8.2 Channel output modes controlled independently by TAUCn signals. . . . . 1284

17.8.3 Channel output modes controlled synchronously by TAUCn signals . . . . 1285

17.9 Start Timing of Operating Modes

17.9.1 Interval Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286

17.9.2 Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239

. . . . . . . . . . . . . . . . . . . . . . . . . . 1260

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270

. . . . . . . . . . . . . . . . . . 1271

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286

17.10 TAUCnTTOUTm toggle and INTTAUCnIm Generation when Counter start is triggered (MD0-bit)

17.11 Independent Channel Operation Functions

17.12 Independent Channel Interrupt Functions

17.12.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290

17.13 Independent Channel Simultaneous Rewrite Functions

17.13.1 Simultaneous Rewrite Trigger Generation Function Type 1 . . . . . . . . . . . 1299

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288

. . . . . . . . . . . . . . . . . . . . . 1289

. . . . . . . . . . . . . . . . . . . . . . 1289

. . . . . . . . . 1298

17.14 Synchronous PWM Signal Functions Triggered at Regular Intervals

1305

17.14.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306

17.15 Registers

17.15.1 TAUCn registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317

17.15.2 TAUCn prescaler registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318

17.15.3 TAUCn control registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320

17.15.4 TAUCn output registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325

17.15.5 TAUCn channel output level registers details . . . . . . . . . . . . . . . . . . . . . . 1326

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317

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17.15.6 TAUCn simultaneous rewrite register details. . . . . . . . . . . . . . . . . . . . . . . 1327

17.15.7 TAUCn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330

Chapter 18 Timer Array Unit J (TAUJ)

18.1 V850E2/Fx4 TAUJ Features

18.2 TAUJ Input Selection

18.2.1 TAUJ0/TAUJ1 input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335

18.3 Functional Overview

18.3.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341

18.4 Functional Description

18.5 General Operating Procedure

18.6 Operation Modes

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347

18.7 Concepts of Synchronous Channel Operation

18.7.1 Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348

18.7.2 Simultaneous start and stop of synchronous channel counters . . . . . . . . 1350

18.8 Simultaneous Rewrite

18.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351

18.8.2 How to control simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352

18.8.3 Other general rules of simultaneous rewrite . . . . . . . . . . . . . . . . . . . . . . . 1353

18.8.4 Simultaneous rewrite procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351

18.9 Channel Output Modes

18.9.1 General procedure for specifying a channel output mode. . . . . . . . . . . . . 1358

18.9.2 Channel output modes controlled independently by TAUJn signals . . . . . 1359

18.9.3 Channel output modes controlled synchronously by TAUJn signals. . . . . 1360

18.10 Start Timing of Operating Modes

18.10.1 Interval Timer Mode, Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361

18.10.2 Other operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1331

. . . . . . . . . . . . . . . . . . 1348

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361

18.11 TAUJnTTOUTm Output and INTTAUJnIm Generation when Counter Starts or Restarts

18.12 Interrupt Generation upon Overflow

18.12.1 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365

18.12.2 Capture and One Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366

18.12.3 Count Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367

18.12.4 Capture and Gate Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368

18.13 TAUJnTTINm Edge Detection

18.14 Independent Channel Operation Functions

18.15 Independent Channel Interrupt Functions

18.15.1 Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371

18.15.2 TAUJnTTINm Input Interval Timer Function . . . . . . . . . . . . . . . . . . . . . . . 1378

18.16 Independent Channel Signal Measurement Fuctions

18.16.1 TAUJnTTINm Input Pulse Interval Measurement Function. . . . . . . . . . . . 1385

18.16.2 TAUJnTTINm Input Signal Width Measurement Function. . . . . . . . . . . . . 1392

18.16.3 Overflow Interrupt Output Function

(During TAUJnTTINm Width Measurement) . . . . . . . . . . . . . . . . . . . . . . . 1399

18.16.4 TAUJnTTINm Input Period Count Detection Function. . . . . . . . . . . . . . . . 1403

18.16.5 Overflow Interrupt Output Function

(During TAUJnTTINm Input Period Count Detection) . . . . . . . . . . . . . . . . 1409

18.17 Other Independent Channel Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369

. . . . . . . . . . . . . . . . . . . . . 1370

. . . . . . . . . . . . . . . . . . . . . . 1370

. . . . . . . . . . . 1384

. . . . . . . . . . . . . . . . . . . . . . . . . 1414

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18.17.1 TAUJnTTINm Input Position Detection Function. . . . . . . . . . . . . . . . . . . . 1415

18.18 Synchronous PWM Signal Functions Triggered at Regular Intervals

1421

18.18.1 PWM Output Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422

18.19 Registers

18.19.1 TAUJn registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433

18.19.2 TAUJn prescaler registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434

18.19.3 TAUJn control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437

18.19.4 TAUJn output registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447

18.19.5 TAUJn simultaneous rewrite register details . . . . . . . . . . . . . . . . . . . . . . . 1450

18.19.6 TAUJn emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433

Chapter 19 Real-Time Clock (RTCA)

19.1 V850E2/Fx4 RTCA Features

19.2 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456

19.3 Functional Description

19.3.1 Operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458

19.3.2 Clock counter format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458

19.3.3 Fixed interval interrupt function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459

19.3.4 Alarm interrupt function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460

19.3.5 Clock error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461

19.4 Registers

19.4.1 RTCA registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465

19.4.2 RTCA control registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467

19.4.3 RTCA sub-counter registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471

19.4.4 RTCA clock counter and buffer registers details. . . . . . . . . . . . . . . . . . . . 1475

19.4.5 RTCA special counter and buffer registers details . . . . . . . . . . . . . . . . . . 1490

19.4.6 RTCA alarm setting registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494

19.4.7 RTCA emulation register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453

19.5 Procedures for Setup, Writing and Reading

19.5.1 Initial setting of the RTCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498

19.5.2 Updating clock counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500

19.5.3 Reading clock counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501

19.5.4 Reading RTCAnSRBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504

19.5.5 Writing to RTCAnSUBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505

19.5.6 Writing to RTCAnSCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506

19.6 Timing diagrams

19.6.1 Timing of RTCA counter start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507

19.6.2 Timing of RTCA while counter is enabled . . . . . . . . . . . . . . . . . . . . . . . . . 1508

19.6.3 Timing of sub-counter buffer read while counter is enabled . . . . . . . . . . . 1509

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507

. . . . . . . . . . . . . . . . . . . . 1498

Chapter 20 Motor Control

20.1 Basic structure of motor control

20.2 V850E2/Fx4 Timer Motor Control Function (TAPA) Features

20.3 TAPA0 Hi-Z control input selection

20.4 Functional Overview

20.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517

20.4.2 Peak and valley interrupts - Peak and valley of timer counter. . . . . . . . . . 1518

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510

. . . . 1512

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517

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20.5 Registers

20.5.1 Registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519

20.5.2 Registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520

20.6 Basic Functions

20.6.1 Asynchronous Hi-Z control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525

20.6.2 INT signal output selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532

20.6.3 A/D conversion trigger selection function . . . . . . . . . . . . . . . . . . . . . . . . . 1533

20.7 Three-Phase PWM Output with Dead Time

20.7.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537

20.7.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537

20.7.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540

20.7.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549

20.7.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1551

20.7.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525

. . . . . . . . . . . . . . . . . . . . . . 1537

20.8 High-accuracy Triangle PWM Output with Dead Time

20.8.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564

20.8.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565

20.8.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568

20.8.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581

20.8.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1583

20.8.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591

20.9 Delay Pulse Output with Dead Time

20.9.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603

20.9.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603

20.9.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606

20.9.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612

20.9.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1615

20.9.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603

. . . . . . . . . . . 1564

Chapter 21 Encoder Timer

21.1 Basic structure of Encoder Timer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628

21.2 V850E2/Fx4 Encoder Timer (ENCA) Features

21.3 ENCA Functional Overview

21.3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634

21.3.2 Preliminary knowledge for understanding basic specifications. . . . . . . . . 1635

21.4 ENCA Control Registers

21.5 ENCA Functional Description

21.5.1 Timer counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647

21.5.2 Up/down control of timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649

21.5.3 Timer counter clear control by encoder input . . . . . . . . . . . . . . . . . . . . . . 1653

21.5.4 Functions of ENCAnCCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654

21.5.5 Functions of ENCAnCCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655

21.6 ENCA Setting Sequences

21.6.1 Encoder timer setting procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658

21.7 A/D Trigger Encoder Capture

21.7.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661

21.7.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661

21.7.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661

. . . . . . . . . . . . . . . . . . . 1630

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21.7.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663

21.7.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1664

21.7.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666

21.8 Synchronized Timer Operation

21.8.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668

21.8.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668

21.8.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669

21.8.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670

21.8.5 Setting up operation functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670

21.8.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671

21.9 Trigger Pulse Width Measurement

21.9.1 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673

21.9.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673

21.9.3 Operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675

21.9.4 Setup flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678

21.9.5 Example of setting up operation functions . . . . . . . . . . . . . . . . . . . . . . . . 1681

21.9.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673

Chapter 22 PWM Diagnostic

22.1 PWM Diagnostic functional overview

22.1.1 Basic concept and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690

22.1.2 PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691

22.1.3 Channel-to-channel delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692

22.1.4 A/D Converter trigger delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693

22.1.5 Synchronous PWM groups multiplexer and A/D Converter control. . . . . . 1694

22.1.6 A/D Converter conversion result memory transfer . . . . . . . . . . . . . . . . . . 1696

22.1.7 Diagnostic value evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696

22.2 PWM Delay (DLYA)

22.2.1 DLYA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698

22.2.2 PWM Delay (DLYA) bypass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702

22.2.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704

22.2.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705

22.2.5 Procedure for Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710

22.2.6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1690

22.3 PWM Diagnostic timing and trigger generation (PMCA)

22.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711

22.3.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714

22.3.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721

22.3.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723

22.3.5 Procedures for Setup, Writing and Reading . . . . . . . . . . . . . . . . . . . . . . . 1727

. . . . . . . . . 1711

Chapter 23 Asynchronous Serial Interface E (URTE)

23.1 V850E2/Fx4 URTEn Features

23.2 Functional Overview

23.3 Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734

23.4 URTE Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735

23.5 Interrupt Request Signals

23.5.1 Transmission interrupt request INTUAEnTIT. . . . . . . . . . . . . . . . . . . . . . . 1751

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. . . . . . . . . 1728

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23.5.2 Reception interrupt request INTUAEnTIR. . . . . . . . . . . . . . . . . . . . . . . . . 1752

23.5.3 Status interrupt request INTUAEnTIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753

23.6 Operation

23.6.1 Data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753

23.6.2 BF transmission/reception format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755

23.6.3 BF transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757

23.6.4 BF reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758

23.6.5 Transmission data consistency check . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760

23.6.6 URTEn transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761

23.6.7 Continuous transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762

23.6.8 URTEn reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764

23.6.9 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766

23.6.10 Parity types and operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767

23.6.11 Digital receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768

23.7 Baud Rate Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769

Chapter 24 LIN Master Controller (LMA)

24.1 V850E2/Fx4 LMAn Features

24.2 LIN Master Scheduler Counters (CNTA)

24.2.1 CNTAm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776

24.3 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778

24.4 Functional Description

24.4.1 UART through mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780

24.4.2 UART buffer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781

24.4.3 LIN master modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787

24.4.4 Automatic checksum function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799

24.4.5 Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800

24.5 LMAn Registers

24.5.1 LMAn registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805

24.5.2 LMAn registers details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805

Chapter 25 CAN Controller (FCN)

25.1 V850E2/Fx4 FCN Features

25.2 FCN0 and FCN1 connection

25.3 CAN baudrate and time quanta

25.4 Features

25.4.1 Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830

25.4.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832

25.5 Internal Registers of CAN Controller

25.5.1 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833

25.5.2 CAN Controller Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835

25.5.3 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837

25.6 Bit Set/Clear Function

25.7 Control Registers

25.7.1 CAN Controller global registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844

25.7.2 CAN channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853

25.7.3 Message buffer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833

. . . . . . . . . . . . . . . . . . . . . . . . 1770

. . . . . . . . . . . . . . . . . . . . . . . . . 1776

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25.8 CAN Controller Initialization

25.8.1 Initialization of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884

25.8.2 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884

25.8.3 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884

25.8.4 Transition from initialization mode to operation mode. . . . . . . . . . . . . . . . 1886

25.9 Message Reception

25.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887

25.9.2 Receive data read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888

25.9.3 Receive history list function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889

25.9.4 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891

25.9.5 Multi buffer receive block function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893

25.9.6 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887

25.10 Message Transmission

25.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896

25.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898

25.10.3 Automatic block transmission (ABT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900

25.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902

25.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903

25.11 Power Saving Modes

25.11.1 CAN Controller sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904

25.11.2 CAN Controller stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1907

25.11.3 Example of using power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 1908

25.12 Interrupt Function

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1904

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1909

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896

25.13 Diagnosis Functions and Special Operational Modes

25.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910

25.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911

25.13.3 Self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912

25.13.4 Receive/transmit operation in each operation mode. . . . . . . . . . . . . . . . . 1913

25.14 Time Stamp Function

25.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914

25.15 Baudrate Settings

25.15.1 Baudrate setting conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915

25.15.2 Clock prescaler and baudrate generator settings . . . . . . . . . . . . . . . . . . . 1919

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915

25.16 Operation of the CAN Controller

25.16.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921

25.16.2 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927

25.16.3 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941

25.16.4 Power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921

. . . . . . . . . . . 1910

Chapter 26 Diagnostic CAN Controller (DCN)

26.1 V850E2/Fx4 DCN Features

26.2 Diagnostic CAN Controller (DCN) baudrate and time quanta

26.3 Introduction

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957

26.4 Overview of Functions

26.5 Architecture

26.5.1 CPU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961

26.5.2 Global module control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961

26.5.3 CAN interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959

. . . . . . . . . . . . . . . . . . 1953

. . . . 1956

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26.5.4 Message control (MSG Ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961

26.5.5 Arbitration logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962

26.5.6 RXONLY_CH CAN machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962

26.5.7 DIAG_CH CAN machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963

26.6 Module Initialisation and Control

26.6.1 Global Module initialisation and control. . . . . . . . . . . . . . . . . . . . . . . . . . . 1965

26.6.2 Message buffer initialisation and configuration . . . . . . . . . . . . . . . . . . . . . 1974

26.6.3 Message buffer to CAN I/F channel assignment. . . . . . . . . . . . . . . . . . . . 1975

26.6.4 DCN module initialisation and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980

26.6.5 CAN bit time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980

26.6.6 Transitions for operational modes of DIAG_CH. . . . . . . . . . . . . . . . . . . . . 1981

26.6.7 Transition for operational modes of RXONLY_CH. . . . . . . . . . . . . . . . . . . 1983

26.7 Module Interrupts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985

26.8 Message Reception of RXONLY Channel

26.8.1 Principal reception process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989

26.8.2 Reception History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989

26.8.3 Reception of remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990

26.9 Message Transmission

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990

26.10 Operational Modes of RXONLY_CH

26.10.1 Receive–only mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991

26.10.2 Mirror mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996

26.10.3 Mirror mode with TIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1998

26.11 Transitions for Buffer Assignment

26.12 Register Description

26.12.1 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002

26.12.2 DCN global registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010

26.12.3 DCN module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016

26.12.4 DCN message buffers registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964

. . . . . . . . . . . . . . . . . . . . . . . 1989

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1999

Chapter 27 Clocked Serial Interface G (CSIG)

27.1 V850E2/Fx4 CSIG Features

27.1.1 Data consistency check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043

27.2 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044

27.3 Functional Description

27.3.1 Master/slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046

27.3.2 Master/slave connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047

27.3.3 Transmission clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2049

27.3.4 Data transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2050

27.3.5 Data length selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051

27.3.6 Serial data direction select function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053

27.3.7 Communication in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2054

27.3.8 CSIG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055

27.3.9 Handshake function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057

27.3.10 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060

27.3.11 Error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061

27.4 CSIG Control Registers

27.5 Operating Procedure Example

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2064

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076

. . . . . . . . . . . . . . . . . . 2039

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Chapter 28 Clocked Serial Interface H (CSIH)

28.1 V850E2/Fx4 CSIH Features

28.1.1 Data consistency check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082

28.2 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2083

28.3 Functional Description

28.3.1 Operating modes (master/slave). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086

28.3.2 Master/slave connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087

28.3.3 Chip selection (CS) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089

28.3.4 The job concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091

28.3.5 Chip select timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092

28.3.6 Transmission clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093

28.3.7 CSIH buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094

28.3.8 Data transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096

28.3.9 Data length selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097

28.3.10 Serial data direction selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100

28.3.11 Communication in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2101

28.3.12 CSIH interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102

28.3.13 Handshake function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110

28.3.14 Error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113

28.3.15 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2122

28.4 CSIH Control Registers

28.4.1 CSIH registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124

28.5 Operating Procedures

28.5.1 Procedures in direct access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147

28.5.2 Procedures in transmit-only buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . 2152

28.5.3 Procedures in dual buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156

28.5.4 Procedures in FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2078

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2085

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147

. . . . . . . . . . . . . . . . . . 2078

Chapter 29 I2C Interface (IICB)

29.1 V850E2/Fx4 IICB Features

29.2 I2C Interface Port Settings

29.3 Functional Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169

29.4 I2C Bus Mode Functions

29.4.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171

29.5 I2C Bus Definition

29.5.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173

29.5.2 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173

29.5.3 Extension code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2174

29.5.4 Transfer direction specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2174

29.5.5 Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2175

29.5.6 Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176

29.5.7 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176

29.5.8 Wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2177

29.5.9 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179

29.6 Registers

29.7 Operation

29.7.1 Single transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204

29.7.2 Continuous transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2180

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166

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29.7.3 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214

29.7.4 Entering and exiting wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215

29.7.5 Extension code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220

29.8 Interrupt Request Signals

29.8.1 Single transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222

29.8.2 Continuous transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225

29.9 Interrupt Outputs and Statuses

29.9.1 Single transfer mode (master device operation) . . . . . . . . . . . . . . . . . . . . 2232

29.9.2 Single transfer mode (slave device operation: during slave address reception

(IICBnSTR0.IICBnSSC0 bit = 1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235

29.9.3 Single transfer mode (slave device operation: during extension code reception

(IICBnSTR0.IICBnSSEX bit = 1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239

29.9.4 Single transfer mode (non-participation in communications) . . . . . . . . . . 2243

29.9.5 Single transfer mode (arbitration loss operation

(IICBnSTR0.IICBnALDF bit = 1): operation as slave after arbitration loss) 2244

29.9.6 Single transfer mode (arbitration loss operation

(IICBnSTR0.IICBnALDF bit = 1): non-participation in communications after

arbitration loss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2246

29.9.7 Single transfer mode (arbitration loss operation (IICBnSTR0.IICBnALDF bit =

1): non-participation in communications after arbitration loss (during extension

code transfer)). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2252

29.9.8 Continuous transfer mode (master device operation (reception)) . . . . . . . 2253

29.9.9 Continuous transfer mode (master device operation (transmission)) . . . . 2256

29.9.10 Continuous transfer mode (slave device operation (reception): during slave

address reception (IICBnSTR0.IICBnSSC0 bit = 1)). . . . . . . . . . . . . . . . . 2259

29.9.11 Continuous transfer mode (slave device operation (reception): during extension

code reception (IICBnSTR0.IICBnSSEX bit = 1)) . . . . . . . . . . . . . . . . . . . 2263

29.9.12 Continuous transfer mode (slave device operation (transmission): during slave

address reception (IICBnSTR0.IICBnSSC0 bit = 1)). . . . . . . . . . . . . . . . . 2267

29.9.13 Continuous transfer mode (slave device operation (transmission): during

extension code reception (IICBnSTR0.IICBnSSEX bit = 1)). . . . . . . . . . . 2271

29.9.14 Continuous transfer mode (non-participation in communications) . . . . . . 2275

29.9.15 Continuous transfer mode (arbitration loss operation (IICBnSTR0.IICBnALDF

bit = 1) (when address was transferred during reception): operation as slave

after arbitration loss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2276

29.9.16 Continuous transfer mode (arbitration loss operation (IICBnSTR0.IICBnALDF

bit = 1) (when address was transferred during reception): non-participation in

communications after arbitration loss). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278

29.9.17 Continuous transfer mode (arbitration loss operation (IICBnSTR0.IICBnALDF

bit = 1) (when address was transferred during reception): non-participation in communications after arbitration loss (during extension code transfer)). . 2283

29.10 Setting Sequence

29.10.1 Single master environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285

29.10.2 Multi-master environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2221

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231

Chapter 30 FlexRay

30.1 V850E2/Fx4 FLXn Features

30.2 E-Ray Overview

30.2.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300

30.2.2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300

30.2.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297

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30.2.4 Terms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300

30.2.5 Functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301

30.2.6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303

30.2.7 Host CPU interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305

30.2.8 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305

30.3 Programmer’s Model

30.3.1 Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306

30.3.2 E-Ray registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311

30.3.3 Special registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316

30.3.4 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2323

30.3.5 CC control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2344

30.3.6 CC status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2368

30.3.7 Message buffer control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2385

30.3.8 Message buffer status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2391

30.3.9 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404

30.3.10 Input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2406

30.3.11 Output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2415

30.4 Functional Description

30.4.1 Communication cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426

30.4.2 Communication modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428

30.4.3 Clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429

30.4.4 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431

30.4.5 Communication controller states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2433

30.4.6 Network management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2448

30.4.7 Filtering and masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2448

30.4.8 Transmit process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2451

30.4.9 Receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454

30.4.10 FIFO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456

30.4.11 Message handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458

30.4.12 Message RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468

30.4.13 Module interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477

30.5 Appendix

30.5.1 Assignment of FlexRay Configuration Parameters . . . . . . . . . . . . . . . . . . 2479

30.6 Cautions

30.6.1 Loop back mode operates only at 10 MBit/s. . . . . . . . . . . . . . . . . . . . . . . 2481

30.6.2 Noise following a dynamic frame that delays idle detection may fail to stop slot

30.6.3 Register FLXnRCV displays wrong value.. . . . . . . . . . . . . . . . . . . . . . . . . 2482

30.6.4 After reception of a valid sync frame followed by a valid non-sync frame in the

30.6.5 Sync frame overflow flag FLXnEIR.FLXnSFO may be set if slot counter is

30.6.6 Acceptance of startup frames received after reception of more than

30.6.7 Initial rate correction value of an integrating node is zero if

30.6.8 Incorrect rate and/or offset correction value if second Secondary Time

30.6.9 Flag SFS.MRCS is set erroneously although at least one valid sync frame pair

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2481

counting for the remainder of the dynamic segment . . . . . . . . . . . . . . . . . 2481

same static slot the received sync frame may be ignored. . . . . . . . . . . . . 2482

greater than 1024.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483

gSyncNodeMax sync frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483

pMicroInitialOffsetA,B = 00H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2484

Reference Point (STRP) coincides with the action point after detection of a valid

frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485

is received. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426

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30.6.10 Rate correction set to zero in case of SyncCalcResult=MISSING_TERM. 2486

30.6.11 A sequence of received WUS may generate redundant FLXnSIR.FLXnWUPA/

B events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2486

30.6.12 Erroneous cycle offset during startup after abort of startup or normal operation

by a READY or FREEZE command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2487

30.6.13 First WUS following received valid WUP may be ignored. . . . . . . . . . . . . 2487

30.6.14 READY command accepted in READY state. . . . . . . . . . . . . . . . . . . . . . . 2488

30.6.15 Slot Status vPOC!SlotMode is reset immediately when entering HALT state

(CCSV.SLM[1:0] = "00"). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488

30.6.16 Received messages not stored in Message RAM when in Loop Back Mode. .

2488

Chapter 31 Random Number Generator A (RNGA)

31.1 V850E2/Fx4 RNGA Features

31.2 Functional Overview

31.3 Functional Description

31.3.1 RNGA status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491

31.3.2 RNGA start and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491

31.4 Registers

31.4.1 Registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492

31.4.2 Registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491

Chapter 32 Key Return Function (KR)

32.1 V850E2/Fx4 KR Features

32.2 Functional Overview

32.3 Functional Description

32.3.1 Interrupt request KRnTIKR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496

32.4 Registers

32.4.1 Key Return Function registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2497

32.4.2 Key Return Function registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2497

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2497

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2495

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2489

. . . . . . . . . . . . . . . . . . . . . . . . . . . 2493

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2493

. . . . . . . . . . . . 2489

Chapter 33 A/D Converter A (ADCA)

33.1 V850E2/Fx4 ADCA Features

33.2 H/W Trigger Expansion

33.2.1 ADCAn H/W trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502

33.2.2 ADCAn H/W trigger edge selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503

33.2.3 ADCA0 H/W trigger selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504

33.2.4 ADCA1 H/W trigger selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2509

33.3 Functional Overview

33.4 Cautions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511

33.5 Functional Description

33.5.1 Basic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515

33.5.2 Clock usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2516

33.5.3 Channels and channel groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2516

33.5.4 A/D conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2518

33.5.5 Starting A/D conversion (start trigger modes). . . . . . . . . . . . . . . . . . . . . . 2521

33.5.6 Stopping A/D conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523

33.5.7 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2525

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2498

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33.5.8 Pausing and resuming A/D conversion (ADCHALT mode) . . . . . . . . . . . . 2525

33.5.9 Resolution, sampling and conversion times . . . . . . . . . . . . . . . . . . . . . . . 2526

33.5.10 Interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2527

33.5.11 Storage of A/D conversion result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2528

33.5.12 Result check functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2531

33.5.13 Channel S&H function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533

33.5.14 Self-diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2540

33.5.15 Discharge function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2547

33.5.16 Buffer amplifier function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2548

33.5.17 Stabilization control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2548

33.6 Registers

33.6.1 ADCA registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549

33.6.2 Control registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2551

33.6.3 Conversion status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2562

33.6.4 S/W trigger registers details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566

33.6.5 ADCA conversion result registers details . . . . . . . . . . . . . . . . . . . . . . . . . 2568

33.6.6 A/D conversion result upper/lower limit comparison registers details. . . . 2575

33.6.7 Diagnose functions registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2579

33.6.8 Emulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549

Chapter 34 Voltage Comparator (VCPC)

34.1 V850E2/Fx4 VCPC Features

34.2 Overview

34.2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586

34.2.2 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586

34.3 Voltage Comparator Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2583

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2589

Chapter 35 On-chip Debug Unit (OCD)

35.1 V850E2/Fx4 On-chip Debug Features

35.1.1 Modules behaviour during emulation break . . . . . . . . . . . . . . . . . . . . . . . 2592

35.1.2 Signal masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2594

35.2 Functional Overview

35.3 Emulation Break Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2594

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597

35.4 Connection with On-Chip Debug Emulator

35.5 Cautions on using On-Chip Debugging

Chapter 36 Boundary Scan

36.1 Outline

36.2 JTAG interface

36.3 Entering Boundary Scan mode

36.4 Boundary scan features

36.5 Boundary Scan applicable pins

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600

36.6 DID - Boundary scan ID register

. . . . . . . . . . . . . . . . . . . . . . . . . . . 2592

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2601

. . . . . . . . . . . . . . . . . . . . . . . . 2583

. . . . . . . . . . . . . . . . . . . . . . . . . . 2592

. . . . . . . . . . . . . . . . . . . . . 2598

. . . . . . . . . . . . . . . . . . . . . . . . . 2598

Chapter 37 Power Supply

37.1 Power supply pins naming

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2602

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37.2 Power supply schemes

37.2.1 V850E2/Fx4-M1 and -M2 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603

37.2.2 V850E2/FG4 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2605

37.2.3 V850E2/FJ4 power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2606

37.2.4 V850E2/FK4 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607

37.2.5 V850E2/FL4 power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2608

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603

37.3 Power-up and down procedures

37.3.1 Power Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612

37.3.2 Initial power-up and final power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2614

37.3.3 DEEPSTOP entry and wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2615

37.3.4 Other power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619

Revision History

Revision History Rev. 0.04 Revision History Rev. 1.00 Revision History Rev. 1.01 Revision History Rev. 1.02 Revision History Rev. 1.03

Index

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2635

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2626

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2630

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2631

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2610

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How to use this manual

Purpose and target readers

This manual is designed to provide the user with an understanding of the hardware functions of the microcontroller. It is intended for users designing application systems incorporating the microcontroller. A basic knowledge of electric circuits, logical circuits, and microcontrollers is necessary in order to use this manual.

Special notations

Following special notations are used throughout this document:

Note Additional remark or tip

Caution Item deserving extra attention

Electrical specifications

This manual does not present any electrical specifications. Refer to the "Electrical Target Specification" for detailed definitions of all electrical properties. For information about the "Electrical Target Specification" document, refer to the section “Related Documents” in the chapter “Introduction”.

Additional documents

Following types of documents are available for the V850E2/Fx4 microcontrollers. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Electronics Web site.

Document Type Description Document

Data sheet Hardware overview and electrical characteristics Refer to the section User manual:

Hardware

User manual: 32-bit Microprocessor Core Architecture

Hardware specifications (pin assignments, memory maps, functional modules specifications and operation description) Note: Refer to the application notes for details on using functional modules.

Description of CPU, its instruction set and processor protection functions

“Related Documents” in the chapter “Introduction”

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How to use this manual

Document Type Description Document

Application note Information on using peripheral functions and application

examples, sample programs and information on writing programs in assembly language and C

Renesas technical update

Product specifications, updates on documents, etc.

Available from Renesas Electronics Web site

Content of this manual

In the following brief hints are given where to find certain information about the V850E2/Fx4 microcontrollers.

Product overview Refer to the chapter “Introduction” for an overview of the features of all target

microcontrollers and their block diagrams. Order codes for all devices and a list of related documents is given here as well.

CPU core functions The functions of the CPU core (e.g. instruction set, processor protection

functions, etc.) are not subject to this manual. Refer to the separate CPU core manual, shown in the section “Related Documents” in the chapter “Introduction”.

CPU Subsystem

functions

Port functions The chapter “Port Functions” describes all input/output port related functions,

Interrupt functions Refer to the chapter “Interrupt Controller”.

The functions of the CPU Subsystem (including address map, operation modes, etc.) are described in the chapter “CPU System Function”. The section “Write protected Registers” in this chapter describes how to deal with registers, that feature special write protection facilities. If the microcontroller has separate bus systems beside the CPU Subsystem to connect certain functional modules, refer to the chapter “Bus Architecture”.

such as port sharing, I/O buffer control, port filters. The features and electrical properties of the I/O buffers are not subject to this manual, but are described in the "Electrical Target Specification".

Note that the function of each interrupt source is not described here, but in the related chapter of the module, that generates the interrupt.

DMA/DTS functions Refer to the chapter “DMA/DTS Controller” or “DMA Controller”, if the target

microcontroller does not feature DTS functions. Note that the function of each DMA/DTS trigger source is not described here, but in the related chapter of the module, that generates the trigger signal.

Flash memory For microcontrollers with on-chip flash memory refer to the chapter “Flash

Memory” for information about the flash memories structure and features, programming facilities, etc.

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How to use this manual

Stand-by functions How to set the microcontroller in stand-by modes and wake it up again is

described in the chapter “Stand-by Controller (STBC)”.

Code protection

and security

Clock supply The chapter “Clock Controller” describes the generation and operation of all

Resets The sources that can generate reset signals to all or dedicated internal

Functional modules The description of most functional modules, like timers, serial interfaces, etc. is

Debugging The main features on the On-Chip Debug Unit of the microcontroller is

Facilities to protect program code in on-chip flash memory (if available) from illegal read-out via external flash programming equipment or debuggers is described in the chapter “Code Protection and Security”.

clocks, provide to the entire microcontroller.

modules and how to control them is described in the chapter “Reset Controller”.

provided in separate chapters. These chapters have a certain structure of information presentation. Refer to the section “Functional modules descriptions”.

described in the chapter “On-chip Debug Unit (OCD)”. Note that the description of the external debugger tool is not subject to this manual.

Power supply The chapter “Power Supply” provides information which modules of the

microcontrollers are supplied by which external power supply pins. Note that the specification of the external power supply is not subject to this manual. Refer to the "Electrical Target Specification" for detailed definitions of the power supply.

Boundary scan If the target microcontroller supports boundary scan testing, refer to the

chapter “Boundary Scan” for information about available Boundary Scan features.

Notation of numbers and symbols

Symbols Symbols and notation are used as follows:

• Weight in data notation: Left is high order column, right is low order column

• Active low notation: xxx (pin or signal name is over-scored) or /xxx (slash before signal name)

• Memory map address: High order at high stage and low order at low stage

Numeric notation • Binary: xxxx or xxx

• Decimal: xxxx

• Hexadecimal: xxxxH or 0x xxxx

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How to use this manual

Numeric prefixes represent different factors, depending on the measure:

Prefix Powers of 2 Powers of 10

k (kilo) – 103 = 1000

K (Kilo) 210 = 1024 –

M (Mega) 220 = 10242 = 1,048,576 106 = 10002 = 1,000,000

G (Giga) 230 = 10243 = 1,073,741,824 109 = 10003 = 1,000,000,000

m (milli) – 10-3 = 0.001

µ (micro) – 10-6 = 0.0012 = 0.000,001

p (piko) – 10-9 = 0.0013 = 0.000,000,001

For example used for

• address and memory spaces in bytes: KB, MB, GB

For example used for

• frequencies: kHz, MHz, GHz

• times: ms, µs

• resistance: kΩ, MΩ

• capacitance: µF, pF

Diagrams

Block diagrams do not necessarily show the exact wiring in hardware but the functional structure.

Timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation.

Trademarks

All trademarks are the property of their respective owners.

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How to use this manual

Functional modules descriptions

Most of the chapters provide a technical description of a certain functional module.

These chapters are split into two parts:

• The first section describes all properties of the functional module specific to the target product of the user manual, such as instances, register base addresses, input/output signal names, etc.

• The subsequent sections describe the features of the functional module as a generic description. The generic description is common to all user manuals of products, that feature this module.

Functional modules abbreviation convention

Each functional module has a unique abbreviation, for instance

TAUA for the Timer Array Unit A

This shortcut is used in names for various purposes:

• The module registers and their bits names are preceded by this shortcut, for instance

TAUAnTS for the TAUAn channel start trigger register

The index “n” denotes the instance number of the module, refer to the next section and the key words “Instances” and “Instances index n”.

• The base address of the module registers include the by this shortcut, for instance

<TAUAn_base> for the base address of the TAUAn registers

• The input/output signals of the module are preceded by this shortcut, for instance

TAUAnTTIN0 for the TAUAn channel 0 input signal

• The names of the module interrupts includes the module shortcut, for instance

INTTAUAnI0 for the TAUAn channel 0 interrupt

Product specific features

The product specific section is always structured by a set of identical key words.

For the naming of signals product specific section serves also as some kind of interface between the generic module description and all other parts of the document. This means that the names of signals, used in the generic module description, may be translated to other names, that are used in the other document chapters. This name translation is given in form of tables, as the following as an example:

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Table 0-1 Example: Instances of TAUAn

Timer Array Unit A Device_1 Device_2 Device_3

Instance 2 4 2 Name TAUA0 to TAUA1 TAUA0 to TAUA3 TAUA0 to TAUA1

How to use this manual

Module signals Function Connected to

Module shortcut:

Name used in

generic module

description

The following lists the key words for product specific definitions. As examples, definitions of different modules are used.

Cautions 1. The following product specific definitions are only used as examples and do

not define any properties of the target product of this document.

2. Consequently the functional modules, used for examples purposes, may not

be available with the target product of this document.

Brief functional description Name used in remaining

document

Instances The devices of the target product may contain different numbers of the

functional module, so called instances. The “Instances” paragraph specifies the number of instances for all devices of the target product.

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Channel index m Timer Array Unit A has 16 channels. Throughout this chapter, the

individual channels are identified by the index “m” (m = 0 to 15), thus a certain channel is denoted as CHm. The even numbered channels (m = 0, 2, 4, 6, 8, 10, 12, 14) are denoted as CHm_even. The odd numbered channels (m = 1, 3, 5, 7 , 9, 11, 13, 15) are denoted as CHm_odd.

Table 0-2 Example: Register base addresses <TAUAn_base>

TAUAn instance <TAUAn_base> address

TAUA0 FF80 8000

TAUA1 FF80 9000

TAUA2 FF80 A000

TAUA3 FF80 B000

TAUA4 FF80 C000

How to use this manual

Instances index n Throughout the following generic module description, an instance of a module

is identified by the index "n", for instance

TAUAnTS for the TAUAn channel start trigger register

“n” counts from 0 to the number of instances minus one.

Other indices In case other indices, except “n” for instances, are used throughout the generic

module description, they are specified here.

offsets to a base address, that is individual to a certain module instance n. For each module instance n the individual base address is given here.

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Table 0-3 Example: TAUAn clock supply

TAUAn instance TAUAn clock Connected to

TAUA0 PCLK Clock Generator CKSCLK_006 TAUA1 PCLK Clock Generator CKSCLK_104 TAUA2 PCLK Clock Generator CKSCLK_111 TAUA3 PCLK Clock Generator CKSCLK_106 TAUA4 PCLK Clock Generator CKSCLK_105

Table 0-4 Example: TAUAn interrupt and DMA/DTS requests

TAUAn signals Function Connected to

TAUA0:

INTTAUA0I0 to

INTTAUA0I7

Channel 0 to 7 interrupt Interrupt Controller INTTAUA0I0

to INTTAUA0I7

INTTAUA0I8 Channel 8 interrupt Interrupt Controller INTTAUA0I8

DMA Controller trigger 15 DTS Controller trigger 9

INTTAUA0I9 to 15 Channels 9 to 14 interrupt not connected

TAUA1:

... ... ...

How to use this manual

Clock supply The clock signals of each instance n of the module and their connection to

other functional modules of the device are given here. A figure shows the modules clock supply options.

Interrupts and

DMA/DTS

The interrupt signals of each instance n of the module and their connections to other functional modules of the device are given here.

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Table 0-5 Example: VIn internal signals

VIn signal Function Connected to

VI0EN VIO0 enable VI0 I/F control ES_VSYNC VSYNC signal output MVO0 EVSYNC ES_HSYNC HSYNC signal output MVO0 EHSYNC

Table 0-6 Example: TAUAn reset signals

TAUAn Reset signal TAUA0 • Reset Controller SYSRES

• Reset upon Isolated-Area-0 wake-up from DEEPSTOP

mode

TAUA1 to TAUA4 • Reset Controller SYSRES

• Reset upon Isolated-Area-1 wake-up from DEEPSTOP mode

How to use this manual

Internal signals Signals of some modules are connected to other device’s modules. Such

connections are defined here.

H/W reset The signals, that reset each instance n of the module, are listed here.

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Table 0-7 Example: TAUAn I/O signals

TAUA signal Function Connected to

TAUA0:

TAUA0TTIN0 Channel 0 input Port TAUA0I0a or FCN0 TSOUT

or port URTE0RX

These input signals are passed through a noise filter, refer to the section “Port Filters” in the chapter “Port Functions”.

Refer to 15.2 “TAUA Input Selection” on page 662 for details.

TAUA0TTIN1 Channel 1 input Port TAUA0I1a or FCN1 TSOUT

or port URTE1RX

TAUA0TTIN2 to

TAUA0TTIN15

Channel 2 to 15 input Port TAUA0I2a to TAUA0I115

TAUA0TTOUT0 to

TAUA0TTOUT15

Channel 0 to 15 output Port TAUA0O0 to TAUA0O15

TAUA1:

... ... ...

How to use this manual

I/O signals The input/output signals of each instance n of the module and their

connections to ports and other functional modules of the device are given here.

Special definitions If the functional module needs any particular definitions for its operation, which

are product dependent, these are defined here.

Further information

For further information see http://www.renesas.com.

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Chapter 1 Introduction

1.1 V850E2/Fx4 Product Line Overview

1.1.1 V850E2/Fx4 products features

The following tables show the common and different features of various devices.

(1) V850E2/FG4 product series overview

Table 1-1 V850E2/FG4 product series overview (1/2)

Series name FG4-512K FG4-768K FG4-1M

Part number

Internal memory Instruction flash 512 KB 768 KB 1 MB

Data flash 32 KB RAM 48 KB 64 KB 80 KB Back-up RAM 4 KB 8 KB

CPU CPU System V850E2M

CPU frequency 80 MHz max. (+ 5 % with SSCG) System Protection Functions

(SPF)

Instruction cache 8 KB/2 way associative (4 KB/way) DMA 8 channels Operating clock Main Oscillator (MainOsc) 4 MHz to 20 MHz

Low Speed Internal Oscillator (LS IntOsc) 240 kHz typ.

High Speed Internal Oscillator (HS IntOsc) 8 MHz typ.

PLL0 (SSCG0) 80 MHz max. (+ 5 % with SSCG)

PLL1 80 MHz max.

PLL2 (SSCG2) • µPD70F3548 - µPD70F3550: –

I/O ports 72 A/D converter (ADCA) 20 channels, 12 bit, 6 S & H Timers Timer Array Unit A (TAUA), 16 bit 1 units x 16 channels

Timer Array Unit B (TAUB), 16 bit 1 units x 16 channels

Timer Array Unit J (TAUJ), 32 bit 2 units x 4 channels

Window Watchdog (WDTA) 2 channels

Operating System Timer (OSTM) 1 channel

Motor Control (TAPA) 1 channel

Encoder Timer (ENCA) 1 channel

MPU provided

SRP provided TSU provided

µPD70F3548 µPD70F4000

• µPD70F4000 - µPD70F4002:

80 MHz max. (+ 5 % with SSCG)

µPD70F3549 µPD70F4001

µPD70F3550 µPD70F4002

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Chapter 1 Introduction

Table 1-1 V850E2/FG4 product series overview (2/2)

Series name FG4-512K FG4-768K FG4-1M

Part number

Serial interfaces CAN I/F (FCN) 2 channels (64 messages buffer)

UART I/F (URTE) with LIN Master Controller (LM) 5 channels

Synchronous I/F (CSIG) 2 channels

Synchronous I/F (CSIH) 1 channel

I2C I/F (IICB) 1 channel

Flexray (FLX) • µPD70F3548 - µPD70F3550: –

External interrupts

Other functions Power-On-Clear (POC) provided

Voltage supply System supply 3.0 V to 5.5 V

Operating Temperature -40° C … +125° C Package 100-pin LQFP

Refer to the Data Sheet.

Maskable (INTPn) 12

Non-maskable (NMI) 1

Voltage Comparators (VCPC) 1 channel

Clock Monitors (CLMA) provided for MainOsc, HS IntOsc, PLL0

Random Number Generator (RNGA) 1 channel

Data CRC (DCRA) 1 channel

Key Return (KR) 8 channels

Wake-up signal output provided

Auxiliary frequency output (FOUT) provided

On-Chip debug (OCD) provided

Boundary Scan provided

Port supply 3.0 V to 5.5 V

µPD70F3548 µPD70F4000

• µPD70F4000 - µPD70F4002:

1 unit (2 channels)

µPD70F3549 µPD70F4001

supervision

µPD70F3550 µPD70F4002

a a

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PBUS

AWO:

TAUJ0 - TAUJ1

WDTA0

VCPC0 (1 chn.)

KR0

OSTM0

Iso1:

RNG0

DCRA0

CSIG0

FCN0 - FCN1 (2 x 64 msg. buf.)

IICB0

FLXA0

Note

CSIH2 (7 CS)

URTE/LMA2 URTE/LMA4

URTE/LMA10 URTE/LMA11

TAUB1

ADCA0 (20 chn.)

Iso0:

TAUA0

CSIG4

TAPA0

ENCA0

WDTA1

Power and Reset:

UARTA0

UARTA1

UARTA0

UARTA1

UARTA1UARTA1

AWO:

Reset

POC

Power

CPU Subsystem

CPU

DMA INTC

PBUS I/F

Iso0:

AWO:

STBC

On-Chip Debug:

AWO:

OCD

Note: Available on µPD70F4000 to µPD70F4002

Port groups P1 - P4, P10, P11

Port group P0, JP0

BURAM

Memory

Iso0:

Instruction flash

Data flash

RAM

Clock Generator:

AWO:

MainOsc

CLMA0

LS IntOsc FOUT

Iso0:

PLL0 (SSCG0)

CLMA3

PLL1

PLL2 (SSCG2)

Note

CLMA2

HS IntOsc

Clock Selectors CKSC_An

Clock Selectors CKSC_0n

Iso1:

Clock Selectors CKSC_1n

Chapter 1 Introduction

Figure 1-1 V850E2/FG4 block diagram

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Chapter 1 Introduction

(2) V850E2/FJ4 product series overview

Table 1-2 V850E2/FJ4 product series overview (1/2)

Series name FJ4-512K FJ4-768K FJ4-1M FJ4-1.5M

Part number

Internal memory Instruction flash 512 KB 768 KB 1 MB 1.5 MB

Data flash 32 KB 64 KB

RAM 48 KB 64 KB 80 KB 112 KB

Back-up RAM 4 KB 8 KB 16 KB CPU CPU System V850E2M

FPU – provided

CPU frequency 80 MHz max. (+ 5 % with SSCG)

System Protection

Functions (SPF)

Instruction cache 8 KB/2 way associative (4 KB/way) DMA 8 channels Operating clock Main Oscillator (MainOsc) 4 MHz to 20 MHz

Low Speed Internal Oscillator (LS

IntOsc)

High Speed Internal Oscillator (HS

IntOsc)

Sub Oscillator (SubOsc) 32768 Hz typ.

PLL0 (SSCG0) 80 MHz max. (+ 5 % with SSCG)

PLL1 80 MHz max.

PLL2 (SSCG2) • µPD70F3551 - µPD70F3554: –

I/O ports 112 A/D converter (ADCA) 24 channels, 12 bit, 6 S & H Timers Timer Array Unit A (TAUA), 16 bit 1 units x 16 channels

Timer Array Unit B (TAUB), 16 bit 1 units x 16 channels

Timer Array Unit C (TAUC), 16bit 4 units x 8 hannels

Timer Array Unit J (TAUJ), 32 bit 2 units x 4 channels

PWM Diagnosis (PMCA) 1 unit (40 channels)

PWM Delay (DLYA) 1 unit (40 channels)

Realtime Clock (RTCA) and

calibration

Window Watchdog (WDTA) 2 channels

Operating System Timer (OSTM) 1 channel

Motor Control (TAPA) 1 channel

Encoder Timer (ENCA) 1 channel

MPU provided

SRP provided TSU provided PPU – provided

µPD70F3551 µPD70F4003

• µPD70F4003- µPD70F4006:

80 MHz max. (+ 5 % with SSCG)

µPD70F3552 µPD70F4004

240 kHz typ.

8 MHz typ.

1 unit

µPD70F3553 µPD70F4005

µPD70F3554 µPD70F4006

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Chapter 1 Introduction

Table 1-2 V850E2/FJ4 product series overview (2/2)

Series name FJ4-512K FJ4-768K FJ4-1M FJ4-1.5M

Part number

Serial interfaces CAN I/F (FCN) 3 channels (64 messages buffer)

UART I/F (URTE) with LIN Master

Controller (LM)

Synchronous I/F (CSIG) 2 channels

Synchronous I/F (CSIH) 2 channels

I2C I/F (IICB) 1 channel

Flexray (FLX) • µPD70F3551 - µPD70F3554: –

External interrupts

Other functions Power-On-Clear (POC) provided

Voltage supply System supply 3.0 V to 5.5 V

Operating Temperature -40° C … +125° C Package 144-pin HLQFP

Refer to the Data Sheet.

Maskable (INTPn) 15

Non-maskable (NMI) 1

Voltage Comparators (VCPC) 2 channels

Clock Monitors (CLMA) provided for MainOsc, HS IntOsc, PLL0 supervision

Random Number Generator

(RNGA)

Data CRC (DCRA) 1 channel

Key Return (KR) 8 channels

Wake-up signal output provided

Auxiliary frequency output (FOUT) provided

On-Chip debug (OCD) provided

Boundary Scan provided

Port supply 3.0 V to 5.5 V

µPD70F3551 µPD70F4003

• µPD70F4003 - µPD70F4006:

1 unit (2 channels)

µPD70F3552 µPD70F4004

6 channels

1 channel

µPD70F3553 µPD70F4005

a a

µPD70F3554 µPD70F4006

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PBUS

AWO:

TAUJ0 - TAUJ1

WDTA0

VCPC0 (2 chn.)

RTCA0

KR0

URTE/LMA10 URTE/LMA11

OSTM0

Iso1:

RNG0CSIG0

FCN0 - FCN2 (3 x 64 msg. buf.)

IICB0

FLXA0

Note

PMCA0 (40 chn.)

DLYA0

CSIH0 & CSIH2 (8 + 6 CS)

URTE/LMA2 URTE/LMA5

TAUC0 - TAUC3

TAUB1

ADCA0 (24 chn.)

Iso0:

TAUA0

CSIG4

TAPA0

ENCA0

WDTA1

Power and Reset:

UARTA0

UARTA1

UARTA0

UARTA1

UARTA1UARTA1

AWO:

Reset

POC

Power

CPU Subsystem

CPU

DMA INTC

PBUS I/F

Iso0:

AWO:

STBC

On-Chip Debug:

AWO:

OCD

Note: Available on µPD70F4004 to µPD70F4006

FPU

Port groups P21, P25, P27

Port groups P1 - P4, P10, P11

Port group P0, JP0

Memory

Iso0:

Instruction flash

Data flash

RAM

BURAM

DCRA0

Clock Generator:

AWO:

MainOsc

CLMA0

LS IntOsc FOUT

Iso0:

PLL0 (SSCG0)

CLMA3

PLL1

PLL2 (SSCG2)

Note

CLMA2

HS IntOsc

Clock Selectors CKSC_An

Clock Selectors CKSC_0n

Iso1:

Clock Selectors CKSC_1n

SubOsc

Chapter 1 Introduction

R01UH0076ED0103 Rev. 1.03 45

Figure 1-2 V850E2/FJ4 block diagram

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Chapter 1 Introduction

(3) V850E2/FK4 product series overview

Table 1-3 V850E2/FK4 product series overview (1/2)

Series name FK4-768K FK4-1M FK4-1.5M FK4-2M

Part number

Internal memory Instruction flash 768 KB 1 MB 1.5 MB 2 MB

Data flash 32 KB 64 KB

RAM 64 KB 80 KB 112 KB 144 KB

Back-up RAM 8 KB 16 KB External memory interface (MEMC) provided CPU CPU System V850E2M

FPU – provided

CPU frequency 80 MHz max. (+ 5 % with SSCG)

System Protection

Functions (SPF)

Instruction cache 8 KB/2 way associative (4 KB/way) DMA 8 channels Operating clock Main Oscillator (MainOsc) 4 MHz to 20 MHz

Low Speed Internal Oscillator (LS

IntOsc)

High Speed Internal Oscillator (HS

IntOsc)

Sub Oscillator (SubOsc) 32768 Hz typ.

PLL0 (SSCG0) 80 MHz max. (+ 5% with SSCG)

PLL1 80 MHz max.

PLL2 (SSCG2) • µPD70F3555 - µPD70F3558: –

I/O ports 137 A/D converter (ADCA) 1 x 24 channels, 1 x 16 channels, 12 bit, 6 S & H Timers Timer Array Unit A (TAUA), 16 bit 1 units x 16 channels

Timer Array Unit B (TAUB), 16 bit 1 units x 16 channels

Timer Array Unit C (TAUC), 16 bit 5 units x 8 channels

Timer Array Unit J (TAUJ), 32 bit 2 units x 4 channels

PWM Diagnosis (PMCA) 1 unit (48 channels)

PWM Delay (DLYA) 1 unit (48 channels)

Realtime Clock (RTCA) and

calibration

Window Watchdog (WDTA) 2 channels

Operating System Timer (OSTM) 1 channel

Motor Control (TAPA) 1 channel

Encoder Timer (ENCA) 1 channel

MPU provided provided

SRP provided provided TSU provided provided PPU – provided

µPD70F3555 µPD70F4007

• µPD70F4007 - µPD70F4010:

80 MHz max. (+ 5 % with SSCG)

µPD70F3556 µPD70F4008

240 kHz typ.

8 MHz typ.

1 unit

µPD70F3557 µPD70F4009

µPD70F3558 µPD70F4010

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Chapter 1 Introduction

Table 1-3 V850E2/FK4 product series overview (2/2)

Series name FK4-768K FK4-1M FK4-1.5M FK4-2M

Part number

Serial interfaces CAN I/F (FCN) 3 channels (64 messages buffer)

UART I/F (URTE) with LIN Master

Controller (LM)

Synchronous I/F (CSIG) 2 channels

Synchronous I/F (CSIH) 3 channels

I2C I/F (IICB) 1 channel

Flexray (FLX) • µPD70F3555 - µPD70F3558: –

External interrupts

Other functions Power-On-Clear (POC) provided

Voltage supply System supply 3.0 V to 5.5 V

Operating Temperature -40° C … +125° C Package 176-pin HLQFP

Refer to the Data Sheet.

Maskable (INTPn) 16

Non-maskable (NMI) 1

Voltage Comparators (VCPC) 2 channels

Clock Monitors (CLMA) provided for MainOsc, HS IntOsc, PLL0 supervision

Random Number Generator

(RNGA)

Data CRC (DCRA) 1 channel

Key Return (KR) 8 channels

Wake-up signal output provided

Auxiliary frequency output (FOUT) provided

On-Chip debug (OCD) provided

Boundary Scan provided

Port supply 3.0 V to 5.5 V

µPD70F3555 µPD70F4007

• µPD70F4007 - µPD70F4010: 1 unit (2 channels)

µPD70F3556 µPD70F4008

1 channel (128 messages buffer)

µPD70F3557 µPD70F4009

8 channels

1 channel

µPD70F3558 µPD70F4010

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PBUS

AWO:

TAUJ0 - TAUJ1

WDTA0

VCPC0 (2 chn.)

RTCA0

KR0

URTE/LMA10 URTE/LMA11

ADCA0 (24 chn.)

Iso0:

TAUA0

CSIG4

TAPA0

ENCA0

WDTA1

Power and Reset:

UARTA0

UARTA1

UARTA0

UARTA1

UARTA1UARTA1

AWO:

Reset

POC

Power

CPU Subsystem

CPU

DMA INTC

PBUS I/F

Iso0:

AWO:

STBC

Iso0:

MEMC

On-Chip Debug:

AWO:

OCD

Note: Available on µPD70F4007 to µPD70F4010

FPU

OSTM0

Iso1:

RNG0CSIG0

FCN0 - FCN3 (2 x 64, 1 x 128 msg. buf.)

IICB0

FLXA0

Note

ADCA1 (16 chn.)

PMCA0 (48 chn)

DLYA0

CSIH0 - CSIH2 (8 + 8 + 8 CS)

URTE/LMA2 URTE/LMA7

TAUC2 - TAUC6

TAUB1

Port groups P12, P21, P24, P25, P27

Port groups P1 - P4, P10, P11

Port group P0, JP0

Memory

Iso0:

Instruction flash

Data flash

RAM

BURAM

DCRA0

Clock Generator:

AWO:

MainOsc

CLMA0

LS IntOsc FOUT

Iso0:

PLL0 (SSCG0)

CLMA3

PLL1

PLL2 (SSCG2)

Note

CLMA2

HS IntOsc

Clock Selectors CKSC_An

Clock Selectors CKSC_0n

Iso1:

Clock Selectors CKSC_1n

SubOsc

Chapter 1 Introduction

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Figure 1-3 V850E2/FK4 block diagram

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Chapter 1 Introduction

(4) V850E2/FL4 product series overview

Table 1-4 V850E2/FL4 product series overview (1/2)

Product series FL4-1.5M FL4-2M

Part number

Internal memory Instruction flash 1.5 MB 2 MB

Data flash 64 KB RAM 112 KB 144 KB

Back-up RAM 16 KB External memory interface (MEMC) provided CPU CPU System V850E2M

FPU provided

CPU frequency 80 MHz max.

System Protection Functions (SPF) MPU provided

SRP provided TSU provided PPU provided

Instruction cache 8 KB/2 way associative (4 KB/way) DMA 8 channels Operating clock Main Oscillator (MainOsc) 4 MHz to 20 MHz

Low Speed Internal Oscillator (LS IntOsc) 240 kHz typ.

High Speed Internal Oscillator (HS IntOsc) 8 MHz typ.

Sub Oscillator (SubOsc) 32768 Hz typ.

PLL0 (SSCG0) 80 MHz max. (+ 5% with SSCG)

PLL1 80 MHz max.

PLL2 (SSCG2) • µPD70F3559 - µPD70F3560: –

I/O ports 164 A/D converter (ADCA) 2 x 24 channels, 12 bit,

Timers Timer Array Unit A (TAUA), 16 bit 1 units x 16 channels

Timer Array Unit B (TAUB), 16 bit 1 units x 16 channels

Timer Array Unit C (TAUC), 16 bit 6 units x 8 channels

Timer Array Unit J (TAUJ), 32 bit 2 units x 4 channels

PWM Diagnosis (PMCA) 1 unit (56 channels)

PWM Delay (DLYA) 1 unit (56 channels)

Realtime Clock (RTCA) and calibration 1 unit

Window Watchdog (WDTA) 2 channels

Operating System Timer (OSTM) 1 channel

Motor Control (TAPA) 1 channel

Encoder Timer (ENCA) 1 channel

µPD70F3559 µPD70F4011

(+ 5% with SSCG)

• µPD70F4011 - µPD70F4012: 80 MHz max. (+ 5 % with SSCG)

6 S & H

µPD70F3560 µPD70F4012

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Chapter 1 Introduction

Table 1-4 V850E2/FL4 product series overview (2/2)

Product series FL4-1.5M FL4-2M

Part number

Serial interfaces CAN I/F (FCN) 3 channels (64 messages buffer)

Diagnostic CAN I/F (DCN) 1 channel (128 messages buffer) UART I/F (URTE) with LIN Master Controller (LM) 12 channels Synchronous I/F (CSIG) 2 channels Synchronous I/F (CSIH) 3 channels I2C I/F (IICB) 1 channel Flexray (FLX) • µPD70F3559 - µPD70F3560: –

External interrupts

Other functions Power-On-Clear (POC) provided

Voltage supply System supply 3.0 V to 5.5 V

Operating Temperature -40° C … +125° C Package 208-pin QFP

Refer to the Data Sheet.

Maskable (INTPn) 16 Non-maskable (NMI) 1

Voltage Comparators (VCPC) 2 channels Clock Monitors (CLMA) provided for MainOsc, HS IntOsc, PLL0

Random Number Generator (RNGA) 1 channel Data CRC (DCRA) 1 channel Key Return (KR) 8 channels Wake-up signal output provided Auxiliary frequency output (FOUT) provided On-Chip debug (OCD) provided Boundary Scan provided

Port supply 3.0 V to 5.5 V

µPD70F3559 µPD70F4011

1 channel (128 messages buffer)

• µPD70F4011 - µPD70F4012: 1 unit (2 channels)

supervision

µPD70F3560 µPD70F4012

a a

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PBUS

AWO:

TAUJ0 - TAUJ1

WDTA0

VCPC0 (2 chn.)

RTCA0

KR0

URTE/LMA10 URTE/LMA11

Iso0:

TAUA0

CSIG4

TAPA0

ENCA0

WDTA1

ADCA0 (24 chn.)

Power and Reset:

UARTA0

UARTA1

UARTA0

UARTA1

UARTA1UARTA1

AWO:

Reset

POC

Power

CPU Subsystem

CPU

DMA INTC

PBUS I/F

Iso0:

AWO:

STBC

Iso0:

MEMC

On-Chip Debug:

AWO:

OCD

Note: Available on µPD70F4011 to µPD70F4012

FPU

Port groups P12, P13, P21, P24, P25, P27, P28

Port groups P1 - P4, P10, P11

Port group P0, JP0

OSTM0

Iso1:

RNG0CSIG0

FCN0 - FCN3 (2 x 64, 1 x 128 msg. buf.)

IICB0

DCN0 (128 msg. buf)

FLXA0

Note

ADCA1 (24 chn.)

PMCA0 (56 chn.)

DLYA0

CSIH0 - CSIH2 (8 + 8 + 8 CS)

URTE/LMA0 URTE/LMA9

TAUC2 - TAUC7

TAUB1

Memory

Iso0:

Instruction flash

Data flash

RAM

BURAM

DCRA0

Clock Generator:

AWO:

MainOsc

CLMA0

LS IntOsc FOUT

Iso0:

PLL0 (SSCG0)

CLMA3

PLL1

PLL2 (SSCG2)

Note

CLMA2

HS IntOsc

Clock Selectors CKSC_An

Clock Selectors CKSC_0n

Iso1:

Clock Selectors CKSC_1n

SubOsc

Chapter 1 Introduction

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Figure 1-4 V850E2/FL4 block diagram

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Chapter 1 Introduction

1.2 Related Documents

Table 1-5 Related documents

Document number

R01US0001EJxxxx User’s Manual:

EASE-DS-0030-x.x Data Sheet V850E2/FG4 EASE-DS-0031-x.x Data Sheet V850E2/FJ4 EASE-DS-0029-x.x Data Sheet V850E2/FK4 EASE-DS-0027-x.x Data Sheet V850E2/FL4 R20UT0008EJxxxx User’s Manual:

U17638EJxVxUM00 User’s Manual:

U20281EExVxUM00 User’s Manual:

U20279EExVxUM00 User’s Manual:

“x” denotes the current document revision numbers.

V850E2M 32-bit Microcontroller Core Architecture

PG-FP5 Flash Memory Programmer

QB-V850MINI, QB-V850MINIL On-Chip Debug Emulator

Flash Self-programming Library FSL - T05

Data Flash Access Library FDL - T05

Title

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Chapter 1 Introduction

1.3 Ordering Information

Table 1-6 V850E2/Fx4 ordering information

Series name Part number Renesas order code Remarks

FG4-512K µPD70F3548 UPD70F3548MxGC(Ax)-UEU-AX

µPD70F4000 UPD70F4000MxGC(Ax)-UEU-AX µPD70F3548 with Flexray

FG4-768K µPD70F3549 UPD70F3549MxGC(Ax)-UEU-AX

µPD70F4001 UPD70F4001MxGC(Ax)-UEU-AX µPD70F3549 with Flexray

FG4-1M µPD70F3550 UPD70F3550MxGC(Ax)-UEU-AX

µPD70F4002 UPD70F4002MxGC(Ax)-UEU-AX µPD70F3550 with Flexray

FJ4-512K µPD70F3551 UPD70F3551MxGJ(Ax)-GBG-AX

µPD70F4003 UPD70F4003MxGJ(Ax)-GBG-AX µPD70F3551 with Flexray

FJ4-768K µPD70F3552 UPD70F3552MxGJ(Ax)-GBG-AX

µPD70F4004 UPD70F4004MxGJ(Ax)-GBG-AX µPD70F3552 with Flexray

FJ4-1M µPD70F3553 UPD70F3553MxGJ(Ax)-GBG-AX

µPD70F4005 UPD70F4005MxGJ(Ax)-GBG-AX µPD70F3553 with Flexray

FJ4-1.5M µPD70F3554 UPD70F3554MxGJ(Ax)-GBG-AX

µPD70F4006 UPD70F4006MxGJ(Ax)-GBG-AX µPD70F3554 with Flexray

FK4-768K µPD70F3555 UPD70F3555MxGM(Ax)-GBK-AX

µPD70F4007 UPD70F4007MxGM(Ax)-GBK-AX µPD70F3555 with Flexray

FK4-1M µPD70F3556 UPD70F3556MxGM(Ax)-GBK-AX

µPD70F4008 UPD70F4008MxGM(Ax)-GBK-AX µPD70F3556 with Flexray

FK4-1.5M µPD70F3557 UPD70F3557MxGM(Ax)-GBK-AX

µPD70F4009 UPD70F4009MxGM(Ax)-GBK-AX µPD70F3557 with Flexray

FK4-2M µPD70F3558 UPD70F3558MxGM(Ax)-GBK-AX

µPD70F4010 UPD70F4010MxGM(Ax)-GBK-AX µPD70F3558 with Flexray

FL4-1.5M µPD70F3559 UPD70F3559MxGD(Ax)-FAD-AX

µPD70F4011 UPD70F4011MxGD(Ax)-FAD-AX µPD70F3560 with Flexray

FL4-2M µPD70F3560 UPD70F3560MxGD(Ax)-FAD-AX

µPD70F4012 UPD70F4012MxGD(Ax)-FAD-AX µPD70F3560 with Flexray

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Chapter 1 Introduction

1.4 Product Name Register

Several product information can be read via the product name register PRDNAME:

• product number: identifies the device of the V850E2/Fx4 product series

• product version: revision number of the device

(1) PRDNAME - Product name register

This register holds the product information.

Access This register can be read in 32-bit units.

Address FF47 0028

Initial Value 00xx xxxx xxxx xxx 0000 xxxx xxxx xxxx

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 0 PRDNUM[13:0]

R R R R R R R R R R R R R R R R

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R R R R R R R R R R R R R R R R

Table 1-7 PRDNAME register contents

Bit position Bit name Function

29 to 16 PRD

NUM[13:0]

Product number

0DDCH: µPD70F3548 0DDDH: µPD70F3549 0DDEH: µPD70F3550 0DDFH: µPD70F3551 0DE0H: µPD70F3552 0DE1H: µPD70F3553 0DE2H: µPD70F3554 0DE3H: µPD70F3555 0DE4H: µPD70F3556 0DE5H: µPD70F3557 0DE6H: µPD70F3558 0DE7H: µPD70F3559 0DE8H: µPD70F3560

0FA0H: µPD70F4000 0FA1H: µPD70F4001 0FA2H: µPD70F4002 0FA3H: µPD70F4003 0FA4H: µPD70F4004 0FA5H: µPD70F4005 0FA6H: µPD70F4006 0FA7H: µPD70F4007 0FA8H: µPD70F4008 0FA9H: µPD70F4009 0FAAH: µPD70F4010 0FABH: µPD70F4011 0FACH: µPD70F4012

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Chapter 2 Port Functions

This chapter contains a generic description of the Port control functions. The first section describes all properties specific to the V850E2/Fx4, such as

port groups, register base addresses, etc. The second section describes the features of the port control functions that

apply to all ports. The third section summarizes the individual functions of all pins of V850E2/Fx4

microcontrollers. Finally the function of analog and digital filters, which are implemented at some

pins, are described.

2.1 V850E2/Fx4 Port Features

Port groups The V850E2/Fx4 microcontrollers have following number of port groups:

Table 2-1 Port groups of V850E2/Fx4

Port groups

Number 7 11 12 14 Names P0, P1, P3, P4, P10,

Port groups index n Throughout this chapter, the individual port groups are identified by the index

V850E2/FG4 V850E2/FJ4 V850E2/FK4 V850E2/FL4

P0 to P4, P10, P11,

P11, JP0

“n”, for example, PMCn for the port mode control register of Pn.

from the individual base addresses <PORTn_base> and <JPORT0_base>. The base addresses <PORTn_base> and <JPORT0_base> are specified in the following table:

Table 2-2 Port base addresses <PORTn_base> and <JPORT0_base>

P21, P25, P27, JP0

<PORTn_base> address <JPORT0_base> address

FF40 0000

P0 to P4, P10 to P12,

P21, P25, P27, JP0

P0 to P4, P10 to P13,

P21, P24, P25, P27,

FF44 0000

JP0

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Chapter 2 Port Functions

2.2 Overview

The microcontroller has various pins for input/output functions, known as ports. The ports are organized in port groups.

The microcontroller also has several control registers to allocate other than general purpose input/output functions to the pins.

For a description of the terms pin, port, or port group, see the following section “Terms”.

Features summary • Configuration possible for individual pins.

• The following features can be selected for most of the pins: – One out of four input buffer characteristics – Output current limit – Open drain emulation

– Pull-up or pull-down resistor connection

• The following registers are offered for most of the ports: – Direct register for reading the pin values – Port register

– Port set/reset register – Register for output inversion

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Chapter 2 Port Functions

2.2.1 Terms

In this chapter, the following terms are used:

• Pin

Denotes the physical pin. Every pin is denoted by a unique pin number. The pin numbers depend on the package and are given in the Data Sheet.

Most of the pins can be used in several modes. Thus the pin name depends on the selected mode.

• Port group

Denotes a group of ports. The ports of a port group have a common set of port mode control registers.

• Port mode / Port

A pin in port mode works as a general purpose input/output pin. It is then called “port”.

The corresponding name is Pn_m. For example, P0_7 denotes port 7 of port group 0. It is referenced as “port P0_7”.

• Alternative mode

In alternative mode, a pin can be used for various non-general purpose input/output functions, for example as the input/output pin of on-chip peripherals.

The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs.

Note that two different names can refer to the same physical pin, for example P0_0 and INTP0. The different names indicate the function in which the pin is being operated.

JTAG ports The JTAG port group JP0 is used for connecting the debugger for on-chip

debugging purposes. Therefore it present a special port group, as the ports of JP0 are not available for application purposes during a debug session. During normal operation, i.e. without debugger, the JP0 ports can be used in the same way as all others.

The JTAG port group JP0 control registers and their control bits have the same names as the other port groups, registers and bits, but are identified by a “J” prefix.

Note Throughout this chapter the description of all ports and their registers apply

also to the JTAG ports, unless otherwise noted.

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Chapter 2 Port Functions

2.2.2 Pin function configuration

The pins can operate in three different general modes:

• Port mode (PMCn.PMCn_m = 0) In port mode the pin operates as a general purpose I/O port. PMn.PMn_m selects input or output.

• S/W I/O control alternative mode (PMCn.PMCn_m = 1, PIPCn.PIPCn_m = 0) In S/W I/O control alternative mode the pin is operated by an alternative function. The selection between input or output is done by S/W via the PMn.PMn_m control bits.

• Direct I/O control alternative mode (PMCn.PMCn_m = 1, PIPCn.PIPCn_m = 1) In direct I/O control alternative mode the pin is operated by an alternative function. In contrast to the S/W I/O control alternative mode the input/output control is also handled by the alternative function, thus the S/W doesn’t have to care about.

An overview of the register settings is given in the tables below.

Table 2-3 Pin function configuration (overview)

Mode

Port 0 0 X O

S/W I/O control alternative 1 0 0 O

Direct I/O control alternative X 1 controlled by

The input buffer must be enabled (PIBCn.PIBCn_m = 1)

If a pin is operated in an alternative mode (PMCn.PMCn_m = 1), one out of up to four different alternative functions can be selected by the PFCn and PFCEn registers.

Selection of one of the alternative input and output functions:

• S/W I/O control alternative functions (PIPCn.PIPCn_m = 0): – outputs (PMn_m = 0): ALT-OUT1 to ALT-OUT4 – inputs (PMn_m = 1): ALT-IN1 to ALT-IN4

PMCn_m PMn_m PIPCn_m

Control bits

1 0 I

I/O

alternative function

• Direct I/O control alternative functions (PIPCn.PIPCn_m = 1): – input/out of ALT-OUT1 to ALT-OUT4 and ALT-IN1 to ALT-IN4 is directly

controlled by the alternative function

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Chapter 2 Port Functions

Table 2-4 Alternative mode selection overview (PMCn.PMCn_m = 1)

Function

Alternative output mode 1 (ALT-OUT1) 0 0 0 0 O Alternative input mode 1 (ALT-IN1) 1 I Alternative output mode 2 (ALT-OUT2) 0 0 1 O Alternative input mode 2 (ALT-IN2) 1 I Alternative output mode 3 (ALT-OUT3) 0 1 0 O Alternative input mode 3 (ALT-IN3) 1 I Alternative output mode 4 (ALT-OUT4) 0 1 1 O Alternative input mode 4 (ALT-IN4) 1 I

If PIPCn.PIPCn_m = 1, the I/O direction is directly controlled by the alternative function and PM is ignored.

Caution In case a certain alternative input function is available via multiple ports, only

one port must be configured to use this alternative input function. All other ports must be configured to use other signals.

PMn/PMCn

The port mode register PMn and port mode control register PMCn can be manipulated in two different ways:

PIPC

Registers

PMaPFCE PFC

I/O

• Direct PMn/PMCn write New value can be written directly to the PMn/PMCn register.

• Indirect PMn/PMCn bit set/reset An indirect way to set or reset a PMn/PMCn bit is possible by using following registers:

– Port mode set reset register PMSRn

If the bit PMSRn.PMSRn(m+16) = 1, the value of bit PMSRn.PMSRn_m determines the value of PMn.PMn_m. Thus PMn_m can be set/reset without a direct write to PMn.

– Port mode control set reset register PMCSRn

If the bit PMCSRn.PMCSRn(m+16) = 1, the value of bit PMCSRn.PMCSRn_m determines the value of PMCn.PMn_m. Thus PMn_m can be set/reset without a direct write to PMCn.

The indirect PMn/PMCn set/reset operation provides access to single bits of the PMn/PMCn register, while leaving all other register bits untouched.

Both ways to manipulate a PMn/PMCn bit can be used concurrently.

Note It is recommended to use the indirect PMn/PMCn bit set/reset method for

changing a single bit or concurrently several bits of the PMn/PMCn register, since all other bits are not modified and can be independently treated by other S/W modules, for instance in interrupt service routines.

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Chapter 2 Port Functions

2.2.3 Pin data input/output

In the following the registers are described, used for data input and output. Depending on the pin mode, the source of the data to be output and the data

read via the PPRn register differs.

Output data In port mode (PMCn.PMCn_m = 0) the data of Pn.Pn_m is output to pin Pn_m.

In alternative mode (PMCn.PMCn_m = 1) the pin Pn_m output is determined by the alternative function.

Input data A read operation of the PPRn register returns either the value of the Pn_m pin,

the associated bit of the port register Pn.Pn_m or the data output by an alternative function.

The source of the data read via PPRn depends on the pin mode and the setting of several control bits.

The table below summarizes the different PPRn read modes.

Note PBDCn_m is not included in the table, as it can be set to 1 for reading the

Pn_m pin level in all modes.

Table 2-5 PPRn_m read values

PMC n_mPMn_m

0 1 0 X X Port input, input buffer disabled Pn.Pn_m register

1 1 X 0 X S/W I/O control alternative input Pn_m pin

If PBDCn_m = 1, Pn_m pin level is read via PPRn_m.

PIBC

n_m

0 X 0 Port push-pull output Pn.Pn_m register

0 0 S/W I/O control alternative

X 1 0 Direct I/O control alternative

PIPC

n_m

1 X Port input, input buffer enabled Pn_m pin

PODC

n_m

1 Port open-drain output

push-pull output

1 S/W I/O control alternative

open-drain output

input/ push-pull output

1 Direct I/O control alternative

input/ open-drain output

Mode PPRn_m read value

Alternative function output

If alternative functions sets port in

• input: PPRn_m = Pn_m pin

• output: PPRn_m = alternative

function output

The control registers in the table above have following effects:

• PBDCn.PBDCn_m (see table footnote) This bit forces to read the Pn_m pin level via PPRn_m, thus enabling a bidirectional mode, where the level of pin Pn_m can also be read back if the port is operated in an output mode.

• PMCn.PMCn_m This bit selects port mode (PMCn_m = 0) or alternative mode (PMCn_m = 1).

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• PMn.PMn_m This bit selects input (PMn_m = 1) or output (PMn_m = 0) in port mode (PMCn_m = 0) and S/W I/O control alternative function mode (PMCn_m = 1, PIPCn_m = 0).

• PIBCn.PIBCn_m This bit disables (PIBCn_m = 0) or enables (PIBCn_m = 1) the input buffer in input port mode (PMCn_m = 0 and PMn_m = 1). If the input buffer is disabled, PPRn_m reads the Pn.Pn_m bit, otherwise the Pn_m pin level is returned.

• PIPCn.PIPCn_m This bit selects between the S/W and direct I/O control alternative mode.

• PODCn.PODCn_m This bit selects between push-pull (PODCn_m = 0) and open-drain (PODCn_m = 1) output.

Pn register write The data to be output via port Pn_m in port mode (PMCn.PMCn_m = 0) is held

in the port register Pn. The Pn data can be manipulated in two different ways:

• Direct Pn write New data can be written directly to the Pn register.

• Indirect Pn bit set/reset/not An indirect way to set (Pn_m = 1), reset (Pn_m = 0), or invert (Pn_m→Pn_m) a Pn bit is possible using two registers:

– Port set reset register PSRn

If the bit PSRn.PSRn(m+16) = 1, the value of bit PSRn.PSRn_m determines the value of Pn.Pn_m. Thus Pn_m can be set/reset without a direct write to Pn.

– Port NOT register PNOTn

Setting PNOTn.PNOTn_m = 1 inverts the bit Pn.Pn_m without a direct write to Pn_m.

The indirect Pn set/reset/not operation provides access to single bits of the Pn register, while leaving all other Pn bits untouched.

Both ways to manipulate a Pn bit can be used concurrently.

Note It is recommended to use the indirect Pn bit set/reset/not method for changing

a single bit or concurrently several bits of the Pn register, since all other bits are not modified and can independently be treated by other S/W modules, for instance in interrupt service routines.

Caution If a port Pn_m

• provides an alternative output ALT_OUTx and input function ALT_INx

• and is used in alternative output mode ALT_OUTx (PMCn.PMCn_m = 1, PMn.PMn_m = 0)

• and the bi-directional mode is enabled (PBDCn.PBDCn_m = 1) for reading the Pn_m level via PPRn.PPRn_m,

the Pn_m output, i.e. of ALT_OUTx, is internally fed back to the alternative input function ALT_INx.

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PBDC

PBDCn_m

PMn_m

PMSRn_m

PIBC

PIBCn_m

PMC

PMCn_m

PMCSRn_m

PSR

Pn_m

PSRn_m

PPR

PPRn_m

PFC

PFCn_m

PFCE

PFCEn_m

PUn_m

PDn_m

PODC

PODCn_m

PIS

PISn_m

PISE

PISEn_m

ALT_OUT

control

PUON

PDON

ENO

DIN

DOUT

I/O Buffer

ALT_IN

control

ISE

1 234 1 234

0 1 0 1

0 0 1 1

PNOTn_m

PIPC

PIPCn_m

ENI

Chapter 2 Port Functions

2.2.4 Port control logic diagram

The following diagram shows the logical circuitry of the port control functions.

Note The diagram is only a logical reference and does not show the real circuitry.

Figure 2-1 Port control logic diagram

The signals to the I/O buffer in the diagram above have the following general function:

Buffer control signal General function

DS port drive strength control IS, ISE input buffer selection PUON/PDON pull-up/-down register control ENO/ENI output/input buffer enable DIN/DOUT port data in/out

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Chapter 2 Port Functions

2.3 Port Group Configuration Registers

This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are grouped as follows:

• “Pin function configuration registers”

• “Pin data input/output”

• “Configuration of electrical characteristics registers”

2.3.1 Writing to protected registers

Write protected registers are protected from inadvertent write access due to erroneous program execution, etc.

Following port registers feature this special write protection:

• Port drive strength control registers PDSCn, JPDSC0

• Port open drain control registers PODCn, JPODC0

Refer to the section “Write protected Registers” in the chapter “CPU System Functions” for a detailed description how to write to write protected registers.

2.3.2 Port control registers overview

The following registers are used for the configuration of the individual pins of the port groups:

Note Some of the registers, listed in the table below, are not available for all port

groups n. Refer to the section “V850E2/Fx4Port Group Configuration” below for information which registers are available for the individual port groups.

Table 2-6 Registers for port group configuration (1/2)

Port mode control register PMCn <PORTn_base> + 0400H + n x 4

Port mode control set reset

Port IP control register PIPCn <PORTn_base> + 4200H + n x 4 Port mode register PMn <PORTn_base> + 0300H + n x 4

Port mode set reset register PMSRn <PORTn_base> + 0800H + n x 4

Port input buffer control register PIBCn <PORTn_base> + 4000H + n x 4

Port function control register PFCn <PORTn_base> + 0500H + n x 4

JPMC0 <JPORT0_base> + 0040 PMCSRn <PORTn_base> + 0900H + n x 4 JPMCSR0 <JPORT0_base> + 0090

JPM0 <JPORT0_base> + 0030

JPMSR0 <JPORT0_base> + 0080

JPIBC0 <JPORT0_base> + 0400

JPFC0 <JPORT0_base> + 0050

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Table 2-6 Registers for port group configuration (2/2)

Port function control expansion

Data input/output:

Port bi-direction control register PBDCn <PORTn_base> + 4100H + n x 4

Port pin read register PPRn <PORTn_base> + 0200H + n x 4

Port register Pn <PORTn_base> + 0000H + n x 4

Port NOT register PNOT0 <PORTn_base> + 0700H + n x 4

Port set reset register PSRn <PORTn_base> + 0100H + n x 4

Configuration of electrical characteristics:

Pull-up option register PUn <PORTn_base> + 4300H + n x 4

Pull-down option register PDn <PORTn_base> + 4400H + n x 4

Port drive strength control

Port open drain control register PODCn <PORTn_base> + 4500H + n x 4

Port input buffer selection

expansion register

PFCEn <PORTn_base> + 0600H + n x 4 JPFCE0 <JPORT0_base> + 0060

JPBDC0 <JPORT0_base> + 0410

JPPR0 <JPORT0_base> + 0020

JP0 <JPORT0_base> + 0000

JPNOT0 <JPORT0_base> + 0070

JPSR0 <JPORT0_base> + 0010

JPU0 <JPORT0_base> + 0430

JPD0 <JPORT0_base> + 0440 PDSCn <PORTn_base> + 4600H + n x 4 JPDSC0 <JPORT0_base> + 0460

JPODC0 <JPORT0_base> + 0450 PISn <PORTn_base> + 4700H + n x 4 JPIS0 <JPORT0_base> + 0470 PISEn <PORTn_base> + 4800H + n x 4 JPISE0 <JPORT0_base> + 0480

<PORTn_base> The base address <PORTn_base> of the port contorl registers is defined in

the first section of this chapter under the key word “Register addresses”.

JTAG port registers The following register descriptions do not explicitely reference the JTAG port

registers. However all description apply also to the respective JTAG port registers, but the base address of the JTAG port registers is different:

<JPORT0_base> The base addresses <JPORT0_base> of the JTAG port control registers is

defined in the first section of this chapter under the key word “Register addresses”.

Initial register

values

The initial values after reset release depend on the port, and are not described in the following register descriptions, but are given in the section “V850E2/Fx4 Port Groups Configuration”.

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2.3.3 Port function configuration registers

(1) PMCn/JPMC0 - Port mode control register

This register specifies whether the individual pins of port group n are in port mode or in alternative mode.

Access PMCn: This register can be read/written in 16-bit units.

JPMC0: This register can be read/written in 8-bit units.

Address PMCn: <PORTn_base> + 0400H + n x 4

JPMC0: <JPORT0_base> + 0040

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

Note The control bits of the JTAG port register JPMC0 are named JPMC0_[7:0].

PMC

n_7

PMC

n_6

PMC

n_5

PMC

n_4

PMC

n_3

PMC

n_2

PMC

n_1

PMC

n_0

Table 2-7 PMCn/JPMC0 register contents

Bit position Bit name Function

15 to 0 PMC

n_[15:0]

Specifies the operation mode of the corresponding pin:

0: Port mode 1: Alternative mode

Cautions 1. Setting PMCn.PMCn_m = 1 to use a port in alternative mode does not hand

over I/O control to the alternative function. If the alternative function requires direct I/O control, PIPCn.PIPCn_m must also be set to 1.

2. Setting PMCn.PMCn_m = 1 to use a port in alternative mode may also

require to configure a port filter, if this port is used as a signal input. The input signal may be passed through a noise filter, that may need to be configured. Refer to the section “Port Filters” in this chapter.

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(2) PMCSRn/JPMCSR0 - Port mode control set reset register

This register provides an alternative method to write data to the PMCn register. The register’s upper 16 bit PMCSRn_[31:16] specify which PMCn.PMCn_m bit

will be modified by the corresponding bit of the lower 16 bit PMCSRn_[15:0].

Access These registers can be read/written in 32-bit units.

Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register PMCn/JPMC0.

Address PMCSRn: <PORTn_base> + 0900H + n x 4

JPMCSR0: <JPORT0_base> + 0090

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PMCSR

n_31

n_30

n_29

n_28

n_27

n_26

n_25

n_24

n_23

n_22

n_21

n_20

n_19

n_18

n_17

n_16

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMCSR

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPMCSR0 are named

JPMCSR0_[31:0].

Table 2-8 PMCSRn/JPMCSR0 register contents

Bit position Bit name Function

31 to 16 PMCSR

n_[31:16]

15 to 0 PMCSR

n_[15:0]

PMCSRn_m specifies whether the value of the corresponding lower bit PMCSRn_m value is written to PMCn_m:

0: PMCn_m is independent of PMCSRn_m

1: PMCn_m is PMCSRn_m Example: If PMCSRn.PMCSRn_31 = 1, the value of bit PMCSRn.PMCSRn_15 is written to bit PMCn.PMCn_15 and output.

Specifies the PMCn_m value if the corresponding upper bit PMCSRn_(m+16) is 1:

0: PMCn_m = 0

1: PMCn_m = 1

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(3) PIPCn - Port IP control register

This register specifies whether the I/O direction of pin Pn_m is controlled by the port mode register PMn.PMn_m or by an alternative function.

If pin Pn_m is operated in alternative mode (PMCn.PMCn_m = 1) and the alternative function requires to directly control the I/O direction of Pn_m, PIPCn.PIPCn_m must be set to 1 as well. This hands over I/O control to the alternative function and overrules the PMn.PMn_m setting.

Access PIPCn: This register can be read/written in 16-bit units.

Address PIPCn: <PORTn_base> + 4200H + n x 4

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIPC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Table 2-9 PIPCn register contents

Bit position Bit name Function

15 to 0 PIPC

n_[15:0]

Specifies the I/O control mode:

0: I/O mode is selected by PMn.PMn_m (S/W I/O control)

1: I/O mode is selected by peripheral function

(direct I/O control)

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(4) PMn/JPM0 - Port mode register

The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode.

Access PMn: This register can be read/written in 16-bit units.

JPM0: This register can be read/written in 8-bit units.

Address PMn: <PORTn_base> + 0300H + n x 4

JPM0: <JPORT0_base> + 0030

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

n_15PMn_14PMn_13PMn_12PMn_11PMn_10PMn_9PMn_8PMn_7PMn_6PMn_5PMn_4PMn_3PMn_2PMn_1PMn_0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note The control bits of the JTAG port register JPM0 are named JPM0_[7:0].

Table 2-10 PMn/JPM0 register contents

Bit position Bit name Function

15 to 0 PM

n_[15:0]

Specifies input/output mode of the corresponding pin:

0: Output mode (output enabled)

1: Input mode (output disabled)

Notes 1. To use a port in input port mode (PMCn.PMCn_m = 0 and

PMn.PMn_m = 1), the input buffer must be enabled (PIBCn.PIBCn_m = 1).

2. By default, PMn_m specifies the I/O direction in port mode

(PMCn.PMCn_m = 0) and alternative mode (PMCn.PMCn_m=1), since PIPCn.PIPCn_m = 0 after reset.

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(5) PMSRn/JPMSR0 - Port mode set reset register

This register provides an alternative method to write data to the PMn register. The register’s upper 16 bit PMSRn_[31:16] specify which PMn.PMn_m bit will

be modified by the corresponding bit of the lower 16 bit PMSRn_[15:0].

Access These registers can be read/written in 32-bit units.

Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register PMn/JPM0.

Address PMSRn: <PORTn_base> + 0800H + n x 4

JPMSR0: <JPORT0_base> + 0080

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PMSR

n_31

n_30

n_29

n_28

n_27

n_26

n_25

n_24

n_23

n_22

n_21

n_20

n_19

n_18

n_17

n_16

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMSR

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPMSR0 are named JPMSR0_[31:0].

Table 2-11 PMSRn/JPMSR0 register contents

Bit position Bit name Function

31 to 16 PMSR

n_[31:16]

15 to 0 PMSR

n_[15:0]

PMSRn_m specifies whether the value of the corresponding lower bit PMSRn_m value is written to PMn_m:

0: PMn_m is independent of PMSRn_m

1: PMn_m is PMSRn_m Example: If PMSRn.PMSRn_31 = 1, the value of bit PMSRn.PMSRn_15 is written to bit PMn.PMn_15 and output.

Specifies the PMn_m value if the corresponding upper bit PMSRn_(m+16) is 1:

0: PMn_m = 0

1: PMn_m = 1

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(6) PIBCn/JPIBC0 - Port input buffer control register

In input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1) this register enables/disables the port pin’s input buffer.

Access PIBCn: This register can be read/written in 16-bit units.

JPIBC0: This register can be read/written in 8-bit units.

Address PIBCn: <PORTn_base> + 4000H + n x 4

JPIBC0: <JPORT0_base> + 0400

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIBC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPIBC0 are named JPIBC0_[7:0].

Table 2-12 PIBCn/JPIBC0 register contents

Bit position Bit name Function

15 to 0 PIBC

n_[15:0]

Enables/disables the input buffer:

0: Input buffer disabled

1: Input buffer enabled

Note When the input buffer is disabled, it does not consume current even when the

pin level is Hi-Z state. Thus the pin does not need to be fixed to a high or low level externally.

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(7) PFCn/JPFC0 - Port function control register

This register, together with register PFCEn, specifies an alternative function of the pins.

Some alternative functions require direct I/O control of pin Pn_m. For such alternative functions PIPCn.PIPCn_m must be set to 1 as well. For other alternative functions, input/output must be specified by PMn.PMn_m.

Access PFCn: This register can be read/written in 16-bit units.

JPFC0: This register can be read/written in 8-bit units.

Address PFCn: <PORTn_base> + 0500H + n x 4

JPFC0: <JPORT0_base> + 0050

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PFC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPFC0 are named JPFC0_[7:0].

Table 2-13 PFCn/JPFC0 register contents

Bit position Bit name Function

15 to 0 PFC

n_[15:0]

Specifies the alternative function of a pin. See Table 2-4 “Alternative mode selection overview (PMCn.PMCn_m = 1)” on page 59 for details.

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(8) PFCEn/JPFCE0 - Port function control expansion register

This register, together with register PFCn, specifies an alternative function of the pins.

Access PFCEn: This register can be read/written in 16-bit units.

JPFCE0: This register can be read/written in 8-bit units.

Address PFCEn: <PORTn_base> + 0600H + n x 4

JPFCE0: <JPORT0_base> + 0060

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PFCE

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPFCE0 are named JPFCE0_[7:0].

Table 2-14 PFCEn/JPFCE0 register contents

Bit position Bit name Function

15 to 0 PFCE

n_[15:0]

Specifies the alternative function of a pin. See Table 2-4 “Alternative mode selection overview (PMCn.PMCn_m = 1)” on page 59 for details.

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2.3.4 Data input/output registers

(1) PBDCn/JPBDC0 - Port bi-direction control register

This register enables the input buffer of Pn_m, if its output buffer is enabled as well. Thus the concerned port Pn_m is operated in bi-directional mode and the Pn_m pin level is read via PPRn.PPRn_m.

Note If Pn_m is not configured as output, the input buffer can not be activated via

the PBDCn/JPBDCn register.

Access PBDCn: This register can be read/written in 16-bit units.

JPBDC0: This register can be read/written in 8-bit units.

Address PBDCn: <PORTn_base> + 4100H + n x 4

JPBDC0: <JPORT0_base> + 0410

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PBDC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

PBDC

n_6

PBDC

n_5

PBDC

n_4

PBDC

n_3

PBDC

n_2

PBDC

n_1

PBDC

n_0

Note The control bits of the JTAG port register JPBDC0 are named JPBDC0_[7:0].

Table 2-15 PBDCn/JPBDC0 register contents

Bit position Bit name Function

15 to 0 PBDC

n_[15:0]

Enables/disables bi-directional mode of the corresponding pin:

0: Bi-directional mode disabled

1: Bi-directional mode enabled

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(2) PPRn/JPPR0 - Port pin read register

This register reflects the actual level of pin Pn_m, the value of the Pn.Pn_m bit or the level of an alternative output function. The value which is read depends on various control settings as described in Table 2-5 “PPRn_m read values” on page 60 .

Access PPRn: This register can be read/written in 16-bit units.

JPPR0: This register can be read/written in 8-bit units.

Address PPRn: <PORTn_base> + 0200H + n x 4

JPPR0: <JPORT0_base> + 0020

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPR

n_15

n_14

n_13

n_12

n_11

n_10

R R R R R R R R R R R R R R R R

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPPR0 are named JPPR0_[7:0].

Table 2-16 PPRn/JPPR0 register contents

Bit position Bit name Function

15 to 0 PPR

n_[15:0]

Pin Pn_m, Pn.Pn_m value or alternative function output.

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(3) Pn/JP0 - Port register

This register holds the data Pn.Pn_m to be output via the related port Pn_m in output port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 0).

Access Pn: This register can be read/written in 16-bit units.

JP0: This register can be read/written in 8-bit units.

Address Pn: <PORTn_base> + 0000H + n x 4

JP0: <JPORT0_base> + 0000

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

n_15Pn_14Pn_13Pn_12Pn_11Pn_10Pn_9Pn_8Pn_7Pn_6Pn_5Pn_4Pn_3Pn_2Pn_1Pn_0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note The control bits of the JTAG port register JP0 are named JP0_[7:0].

Table 2-17 Pn/JP0 register contents

Bit position Bit name Function

15 to 0 P

n_[15:0]

Sets the output level of pin m (m = 0 to 15):

0: Outputs low level

1: Outputs high level

Note The bits of this register can be manipulated by different means, refer to 2.2.3

“Pin data input/output” on page 60 under the keyword “Pn register write”.

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(4) PNOTn/JPNOT0 - Port NOT register

This register allows to invert a bit Pn_m of the port register Pn without directly writing to Pn.

Access PNOTn: This register can be read/written in 16-bit units.

JPNOT0: This register can be read/written in 8-bit units. These registers are always read as 0000H.

Address PNOTn: <PORTn_base> + 0700H + n x 4

JPNOT0: <JPORT0_base> + 0070

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PNOT

n_15

n_14

n_13

n_12

n_11

n_10

W W W W W W W W W W W W W W W W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPNOT0 are named JPNOT0_[7:0].

Table 2-18 PNOTn/JPNOT0 register contents

Bit position Bit name Function

15 to 0 PNOT

n_[15:0]

Specifies if Pn.Pn_m is inverted:

0: Pn.Pn_m is not inverted (Pn_m → Pn_m)

1: Pn.Pn_m is inverted (Pn_m → Pn_m)

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(5) PSRn/JPSR0 - Port set reset register

This register provides an alternative method to write data to the Pn register. The register’s upper 16 bit PSRn_[31:16] specify which Pn.Mn_m bit will be

modified by the corresponding bit of the lower 16 bit PSRn_[15:0].

Access These registers can be read/written in 32-bit units.

Bits 31 to 16 are always read as 0000H. Reading bits 15 to 0 returns the value of register Pn/JP0.

Address PSRn: <PORTn_base> + 0100H + n x 4

JPSR0: <JPORT0_base> + 0010

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PSR

n_31

n_30

n_29

n_28

n_27

n_26

n_25

n_24

n_23

n_22

n_21

n_20

n_19

n_18

n_17

n_16

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PSR

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPSR0 are named JPSR0_[31:0].

Table 2-19 PSRn/JPSR0 register contents

Bit position Bit name Function

31 to 16 PSR

n_[31:16]

15 to 0 PSR

n_[15:0]

PSRn_m specifies whether the value of the corresponding lower bit PSRn_m value is written to Pn_m:

0: Pn_m is independent of PSRn_m

1: Pn_m is PSRn_m Example: If PSRn.PSRn31 = 1, the value of bit PSRn.PSRn_15 is written to bit Pn.Pn_15 and output.

Specifies the Pn_m value if the corresponding upper bit PSRn_(m+16) is 1:

0: Pn_m = 0

1: Pn_m = 1

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2.3.5 Configuration of electrical characteristics registers

(1) PUn/JPU0 - Pull-up option register

This register specifies whether a pull-up resistor is connected to an input pin.

Access PUn: This register can be read/written in 16-bit units.

JPU0: This register can be read/written in 8-bit units.

Address PUn: <PORTn_base> + 4300H + n x 4

JPU0: <JPORT0_base> + 0430

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

n_15PUn_14PUn_13PUn_12PUn_11PUn_10PUn_9PUn_8PUn_7PUn_6PUn_5PUn_4PUn_3PUn_2PUn_1PUn_0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note The control bits of the JTAG port register JPU0 are named JPU0_[7:0].

Table 2-20 PUn/JPU0 register contents

Bit position Bit name Function

15 to 0 PU

n_[15:0]

Notes 1. If a pin is configured that both a pull-up resistor (PUn.PUn_m = 1) and a

Specifies whether a pull-up resistor is connected to the corresponding pin:

0: No pull-up resistor connected

1: Pull-up resistor connected

pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected.

2. The pull-up resistor has no effect when the pin is operated in output mode.

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(2) PDn/JPD0 - Pull-down option register

This register specifies whether a pull-down resistor is connected to an input pin.

Access PDn: This register can be read/written in 16-bit units.

JPD0: This register can be read/written in 8-bit units.

Address PDn: <PORTn_base> + 4400H + n x 4

JPD0: <JPORT0_base> + 0440

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

n_15PDn_14PDn_13PDn_12PDn_11PDn_10PDn_9PDn_8PDn_7PDn_6PDn_5PDn_4PDn_3PDn_2PDn_1PDn_0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note The control bits of the JTAG port register JPD0 are named JPD0_[7:0].

Table 2-21 PDn/JPD0 register contents

Bit position Bit name Function

15 to 0 PD

n_[15:0]

Specifies whether a pull-down resistor is connected to the corresponding pin:

0: No pull-down resistor connected

1: Pull-down resistor connected

Notes 1. If a pin is configured that both a pull-up resistor (PUn.PUn_m = 1) and a

pull-down resistor (PDn.PDn_m = 1) are connected, the pull-down resistor is automatically selected and the pull-up resistor is not connected.

2. The pull-down resistor has no effect when the pin is operated in output

mode.

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(3) PDSCn/JPDSC0 - Port drive strength control register

This register enables the driver strength control function.

Protection Writing to this register is protected by a special sequence of instructions.

Refer to the section “Write protected Registers” in the chapter “CPU System Functions” for a detailed description how to write to write protected registers.

Access These registers can be read/written in 32-bit units.

The bits 31 to 16 must always be written with “0” and “0” is returned when read.

Address PDSCn: <PORTn_base> + 4600H + n x 4

JPDSC0: <JPORT0_base> + 0460

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDSC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPDSC0 are named JPDSC0_[31:0].

Table 2-22 PDSCn/JPDSC0 register contents

Bit position Bit name Function

15 to 0 PDSC

n_[15:0]

Enables/disables output current limiting function:

0: Current limitation enabled

1: Current limitation disabled

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(4) PODCn/JPODC0 - Port open drain control register

This register selects push-pull or open-drain as output buffer function.

Protection Writing to this register is protected by a special sequence of instructions.

Refer to the section “Write protected Registers” in the chapter “CPU System Functions” for a detailed description how to write to write protected registers.

Access These registers can be read/written in 32-bit units.

The bits 31 to 16 must always be written with “0” and “0” is returned when read.

Address PODCn: <PORTn_base> + 4500H + n x 4

JPODC0: <JPORT0_base> + 0450

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PODC

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPODC0 are named JPODC0_[31:0].

Table 2-23 PODCn/JPODC0 register contents

Bit position Bit name Function

15 to 0 PODC

n_[15:0]

Specifies the output buffer function:

0: Push-pull

1: Open-drain

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(5) PISn/JPIS0 - Port input buffer selection register

This register specifies the input buffer characteristics. A port can have up to four different input buffer characteristics.

The type of input characteristic is selected by the

• port input buffer selection register PISn

• port input buffer selection expansion register PISEn

Table 2-24 Port input buffer characteristic selection

PISEn_m PISn_m Input buffer characteristic

0 0 CMOS (type 1)

1 Schmitt2 (type 2)

1 0 Schmitt1 (type 3)

1 Schmitt4 (type 4)

Refer to the Data Sheet for electrical characteristics of the different types and which types are available for each port.

Access PISn: This register can be read/written in 16-bit units.

JPIS0: This register can be read/written in 8-bit units.

Address PISn: <PORTn_base> + 4700H + n x 4

JPIS0: <JPORT0_base> + 0470

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

PIS n_8

PIS n_7

PIS n_6

PIS n_5

PIS n_4

PIS

n_3

PIS n_2

PIS n_1

PIS n_0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIS

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

Note The control bits of the JTAG port register JPIS0 are named JPIS0_[7:0].

Table 2-25 PISn/JPIS0 register contents

Bit position Bit name Function

15 to 0 PIS

n_[15:0]

Specifies the input buffer characteristic of port m (m = 0 to 15) together with the bits PISEn[15:0].

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(6) PISEn/JPISE0 - Port input buffer selection expansion register

This register specifies the input buffer characteristics together with the port input selection register PISn.

If a port has up to five input buffer characteristics, the port input selection advanced register PISAn is also valid.

Access PISEn: This register can be read/written in 16-bit units.

JPISE0: This register can be read/written in 8-bit units.

Address PISEn: <PORTn_base> + 4800H + n x 4

JPISE0: <JPORT0_base> + 0480

Initial Value Refer to the section “V850E2/Fx4 Port Groups Configuration”.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PISE

n_15

n_14

n_13

n_12

n_11

n_10

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

n_9

n_8

n_7

n_6

n_5

n_4

n_3

n_2

n_1

n_0

Note The control bits of the JTAG port register JPISE0 are named JPISE0_[7:0].

Table 2-26 PISEn/JPISE0 register contents

Bit position Bit name Function

15 to 0 PISE

n_[15:0]

Specifies the input buffer characteristic of port m (m = 0 to 15) together with the bits PISn[15:0]. Refer to the PISn register description for how to select the input buffer characteristic.

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2.4 V850E2/Fx4 Port Group Configuration

This section provides

• an overview of the port register protection clusters, refer to the section “Port

registers protection clusters”

• general information for all ports , refer to the section “Common port functions”

• details of all port groups and their associated control registers for each device, refer to the sections

– “V850E2/FG4 port functions” – “V850E2/FJ4 port functions” – “V850E2/FK4 port functions” – “V850E2/FL4 port functions”

• a list of input/output signals with port functionality, refer to the section “Nonport input/putput signals”

• an alphabetic pin functions list and the ports, the functions can be assigned to, refer to the section “Alphabetic pin function list”

• a description of the port status during and after reset and in stand-by modes, refer to the section “Port functions during/after reset and in stand-by

modes”

• recommendations concerning unused pins, refer to the section “Recommended connection of unused pins”.

2.4.1 Port register protection clusters

Several registers of certain port groups n are bundled in port protection clusters:

Table 2-27 Port protection clusters

Port protection cluster Port groups

1 JP0 2 P0 3 P1 to P4, P10, P11 4 P12, P13, P21, P24, P25, P27

For further information concerning port register protection refer to the section “Write protected Registers” in the chapter “CPU System Functions” for a detailed description how to write to write protected registers.

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2.4.2 Common port functions

This section provides information about special port functions, common to all devices.

(1) Initialization of port control registers

The port control registers are initialized by the following reset signals:

Table 2-28 Port control registers reset signals

Port group Power domain Reset signal

JP0, P0, P5 Always-On-Area • Reset Controller: SYSRES P1 to P4, P10, P11 Isolated-Area-0 • Reset Controller: SYSRES

• Stand-by Controller: DPSTPWU_0 (Isolated-Area-0 wake-up from DEEPSTOP mode)

P12, P13, P21, P22, P24 to P29

Isolated-Area-1 • Reset Controller: SYSRES

• Stand-by Controller: DPSTPWU_1 (Isolated-Area-1 wake-up from DEEPSTOP mode)

(2) P0_0: RESETOUT

After reset release P0_0 outputs a RESETOUT signal, which is low level during and after reset release. P0_0 is configured as follows after reset release:

• PM0.PM0_0 = 0: port output

• PODC0.PODC0_0 = 1: open-drain output Since P0.P0_0 = 0 after reset, low level is output. Any change of the P0_0 configuration terminates the RESETOUT output.

Note Since the RESETOUT signal is activated by all reset events, thus also when an

internal reset is applied, it can be used for reset of external devices.

Caution Once asserted the RESETOUT remains on low level. It must be de-asserted

by changing the port configuration of P0_0 after reset release.

(3) JP_0 to JP_5: Debug interface

If the debug reset DCUTRST is at high level at reset release, the port of the JP0 port group are used for the debugger interface:

• JP0_0: DCUTDI input

• JP0_1: DCUTDO output

• JP0_2: DCUTCK input

• JP0_3: DCUTMS

• JP0_4: DCUTRST

• JP0_5: DCUTRDY Consequently all port and alternative modes on these pins can not be used

while the debugger is connected.

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Refer to the chapter “On-chip Debug Unit (OCD)” and the section “Operation Modes” of chapter “CPU System Functions” for details.

Note In order to connect the debugger via the JP0 pins the flash mask option

OPBT0.OPBT0[31] has to be set to 1.

(4) JP0_0, JP0_1, JP0_2: Flash programmer

These ports are used for connecting a flash programmer. Refer to the chapter “Flash Memory” and the section “Operation Modes” of

chapter “CPU System Functions” for details.

(5) Mode pins

Following ports are used as mode setting signals in combination with the FLMD0 pin:

• P0_1: FLMD1

• P0_2: MODE0

• P0_3: MODE1 Refer to the section “Operation Modes” of chapter “CPU System Functions” for

details.

(6) Permanent inputs

Permanent input means, that the input to a port is unconditionally connected to another module. Thus settings of the port control registers do not impact this connection.

Following ports are permanently connected to dedicated function modules:

Table 2-29 Permanent input functions

Port

P10_6 ADCA0I6 P11_4 ADCA0I20 P12_10 ADCA1I10 P10_7 ADCA0I7 P11_5 ADCA0I21 P12_11 ADCA1I11 P10_8 ADCA0I8 P11_6 ADCA0I22 P12_12 ADCA1I12

P10_9 ADCA0I9 P11_7 ADCA0I23 P12_13 ADCA1I13 P10_10 ADCA0I10 P12_0 ADCA1I0 P12_14 ADCA1I14 P10_11 ADCA0I11 P12_1 ADCA1I1 P12_15 ADCA1I15 P10_12 ADCA0I12 P12_2 ADCA1I2 P13_0 ADCA1I16 P10_13 ADCA0I13 P12_3 ADCA1I3 P13_1 ADCA1I17 P10_14 ADCA0I14 P12_4 ADCA1I4 P13_2 ADCA1I18 P10_15 ADCA0I15 P12_5 ADCA1I5 P13_3 ADCA1I19

P11_0 ADCA0I16 P12_6 ADCA1I6 P13_4 ADCA1I20

P11_1 ADCA0I17 P12_7 ADCA1I7 P13_5 ADCA1I21

P11_2 ADCA0I18 P12_8 ADCA1I8 P13_6 ADCA1I22

P11_3 ADCA0I19 P12_9 ADCA1I9 P13_7 ADCA1I23

Permanent

input to

Port

Permanent

input to

Port

Permanent

input to

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Notes 1. If the ports of the port groups P10 to P13 shall be used in input port mode,

set

• ADCA0CTL1.ADCA0GPS = 1 to use P10 or P11 in input port mode

• ADCA1CTL1.ADCA1GPS = 1 to use P12 or P13 in input port mode

2. The input pins of the ADCA0 simultaneous sampling channels ADCA0I0 to

ADCA0I5 do not provide port functionality.

(7) Direct I/O control (PIPC)

Some modules take over the input and output control of the used ports automatically. These ports have to be set in alternative mode by setting PMCn.PMCn_m, PFCn.PFCn_m and PFCEn.PFCEn_m accordingly and I/O control has to be handed over to the module by setting

PIPCn.PIPCn_m = 1. The setting of PMn.PMn_m has no more effect for these ports. The following table lists all alternative modes, where PIPCn.PIPCn_m has to

be set to 1. Note that not all functions in the table below are available for all devices.

Table 2-30 Alternative modes with PIPCn.PIPCn_m = 1 (1/2)

Port Function Alternative mode

Clocked Serial Interfaces G (CSIG):

P0_14 CSIG0SO ALT_OUT4 P0_15 CSIG0SC ALT_IN4/ALT_OUT4

P4_4 CSIG0SO ALT_OUT2 P4_5 CSIG0SC ALT_IN2/ALT_OUT2 P0_1 CSIG4SO ALT_OUT2 P0_3 CSIG4SC ALT_IN2/ALT_OUT2 P3_6 CSIG4SO ALT_OUT4 P3_5 CSIG4SC ALT_IN4/ALT_OUT4 P4_7 CSIG4SO ALT_OUT2

P4_8 CSIG4SC ALT_IN2/ALT_OUT2 P25_4 CSIG4SO ALT_OUT3 P25_5 CSIG4SC ALT_IN3/ALT_OUT3

Clocked Serial Interfaces H (CSIH):

P4_1 CSIH0SO ALT_OUT3

P4_2 CSIH0SC ALT_IN3/ALT_OUT3

P1_8 CSIH1SO ALT_OUT3

P1_9 CSIH1SC ALT_IN3/ALT_OUT3

P1_3 CSIH2SO ALT_OUT4

P1_4 CSIH2SC ALT_IN4/ALT_OUT4 P21_3 CSIH2SO ALT_OUT2 P21_2 CSIH2SC ALT_IN2/ALT_OUT2

External Memory Controller (MEMC):

P25_0 MEMC0AD0 ALT_IN1/ALT_OUT1

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Table 2-30 Alternative modes with PIPCn.PIPCn_m = 1 (2/2)

Port Function Alternative mode

P25_1 MEMC0AD1 ALT_IN1/ALT_OUT1 P25_2 MEMC0AD2 ALT_IN1/ALT_OUT1 P25_3 MEMC0AD3 ALT_IN1/ALT_OUT1 P25_4 MEMC0AD4 ALT_IN1/ALT_OUT1 P25_5 MEMC0AD5 ALT_IN1/ALT_OUT1 P25_6 MEMC0AD6 ALT_IN1/ALT_OUT1 P25_7 MEMC0AD7 ALT_IN1/ALT_OUT1 P25_8 MEMC0AD8 ALT_IN1/ALT_OUT1 P25_9 MEMC0AD9 ALT_IN1/ALT_OUT1

P25_10 MEMC0AD10 ALT_IN1/ALT_OUT1 P25_11 MEMC0AD11 ALT_IN1/ALT_OUT1 P25_12 MEMC0AD12 ALT_IN1/ALT_OUT1 P25_13 MEMC0AD13 ALT_IN1/ALT_OUT1 P25_14 MEMC0AD14 ALT_IN1/ALT_OUT1 P25_15 MEMC0AD15 ALT_IN1/ALT_OUT1

P27_0 MEMC0A16 ALT_OUT1 P27_1 MEMC0A17 ALT_OUT1 P27_2 MEMC0A18 ALT_OUT1 P27_5 MEMC0ASTB ALT_OUT2

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2.4.3 V850E2/FG4 port functions

This section summarizes all port functions of the V850E2/FG4 devices and its port control registers.

(1) V850E2/FG4 general I/O functions

The table below shows all alternative functions, that can be applied to the V850E2/FG4 ports. It also gives the settings of the control bits PMCn_m, PFCn_m, PFCEn_m and PMn_m to the respective port into the different modes.

Table 2-31 V850E2/FG4 general I/O functions (1/3)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

Port group 0 (Always-On-Area, E0VDD/E0VSS power supply):

P0_0 TAUJ1I0 TAUJ1O0 CSIG4SSI ADCA0TRG0 INTP0 P0_1 TAUJ1I1 TAUJ1O1 CSIG4SOaURTE2RX INTP1 TAUA0O1 P0_2 TAUJ1I2 TAUJ1O2 CSIG4SI ADCA0TRG2 URTE2TX INTP2 TAUA0O2 P0_3 TAUJ1I3 TAUJ1O3 CSIG4SC

P0_4 FCN0TX INTP11 P0_5 FCN0RX INTP12 P0_6 FCN1RX URTE11TX KR0I1 CSIH2CSS1 NMI P0_7 URTE11RX FCN1TX KR0I2 CSIH2CSS2 INTP4 P0_8 URTE10TX KR0I3 CSIH2CSS3 INTP5 TAUA0O5 IICB0SDA

P0_9 URTE10RX KR0I4 CSIH2CSS4 INTP6 TAUA0O6 IICB0SCL P0_12 TAUJ0I0 TAUJ0O0 KR0I0 INTP8 CSIG0SSI CSCXFOUT P0_13 TAUJ0I1 TAUJ0O1 KR0I5 CSIH2CSS5 INTP7 CSIG0SI P0_14 TAUJ0I2 TAUJ0O2 KR0I6 CSIH2CSS6 TAUB1O13 CSIG0SO P0_15 TAUJ0I3 TAUJ0O3 KR0I7 CSIH2CSS7 TAUB1O14 CSIG0SC

Port group 1 (Isolated-Area-0, E1VDD/E1VSS power supply):

P1_1 TAUA0I1 TAUA0O1 ENCA0AIN FCN1RX FCN0TX

P1_2 TAUA0I2 TAUA0O2 ENCA0BIN TAPA0UP CSIH2SI FCN1TX

P1_3 TAUA0I3 TAUA0O3 ENCA0ZIN TAPA0UN CSIH2SO

P1_4 TAUA0I4 TAUA0O4 ENCA0TIN0 TAPA0VP CSIH2SC

P1_5 TAUA0I5 TAUA0O5 ENCA0TIN1 TAPA0VN CSIH2RY

P1_6 TAUA0I6 TAUA0O6 TAPA0WP CSIH2SSI CSIH2CSS0

P1_7 TAUA0I7 TAUA0O7 TAPA0WN FCN0RX CSIH2CSS1

P1_8 TAUA0I8 TAUA0O8 URTE4TX

P1_9 TAUA0I9 TAUA0O9 INTP3 FLX0TXENA URTE4RX P1_10 TAUA0I10 TAUA0O10 FLX0RXDA URTE3TX INTP4

Alternative mode

PMCn_m = 1

ADCA0TRG1 INTP3/

TAPA0ESO

b b

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Chapter 2 Port Functions

Table 2-31 V850E2/FG4 general I/O functions (2/3)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

P1_11 TAUA0I11 TAUA0O11 URTE3RX FLX0TXDA INTP5 P1_12 TAUA0I12 TAUA0O12 FLX0RXDB URTE4TX INTP6 P1_13 TAUA0I13 TAUA0O13 URTE4RX FLX0TXDB INTP7 P1_14 TAUA0I14 TAUA0O14 FLX0STPWT INTP8 P1_15 TAUA0I15 TAUA0O15 FLX0TXENB INTP9

Port group 3 (Isolated-Area-0, E1VDD/E1VSS power supply):

P3_2 TAUA0I2 TAUA0O2 KR0I7

P3_3 TAUA0I3 TAUA0O3 KR0I6

P3_4 TAUA0I4 TAUA0O4 KR0I5 CSIG0RY

P3_5 TAUA0I5 TAUA0O5 KR0I4 CSIG0SC

P3_6 TAUA0I6 TAUA0O6 CSIG0SO

P3_7 TAUA0I7 TAUA0O7 CSIG0SI URTE3TX

Port group 4 (Isolated-Area-0, E1VDD/E1VSS power supply):

P4_0

P4_1 TAUB1I2 TAUB1O2 TAUA0I14 TAUA0O14 URTE2RX

P4_2 TAUB1I3 TAUB1O3 TAUA0I15 TAUA0O15 URTE2TX

P4_3 TAUB1I5 TAUB1O5 CSIG0SI URTE10TX INTP10

P4_4 INTP2 TAUB1O6 URTE10RX CSIG0SO

P4_5 TAUB1I7 TAUB1O7 CSIG0SC

P4_6 TAUB1I9 TAUB1O9 CSIG4SI URTE11TX KR0I2 ENCA0AIN

P4_7 INTP4 TAUB1O10 URTE11RX CSIG4SO

P4_8 TAUB1I11 TAUB1O11 CSIG4SC

P4_9 TAUB1I13 TAUB1O13 CSIG0RY P4_10 TAUB1I14 TAUB1O14 CSIG4RY

Port group 10 (Isolated-Area-0, A0VDD/A0VSS power supply):

P10_6 P10_7 P10_8 P10_9 ADCA0TRG0

P10_10 ADCA0TRG1 P10_11 ADCA0TRG2 P10_12 P10_13 P10_14 P10_15

TAUB1I1 TAUB1O1 TAUA0I13 TAUA0O13

Alternative mode

PMCn_m = 1

ENCA0TIN0

KR0I3 ENCA0TIN1

KR0I1 ENCA0BIN KR0I0 ENCA0ZIN

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Chapter 2 Port Functions

Table 2-31 V850E2/FG4 general I/O functions (3/3)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

Port group 11 (Isolated-Area-0, A0VDD/A0VSS power supply):

P11_0 P11_1 P11_2 P11_3

Port group JP0 (Always-On-Area, E0VDD/E0VSS power supply):

JP0_0 INTP0 TAUJ0I0 TAUJ0O0 JP0_1 INTP1 VCPC0OUT TAUJ0I1 TAUJ0O1 JP0_2 INTP2 CSCXFOUT TAUJ0I2 TAUJ0O2 JP0_3 INTP3 TAUJ0I3 TAUJ0O3 JP0_4 JP0_5 NMI

When using this alternative mode, set PIPCn.PIPCn_m = 1. The module controls the I/O setting and PMn_m has no effect.

Refer to the section “I2C Interface Port Settings” in the “I2C Interface (IICB)” chapter for details about the correct configuration of the I2C Interface ports.

Port P4_0 is not available for V850E2/FG4-M2 devices.

The ports of port groups 10 and 11 are also used as permanent inputs to the A/D Converter ADCA0. If the P10 or P11 ports shall be used as port inputs, set ADCA0CTL1.ADCA0GPS = 1.

JP0_0 to JP0_2 are used during flash programming. JP0_0 to JP0_5 are used during debugging. Refer to the section “Common port functions” above for details.

Alternative mode

PMCn_m = 1

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Chapter 2 Port Functions

(2) V850E2/FG4 port control registers

The following table summarizes all V850E2/FJ4 port control registers, their addresses and intitial values.

Tables legend A: Register address

I: Initial value B: Available bits

- 1: available, x: not available

- right: bit 0, left: bit 15

Table 2-32 V850E2/FG4 port (groups 0, 1, 3, 4) control registers (1/2)

PSRn

PNOTn

PPRn

PMn

PMCn

PFCn

PFCEn

PMSRn

PMCSRn

Port group n =

0 1 3 4

A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B:

FF40 0000

0000

FF40 0004

0000

FF40 000C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0100 0000 0000

FF40 0104 0000 0000

FF40 010C 0000 0000

H H

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0700

0000

FF40 0704

0000

FF40 070C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0200

0000

FF40 0204

0000

FF40 020C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0300

FFFE

FF40 0304

FFFF

FF40 030C

FFFF

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0400

0000

FF40 0404

0000

FF40 040C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0500

0000

FF40 0504

0000

FF40 050C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0600

0000

FF40 0604

0000

FF40 060C

0000

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0800 0000 FFFE

FF40 0804

0000 FFFF

H H

FF40 080C 0000 FFFF

H H

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0900 0000 0000

H H

FF40 0904 0000 0000

FF40 090C 0000 0000

H H

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

FF40 0010

0000

FF40 0110

0000 0000

FF40 0710

0000

FF40 0210

0000

FF40 0310

FFFF

FF40 0410

0000

FF40 0510

0000

FF40 0610

0000

FF40 0810 0000 FFFF

FF40 0910

0000 0000

H H

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Chapter 2 Port Functions

Table 2-32 V850E2/FG4 port (groups 0, 1, 3, 4) control registers (2/2)

0 1 3 4

PIBCn A: FF40 4000

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PBDCn A: FF40 4100

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PIPCn A: FF40 4200

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PUn A: FF40 4300

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PDn A: FF40 4400

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PODCn A: FF40 4500

I: 0000 0001 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PDSCn A: FF40 4600

I: 0000 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PISn A: FF40 4700

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PISEn A: FF40 4800

I: 0000 B:

1111 xx11 1111 1111 1111 1111 1111 1111 xxxx xxxx 1111 11xx xxxx x111 1111 1111

PPCMDn A: FF40 4C00

I: 00 B:

1111 1111 1111 1111 1111 1111 1111 1111

PPROTSn A: FF40 4B00

I: 00 B:

xxxx xxx1 xxxx xxx1 xxxx xxx1 xxxx xxx1

Port group n =

H H

FF40 4004

0000

FF40 4104

0000

FF40 4204

0000

FF40 4304

0000

FF40 4404

0000

FF40 4504 0000 0000

FF40 4604 0000 0000

FF40 4704

0000

FF40 4804

0000

FF40 4C04

FF40 4B04

FF40 400C

0000

FF40 410C

0000

FF40 420C

0000

FF40 430C

0000

FF40 440C

0000

FF40 450C 0000 0000

FF40 460C 0000 0000

FF40 470C

0000

FF40 480C

0000

FF40 4C0C

FF40 4B0C

H H

FF40 4010

0000

FF40 4110

0000

FF40 4210

0000

FF40 4310

0000

FF40 4410

0000

FF40 4510

0000 0000

FF40 4610

0000 0000

FF40 4710

0000

FF40 4810

0000

FF40 4C10

FF40 4B10

H H

Table 2-33 V850E2/FG4 port (groups 10, 11, JP0) control registers (1/3)

Port group n =

FF44 0000

10 11 JP0

A: I: B:

FF40 0028

0000

FF40 002C

0000

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111

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Chapter 2 Port Functions

Table 2-33 V850E2/FG4 port (groups 10, 11, JP0) control registers (2/3)

PSRn

PNOTn

PPRn

PMn

PMCn

PFCn

A: I: B:

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111 A: I: B:

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111 A: I: B: A:

10 11 JP0

FF40 0128 0000 0000

FF40 0728

0000

FF40 0228

0000

FF40 0328

FFFF

FF40 0428

0000

xxxx 111x xxxx xxxx xxxx xxxx xx11 1111

— —

I: B:

PFCEn

— —

I: B:

PMSRn

PMCSRn

A: I: B: A: I: B:

FF40 0828 0000 FFFF

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111

FF40 0928 0000 0000

xxxx 111x xxxx xxxx xxxx xxxx xx11 1111

PIBCn A: FF40 4028

I: 0000 B:

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111

PBDCn A: FF40 4128

PIPCn A:

I: 0000 B:

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111

— — —

I: B:

PUn A:

— —

I: 00 B:

H H

FF40 012C

0000 0000

FF40 072C

0000

FF40 022C

0000

FF40 032C

FFFF

H —

H H

H — H

FF40 082C 0000 FFFF

FF40 402C

0000

FF40 412C

0000

Port group n =

H H

FF44 0010 0000 0000

FF44 0070

FF44 0020

FF44 0030

FF44 0040

FF44 0050

H H

xxxx xxxx xx11 1111

FF44 0060

xxxx xxxx xx11 1111

FF44 0080 0000 00FF

FF44 0090 0000 0000

FF44 0400

FF44 0410

FF44 0430

H H

xxxx xxxx xx11 1111

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Chapter 2 Port Functions

Table 2-33 V850E2/FG4 port (groups 10, 11, JP0) control registers (3/3)

PDn A:

10 11 JP0

— —

I: 00 B:

PODCn A: FF40 4528

I: 0000 0000 B:

1111 1111 11xx xxxx xxxx xxxx xxxx 1111 xxxx xxxx xx11 1111

PDSCn A:

— —

I: 0000 0000 B:

PISn A:

— —

I: 00 B:

PISEn A:

— —

I: 00 B:

PPCMDn A: FF40 4C28

I: 00 B:

1111 1111 1111 1111 1111 1111

PPROTSn A: FF40 4B28

I: 00 B:

xxxx xxx1 xxxx xxx1 xxxx xxx1

Port group n =

FF44 0440

xxxx xxxx xx11 1111

H H

FF40 452C

0000 0000

FF44 0450 0000 0000

FF44 0460

H H

xxxx xxxx xx11 1111

FF44 0470

xxxx xxxx xx11 1111

FF44 0480

xxxx xxxx xx11 1111

FF40 4C2C

FF40 4B2C

FF44 04C0

FF44 04B0

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Chapter 2 Port Functions

2.4.4 V850E2/FJ4 port functions

This section summarizes all port functions of the V850E2/FJ4 devices and its port control registers.

(1) V850E2/FJ4 general I/O functions

The table below shows all alternative functions, that can be applied to the V850E2/FJ4 ports. It also gives the settings of the control bits PMCn_m, PFCn_m, PFCEn_m and PMn_m to the respective port into the different modes.

Table 2-34 V850E2/FJ4 general I/O functions (1/4)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

Port group 0 (Always-On-Area, E0VDD/E1VSS power supply):

P0_0 TAUJ1I0 TAUJ1O0 CSIG4SSI ADCA0TRG0 INTP0 P0_1 TAUJ1I1 TAUJ1O1 CSIG4SOaURTE2RX INTP1 TAUA0O1 P0_2 TAUJ1I2 TAUJ1O2 CSIG4SI RTCA0OUT ADCA0TRG2 URTE2TX INTP2 TAUA0O2 P0_3 TAUJ1I3 TAUJ1O3 CSIG4SC

P0_4 FCN0TX INTP11 P0_5 FCN0RX INTP12 P0_6 FCN1RX URTE11TX KR0I1 CSIH2CSS1 NMI P0_7 URTE11RX FCN1TX KR0I2 CSIH2CSS2 INTP4 P0_8 FCN2RX URTE10TX KR0I3 CSIH2CSS3 INTP5 TAUA0O5 IICB0SDA

P0_9 URTE10RX FCN2TX KR0I4 CSIH2CSS4 INTP6 TAUA0O6 IICB0SCL P0_10 URTE11TX INTP9 P0_11 URTE11RX INTP10 P0_12 TAUJ0I0 TAUJ0O0 KR0I0 INTP8 CSIG0SSI CSCXFOUT P0_13 TAUJ0I1 TAUJ0O1 KR0I5 CSIH2CSS5 INTP7 CSIG0SI P0_14 TAUJ0I2 TAUJ0O2 KR0I6 CSIH2CSS6 TAUB1O13 CSIG0SO P0_15 TAUJ0I3 TAUJ0O3 KR0I7 CSIH2CSS7 TAUB1O14 CSIG0SC

Port group 1 (Isolated-Area-0, E1VDD/E1VSS power supply):

P1_1 TAUA0I1 TAUA0O1 TAUC4O1 ENCA0AIN FCN1RX FCN0TX

P1_2 TAUA0I2 TAUA0O2 TAUC4O2 ENCA0BIN TAPA0UP CSIH2SI FCN1TX

P1_3 TAUA0I3 TAUA0O3 TAUC4O5 ENCA0ZIN TAPA0UN CSIH2SO

P1_4 TAUA0I4 TAUA0O4 TAUC4O6 ENCA0TIN0 TAPA0VP CSIH2SC

P1_5 TAUA0I5 TAUA0O5 TAUC4O9 ENCA0TIN1 TAPA0VN CSIH2RY

P1_6 TAUA0I6 TAUA0O6 TAUC4O10 TAPA0WP CSIH2SSI CSIH2CSS0

P1_7 TAUA0I7 TAUA0O7 TAUC4O13 TAPA0WN FCN0RX CSIH2CSS1

P1_8 TAUA0I8 TAUA0O8 TAUC4O14 FCN2RX URTE4TX

Alternative mode

PMCn_m = 1

ADCA0TRG1 INTP3/

TAPA0ESO

b b

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Chapter 2 Port Functions

Table 2-34 V850E2/FJ4 general I/O functions (2/4)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

P1_9 TAUA0I9 TAUA0O9 INTP3 FLX0TXENA URTE4RX FCN2TX P1_10 TAUA0I10 TAUA0O10 FLX0RXDA URTE3TX INTP4 P1_11 TAUA0I11 TAUA0O11 URTE3RX FLX0TXDA INTP5 P1_12 TAUA0I12 TAUA0O12 FLX0RXDB URTE4TX INTP6 P1_13 TAUA0I13 TAUA0O13 URTE4RX FLX0TXDB INTP7 P1_14 TAUA0I14 TAUA0O14 FLX0STPWT URTE5TX INTP8 P1_15 TAUA0I15 TAUA0O15 URTE5RX FLX0TXENB INTP9

Port group 2 (Isolated-Area-0, E1VDD/E1VSS power supply):

P2_0 INTP10

Port group 3 (Isolated-Area-0, E1VDD/E1VSS power supply):

P3_2 TAUC2O2 TAUA0I2 TAUA0O2 KR0I7

P3_3 TAUC2O3 TAUA0I3 TAUA0O3 KR0I6

P3_4 TAUC2O5 TAUA0I4 TAUA0O4 KR0I5 CSIG0RY

P3_5 TAUC2O6 TAUA0I5 TAUA0O5 KR0I4 CSIG0SC

P3_6 TAUC2O7 TAUA0I6 TAUA0O6 CSIG0SO

P3_7 TAUC2O9 TAUA0I7 TAUA0O7 CSIG0SI URTE3TX

Port group 4 (Isolated-Area-0, E1VDD/E1VSS power supply):

P4_0 TAUB1I1 TAUB1O1 TAUA0I13 TAUA0O13 CSIH0SI

P4_1 TAUB1I2 TAUB1O2 TAUA0I14 TAUA0O14 CSIH0SOaURTE2RX

P4_2 TAUB1I3 TAUB1O3 TAUA0I15 TAUA0O15 CSIH0SC

P4_3 TAUB1I5 TAUB1O5 CSIG0SI URTE10TX CSIH0RY INTP10

P4_4 INTP2 TAUB1O6 URTE10RX CSIG0SOaCSIH0SSI CSIH0CSS0 ENCA0TIN0

P4_5 TAUB1I7 TAUB1O7 CSIG0SC

P4_6 TAUB1I9 TAUB1O9 CSIG4SI URTE11TX KR0I2 CSIH0CSS2 ENCA0AIN

P4_7 INTP4 TAUB1O10 URTE11RX CSIG4SO

P4_8 TAUB1I11 TAUB1O11 CSIG4SC

P4_9 TAUB1I13 TAUB1O13 CSIG0RY CSIH0CSS5 P4_10 TAUB1I14 TAUB1O14 CSIG4RY CSIH0CSS6 P4_11 TAUB1I15 TAUB1O15 CSIH0CSS7

Port group 10 (Isolated-Area-0, A0VDD/A0VSS power supply):

P10_6 P10_7 P10_8 P10_9 ADCA0TRG0

P10_10 ADCA0TRG1 P10_11 ADCA0TRG2

Alternative mode

PMCn_m = 1

KR0I3 CSIH0CSS1 ENCA0TIN1

KR0I1 CSIH0CSS3 ENCA0BIN KR0I0 CSIH0CSS4 ENCA0ZIN

URTE2TX

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Chapter 2 Port Functions

Table 2-34 V850E2/FJ4 general I/O functions (3/4)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

P10_12 P10_13 P10_14 P10_15

Port group 11 (Isolated-Area-0, A0VDD/A0VSS power supply):

P11_0 P11_1 P11_2 P11_3 P11_4 P11_5 P11_6 P11_7

Port group 21 (Isolated-Area-1, B0VDD/VSS power supply):

P21_2 INTP10 CSIH2SI IICB0SDA P21_3 INTP11 CSIH2SO P21_4 INTP12 CSIH2SC P21_5 INTP13 CSIH2RY TAUC3O2 P21_6 INTP14 CSIH2SSI CSIH2CSS0 TAUC3O5 P21_7 CSIH2CSS1 TAUC3O6 P21_8 INTP15 CSIH2CSS2 PMCA0

P21_9 CSIH2CSS3 PMCA0

P21_10 CSIH2CSS4 PMCA0

P21_11 CSIH2CSS5 TAUC3O14

Port group 25 (Isolated-Area-1, B0VDD/VSS power supply):

P25_0 INTP6

P25_1

P25_2 P25_3 CSIG4SI P25_4 INTP7 CSIG4SO P25_5 CSIG4SC P25_6 P25_7 P25_8 TAUC5O1

Alternative mode

PMCn_m = 1

IICB0SCL

MSEL0

MSEL1

MSEL2

TAUC2O13 TAUC2O14

TAUC3O1

TAUC3O9

TAUC3O10

TAUC3O13

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Chapter 2 Port Functions

Table 2-34 V850E2/FJ4 general I/O functions (4/4)

Port

mode

PMCn_

m = 0

PFCEn_m = 0, PFCn_m = 0 PFCEn_m = 0, PFCn_m = 1 PFCEn_m = 1, PFCn_m = 0 PFCEn_m = 1, PFCn_m = 1

PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0 PMn_m = 1 PMn_m = 0

ALT_IN1 ALT_OUT1 ALT_IN2 ALT_OUT2 ALT_IN3 ALT_OUT3 ALT_IN4 ALT_OUT4

P25_9 TAUC5O2

P25_10 CSIH2CSS6 TAUC5O5 P25_11 CSIH2CSS7 TAUC5O6 P25_12 IICB0SDA P25_13 IICB0SCL P25_14 INTP5 URTE5RX TAUC5O13 P25_15 FCN3RX URTE5TX TAUC5O14

Port group 27 (Isolated-Area-1, B0VDD/VSS power supply):

P27_0 INTP0 PMCA0

P27_1 INTP1 PMCA0

P27_2 INTP2 PMCA0

Port group JP0 (Always-On-Area, E0VDD/E1VSS power supply):

JP0_0 INTP0 VCPC1OUT TAUJ0I0 TAUJ0O0 JP0_1 INTP1 VCPC0OUT TAUJ0I1 TAUJ0O1 JP0_2 INTP2 CSCXFOUT TAUJ0I2 TAUJ0O2 JP0_3 INTP3 TAUJ0I3 TAUJ0O3 JP0_4 JP0_5 NMI RTCA0OUT

When using this alternative mode, set PIPCn.PIPCn_m = 1. The module controls the I/O setting and PMn_m has no effect.

Refer to the section “I2C Interface Port Settings” in the “I2C Interface (IICB)” chapter for details about the correct configuration of the I2C Interface ports.

The ports of port groups 10 and 11 are also used as permanent inputs to the A/D Converter ADCA0. If the P10 or P11 ports shall be used as port inputs, set ADCA0CTL1.ADCA0GPS = 1.

Port P25_1 is not available for V850E2/FJ4-M2 devices.

JP0_0 to JP0_2 are used during flash programming. JP0_0 to JP0_5 are used during debugging. Refer to the section “Common port functions” above for details.

Alternative mode

PMCn_m = 1

MSEL0

MSEL1

MSEL2

TAUC5O9

TAUC5O10

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Chapter 2 Port Functions

(2) V850E2/FJ4 port control registers

The following table summarizes all V850E2/FJ4 port control registers, their addresses and intitial values.

Tables legend A: Register address

I: Initial value B: Available bits

- 1: available, x: not available

- right: bit 0, left: bit 15

Table 2-35 V850E2/FJ4 port (groups 0 to 3) control registers (1/2)

PSRn

PNOTn

PPRn

PMn

PMCn

PFCn

PFCEn

PMSRn

PMCSRn

Port group n =

0 1 2 3

A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B: A: I: B:

FF40 0000

0000

FF40 0004

0000

FF40 0008

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0100 0000 0000

H H

FF40 0104 0000 0000

FF40 0108 0000 0000

H H

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0700

0000

FF40 0704

0000

FF40 0708

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0200

0000

FF40 0204

0000

FF40 0208

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0300

FFFE

FF40 0304

FFFF

FF40 0308

FFFF

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0400

0000

FF40 0404

0000

FF40 0408

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0500

0000

FF40 0504

0000

FF40 0508

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0600

0000

FF40 0604

0000

FF40 0608

0000

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0800 0000 FFFE

FF40 0804

0000 FFFF

H H

FF40 0808

0000 FFFF

H H

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 0900 0000 0000

H H

FF40 0904 0000 0000

FF40 0908 0000 0000

H H

1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxx1 xxxx xxxx 1111 11xx

FF40 000C

0000

FF40 010C

0000 0000

FF40 070C

0000

FF40 020C

0000

FF40 030C

FFFF

FF40 040C

0000

FF40 050C

0000

FF40 060C

0000

FF40 080C

0000 FFFF

FF40 090C

0000 0000

H H

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