RENESAS CA 3140 AEZ Datasheet [it]

Page 1

CA3140, CA3140A

Data Sheet July 11, 2005 FN957.10

4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output

The CA3140A and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip.

The CA3140A and CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CA3140A and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. T e rminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection against damage from load terminal short circuiting to either supply rail or to ground.

The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (±18V).

Features

• MOSFET Input Stage

- Very High Input Impedance (Z

- Very Low Input Current (I

- Wide Common Mode Input Voltage Range (V

) -1.5TΩ (Typ)

) -10pA (Typ) at ±15V

lCR

) - Can be

Swung 0.5V Below Negative Supply V oltage Rail

- Output Swing Complements Input Common Mode Range

• Directly Replaces Industry Type 741 in Most Applications

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Ground-Referenced Single Supply Amplifiers in Automobile and Portable Instrumentation

• Sample and Hold Amplifiers

• Long Duration Timers/Multivibrators (µseconds-Minutes-Hours)

• Photocurrent Instrumentation

• Peak Detectors

• Active Filters

• Comparators

• Interface in 5V TTL Systems and Other Low Supply Voltage Systems

• All Standard Operational Amplifier Applications

• Function Generators

• Tone Controls

• Power Supplies

• Portable Instruments

• Intrusion Alarm Systems

Pinout

CA3140 (PDIP, SOIC)

TOP VIEW

OFFSET

INV. INPUT

NON-INV.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

NULL

INPUT

V-

STROBE

V+

OUTPUT OFFSET

NULL

Page 2

Ordering Information

CA3140, CA3140A

PART NUMBER

(BRAND)

CA3140AE -55 to 125 8 Ld PDIP E8.3 CA3140AEZ*

(See Note) CA3140AM

(3140A) CA3140AM96

(3140A) CA3140AMZ

(3140A) (See Note) CA3140AMZ96

(3140A) (See Note) CA3140E -55 to 125 8 Ld PDIP E8.3 CA3140EZ*

(See Note) CA3140M

(3140) CA3140M96

(3140) CA3140MZ

(3140) (See Note) CA3140MZ96

(3140) (See Note) *Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder processing applications.

TEMP.

RANGE (°C) PACKAGE

-55 to 125 8 Ld PDIP (Pb-free)

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

-55 to 125 8 Ld PDIP (Pb-free)

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC Tape and Reel

-55 to 125 8 Ld SOIC (Pb-free)

-55 to 125 8 Ld SOIC Tape and Reel (Pb-free)

DWG. #

E8.3

M8.15

E8.3

M8.15

PKG.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

FN957.10

July 11, 2005

Page 3

CA3140, CA3140A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V

Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V)

Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short Circuit Duration∞ (Note 2) . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55

C to 125oC

Thermal Resistance (Typical, Note 1) θ

PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 165 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . 150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied.

NOTES:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details

1. θ

2. Short circuit may be applied to ground or to either supply.

(oC/W) θJC (oC/W)

C to 150oC

Electrical Specifications V

= ±15V, TA = 25oC

SUPPLY

TYPICAL VALUES

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Resistor Typical Value of Resistor

4.7 18 kΩ

UNITSCA3140 CA3140A

Between Terminals 4 and 5 or 4 and 1 to

Input Resistance R Input Capacitance C Output Resistance R Equivalent Wideband Input Noise Voltage

(See Figure 27) Equivalent Input Noise Voltage (See Figure 35) e

Adjust Max V

I I

BW = 140kHz, RS = 1MΩ 48 48 µV

RS = 100Ω f = 1kHz 40 40 nV/√Hz

1.5 1.5 TΩ 44pF

60 60 Ω

f = 10kHz 12 12 nV/√Hz

Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA

-Sink1818mA

Gain-Bandwidth Product, (See Figures 6, 30) f

4.5 4.5 MHz

Slew Rate, (See Figure 31) SR 9 9 V/µs Sink Current From Terminal 8 T o Terminal 4 to

220 220 µA

Swing Output Low Transient Response (See Figure 28) t

Settling Time at 10V

, (See Figure 5) t

P-P

OS Overshoot 10 10 %

RL = 2kΩ C

= 100pF

RL = 2kΩ C

= 100pF

Voltage Follower

Rise Time 0.08 0.08 µs

To 1mV 4.5 4.5 µs To 10mV

1.4 1.4 µs

Electrical Specifications For Equipment Design, at V

PARAMETER SYMBOL

Input Offset Voltage |V Input Offset Current |I Input Current I

|- 5 15- 2 5mV

| - 0.5 30 - 0.5 20 pA

= ±15V, TA = 25oC, Unless Otherwise Specified

SUPPLY

CA3140 CA3140A

- 10 50 - 10 40 pA

UNITSMIN TYP MAX MIN TYP MAX

FN957.10

July 11, 2005

Page 4

CA3140, CA3140A

Electrical Specifications For Equipment Design, at V

= ±15V, TA = 25oC, Unless Otherwise Specified (Continued)

SUPPLY

CA3140 CA3140A

PARAMETER SYMBOL

Large Signal Voltage Gain (Note 3) (See Figures 6, 29)

Common Mode Rejection Ratio (See Figure 34)

Common Mode Input Voltage Range (See Figure 8) V Power-Supply Rejection Ratio,

∆V

/∆VS (See Figure 36)

Max Output Voltage (Note 4) (See Figures 2, 8)

20 100 - 20 100 - kV/V 86 100 - 86 100 - dB

CMRR - 32 320 - 32 320 µV/V

70 90 - 70 90 - dB

ICR

-15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V

PSRR - 100 150 - 100 150 µV/V

76 80 - 76 80 - dB

+ +12 13 - +12 13 - V

VOM- -14 -14.4 - -14 -14.4 - V

UNITSMIN TYP MAX MIN TYP MAX

Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA Device Dissipation P

- 120 180 - 120 180 mW

Input Offset Voltage Temperature Drift ∆VIO/∆T- 8 - - 6 -µV/oC

NOTES:

3. At V

4. At R

= 26V

= 2kΩ.

, +12V, -14V and RL = 2kΩ.

P-P

Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, T

= 25oC

TYPICAL VALUES

PARAMETER SYMBOL

Input Offset Voltage |V Input Offset Current |I Input Current I Input Resistance R Large Signal Voltage Gain (See Figures 6, 29) A

|5 2mV

|0.1 0.1pA

22pA 11TΩ

100 100 kV/V

UNITSCA3140 CA3140A

100 100 dB

Common Mode Rejection Ratio CMRR 32 32 µV/V

90 90 dB

Common Mode Input Voltage Range (See Figure 8) V

ICR

-0.5 -0.5 V

2.6 2.6 V

Power Supply Rejection Ratio PSRR

∆V

/∆V

Maximum Output Voltage (See Figures 2, 8) V

Maximum Output Current: Source I

Sink

+3 3 V

- 0.13 0.13 V

+10 10mA

-1 1mA

100 100 µV/V

80 80 dB

Slew Rate (See Figure 31) SR 7 7 V/µs Gain-Bandwidth Product (See Figure 30) f

3.7 3.7 MHz Supply Current (See Figure 32) I+ 1.6 1.6 mA Device Dissipation P

88mW

Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 µA

FN957.10

July 11, 2005

Page 5

Block Diagram

CA3140, CA3140A

Schematic Diagram

+ 3

INPUT

2mA 4mA

BIAS CIRCUIT

CURRENT SOURCES

AND REGULATOR

200µA200µA1.6mA 2µA2mA

≈

A ≈ 10

10,000

A ≈ 1

12pF

1 8

STROBE

OFFSET

NULL

V+

OUTPUT

V-

DYNAMIC CURRENT SINKOUTPUT STAGESECOND STAGEINPUT STAGEBIAS CIRCUIT

V+

50Ω

20Ω

R 12K

20K

INVERTING

INPUT

NON-INVERTING

INPUT

500Ω

5 1 8

NOTE: All resistance values are in ohms.

500Ω

12pF

50Ω

OUTPUT

30Ω

STROBEOFFSET NULL

V-

FN957.10

July 11, 2005

Page 6

CA3140, CA3140A

Application Information

Circuit Description

As shown in the block diagram, the input terminals may be operated down to 0.5V below the negative supply rail. Two class A amplifier stages provide the voltage gain, and a unique class AB amplifier stage provides the current gain necessary to drive low-impedance loads.

A biasing circuit provides control of cascoded constan t current flow circuits in the first and second stages. The CA3140 includes an on chip phase compensating capacitor that is sufficient for the unity gain vol tage follower configuration.

Input Stage

The schematic diagram consists of a differential input stage using PMOS field-effect transistors (Q mirror pair of bipolar transistors (Q resistors together with resistors R transistors also function as a differential-to-single-ended converter to provide base current drive to the second stage bipolar transistor (Q

). Offset nulling, when desired, can be

effected with a 10kΩ potentiometer connected across Terminals 1 and 5 and with its slider arm connected to Terminal

4. Cascode-connected bipolar transistors Q constant current source for the input stage. The base biasing circuit for the constant current source is described subsequently . The small diodes D protection against high voltage transients, e.g., static electricity.

Second Stage

Most of the voltage gain in the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor Q and its cascode connected load resistance provided by bipolar transistors Q

, Q4. On-chip phase compensation,

sufficient for a majority of the applications is provided by C Additional Miller-Effect compensation (roll off) can be accomplished, when desired, by simply connecting a small capacitor between Terminals 1 and 8. Terminal 8 is also used to strobe the output stage into quiescence. When terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output Terminal 6 swings low, i.e., approximately to Terminal 4 potential.

Output Stage

The CA3140 Series circuits employ a broad band output stage that can sink loads to the negative supply to complement the capability of the PMOS input stage when operating near the negative rail. Quiescent current in the emitter-follower cascade circuit (Q whose base currents are “mirrored” to current flowing through diode D operating such that output Terminal 6 is sourcing current, transistor Q from the V+ bus (Terminal 7), via D conditions, the collector potential of Q permit the necessary flow of base current to emitter follower Q

, Q18) is established by transistors (Q14, Q15)

in the bias circuit section. When the CA3140 is

functions as an emitter-follower to source current

which, in turn, drives Q18.

, Q10) working into a

, Q12) functioning as load

through R5. The mirror pair

, Q5 are the

, D4, D5 provide gate oxide

, R9, and R11. Under these

is sufficiently high to

When the CA3140 is operating such that output Terminal 6 is sinking current to the V - b us, transistor Q16 is the current sinking element. Transistor Q with current fed by wa y of Q turn, is biased by current flow through R

is mirror connected to D6, R7,

, R12, and Q20. T r ansistor Q20, in

, zener D8, and R14.

The dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output Terminal 6 is quiescently established at the potential midpoint between the V+ and V - supply rails. When output current sinking mode operation is required, the collector potential of transistor Q driven below its quiescent level, thereby causing Q

, Q18 to

decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q thereby reducing the channel resistance of Q

is displaced toward the V - bus,

. As a consequence, there is an incremental increase in current flow through Q result, Q the incremental change in output voltage caused by Q

, R12, Q21, D6, R7, and the base of Q16. As a

sinks current from Terminal 6 in direct response to

. This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q protection of the output circuit is provided by Q

. Short circuit

, which is

driven into conduction by the high voltage drop dev eloped across R conditions, the collector of Q reduce the base current drive from Q flow in Q

under output short circuit conditions. Under these

to the short circuited load terminal.

diverts current from Q4 so as to

, thereby limiting current

Bias Circuit

Quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in R The function of the bias circuit is to establish and maintain constant current flow through D

, Q6, Q8 and D2. D1 is a diode

connected transistor mirror connected in parallel with the base

emitter junctions of Q current sampling diode that senses the emitter current of Q and automatically adjusts the base current of Q maintain a constant current through Q currents in Q D

. Furthermore, current in diode connected transistor Q2

, Q3 are also determined by constant current flow

establishes the currents in transistors Q

, Q2, and Q3. D1 may be considered as a

(via Q1) to

and Q15.

, Q8, D2. The base

Typical Applications

Wide dynamic range of input and output characte ristics with the most desirable high input impedance char acteristics is achieved in the CA3140 b y the use of an unique design based upon the PMOS Bipolar process. Input common mode volta ge range and output swing capabilities are compl ementary, allowing operation with the single supply down to 4V.

The wide dynamic range of these parameters also means that this device is suitable for many single supply applications, such as, for example , where one input is driven below the potential of Terminal 4 and the phase sense of the output signal must be maintained – a most important consideration in comparator applications.

FN957.10

July 11, 2005

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CA3140, CA3140A

Output Circuit Considerations

Excellent interfacing with TTL circuitry is easily achieved with a single 6.2V zener diode connected to T erminal 8 as shown in Figure 1. This connection assures that the maximum output signal swing will not go more positive than the zener voltage minus two base-to-emitter voltage drops within the CA3140. These voltages are independent of the operating supply voltage.

V+

5V TO 36V

CA3140

6.2V

FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO

TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING TO TTL LEVELS

)

1000

SUPPLY VOLTAGE (V-) = 0V T

= 25oC

SUPPLY VOLTAGE (V+) = +5V

100

0.01 0.1 LOAD (SINKING) CURRENT (mA)

, Q

OUTPUT STAGE TRANSISTOR (Q

SATURATION VOLTAGE (mV)

FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15

AND Q

) vs LOAD CURRENT

Figure 2 shows output current sinking capabilities of the CA3140 at various supply voltages. Output voltage swing to the negative supply rail permits this device to operate both power transistors and thyristors directly without the need for

LOGIC

SUPPLY

≈5V

+15V

1.0 10

TYPICAL TTL GATE

+30V

level shifting circuitry usually associated with the 741 series of operational amplifiers.

Figure 4 shows some typical configurations. Note that a series resistor, R

, is used in both cases to limit the drive

available to the driven device. Moreover, it is recommende d that a series diode and shunt diode be used at the thyristor input to prevent large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit.

Offset Voltage Nulling

The input offset voltage can be nulled by connecting a 10kΩ potentiometer between Terminals 1 and 5 and returning its wiper arm to terminal 4, see Figure 3A. This technique, however, gives more adjustment range than required and therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors (R) that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in the Electrical Specifications table.

An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value shown in the table. For potentiometers, in which the resistance does not drop to 0Ω at either end of rotation, a value of resistance 10% lower than the values shown in the table should be used.

Low Voltage Operation

Operation at total supply voltages as low as 4V is possible with the CA3140. A current regulator based upon the PMOS threshold voltage maintains reasonable constant operating current and hence consistent performance down to these lower voltages.

The low voltage limitation occurs when the upper extreme of the input common mode voltage range extends down to the voltage at Terminal 4. This limit is reached at a total supply voltage just below 4V. The output voltage range also begins to extend down to the negative supply rail, but is slightly higher than that of the input. Figure 8 shows these characteristics and shows that with 2V dual supplies, the lower extreme of the input common mode voltage range is below ground potential.

CA3140

V+

V-

CA3140

10kΩ

V+

V-

V+

10kΩ

CA3140

V-

10kΩ

FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION

FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS

FN957.10

July 11, 2005

Page 8

CA3140, CA3140A

120V

CA3140

FIGURE 4. METHODS OF UTILIZING THE V

LOAD RESISTANCE (RL) = 2kΩ LOAD CAPACIT ANCE (C

SUPPLY VOLTA GE: VS = ±15V T

= 25oC

8 6 4 2 0

-2

-4

INPUT VOLTAGE (V)

-6

-8

-10

0.1

) = 100pF

10mV 10mV

10mV

SETTLING TIME (µs)

30V NO LOAD

10mV

1.0 10

LOAD

1mV

FOLLOWER INVERTING

1mV1mV

V+ +HV

SINKING CURRENT CAPABILITY OF THE CA3140 SERIES

CE(SAT)

10kΩ

5kΩ

200Ω

4.99kΩ

1N914

CA3140

FOLLOWER

+15V

CA3140

-15V

0.05µF

+15V

CA3140

-15V

SETTLING POINT

1N914

2kΩ

INVERTING

5kΩ

0.1µF

LOAD

100pF

5.11kΩ

SIMULATED

LOAD

2kΩ

SIMULATED

LOAD

2kΩ

FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS

FIGURE 5. SETTLING TIME vs INPUT VOLTAGE

Bandwidth and Slew Rate

For those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between Terminals 1 and 8 can reduce the open loop -3dB bandwidth. The slew rate will, however, also be proportionally reduced by using this additional capacitor. Thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%.

Figure 5 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers.

The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in Figure 6.

Input Circuit Considerations

As mentioned previously, the amplifier inputs can be driven below the Terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry.

Moreover, some current limiting resistance should be provided between the inverting input and the output when

FN957.10

July 11, 2005

Page 9

(

)

CA3140, CA3140A

the CA3140 is used as a unity gain voltage follower. This resistance prevents the possibility of extremely large input signal transients from forcing a signal through the input protection network and directly driving the internal constant current source which could result in positive feedback via the output terminal. A 3.9kΩ resistor is sufficient.

The typical input current is on the order of 10pA when the inputs are centered at nominal device dissipation. As the output supplies load current, device dissipation will increase, raising the chip temperature and resulting in increased input current. Figure 7 shows typical input terminal current versus ambient temperature for the CA3140.

It is well known that MOSFET devices can exhibit slight changes in characteristics (for example, small changes in

SUPPLY VOLTAGE: VS = ±15V T

= 25oC

100

AIN

LTA

P V

PEN L

φOL

RL = 2kΩ, C

= 100pF

RL = 2kΩ, C

= 0pF

-75

-90

-105

-120

-135

-150

OPEN LOOP PHASE

input offset voltage) due to the application of large differential input voltages that are sustained over long periods at elevated temperatures.

Both applied voltage and temperature accelerate these changes. The process is reversib le and offset v oltage shifts of the opposite polarity reverse the offset. Figure 9 sho ws the typical offset voltage change as a function of various stress voltages at the maximum rating of 125

C (for metal can); at

lower temperatures (metal can and pl astic), for example, at

C, this change in voltage is co nsider ably less. In typical linear applications, where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor inp ut stage .

10K

SUPPLY VOLTAGE: VS = ±15V

(DEGREES)

100

INPUT CURRENT (pA)

10310410510610710

FREQUENCY (Hz)

FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs

-60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (

FIGURE 7. INPUT CURRENT vs TEMPERATURE

FREQUENCY

N I

E EX

LTA

UTPUT V

INPUT AND

RL = ∞

AT TA = 125oC

ICR

-0.5

-1.0

-1.5

-2.0

-2.5

FROM TERMINAL 7 (V+)

-3.0

0 5 10 15 20 25

ICR

AT TA = -55oC

ICR

AT TA = 25oC

SUPPLY VOLTAGE (V+, V-)

+V +V +V

OUT OUT OUT

AT TA = 125oC AT TA = 25oC AT TA = -55oC

1.5

-V

1.0

0.5

-V

FOR

OUT

= -55oC to 125oC

-0.5

FROM TERMINAL 4 (V-)

-1.0

-1.5

INPUT AND OUTPUT VOLTAGE EXCURSIONS

0 5 10 15 20 25

SUPPLY VOLTAGE (V+, V-)

ICR

-V

ICR

-V

ICR

FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

AT TA = 125oC AT TA = 25oC AT TA = -55oC

FN957.10

July 11, 2005

Page 10

CA3140, CA3140A

TA = 125oC FOR METAL CAN PACKAGES

DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V

OUTPUT STAGE TOGGLED

OFFSET VOLTAGE SHIFT (mV)

0 500 1000 1500 2000 2500 3000 3500 4000 4500

FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE

DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2

TIME (HOURS)

SHIFT vs OPERATING LIFE

Super Sweep Function Generator

A function generator having a wide tuning range is shown in Figure 10. The 1,000,000/1 adjustment range is accomplished by a single variable potentiometer or by an auxiliary sweeping signal. The CA3140 functions as a noninverting readout amplifier of the triangular signal developed across the integrating capacitor network connected to the output of the CA3080A current source.

Buffered triangular output signals are then applied to a second CA3080 functioning as a high speed hysteresis switch. Output from the switch is returned directly back to the input of the CA3080A current source, thereby, completing the positive feedback loop

The triangular output level is determined by the four 1N914 level limiting diodes of the second CA3080 and the resistor divider network connected to Terminal No. 2 (input) of the CA3080. These diodes establish the input trip level to this switching stage and, therefore, indirectly determine the amplitude of the output triangle.

Compensation for propagation delays around the entire loop is provided by one adjustment on the input of the CA3080. This adjustment, which provides for a constant generator amplitude output, is most easily made while the generator is sweeping. High frequency ramp linearity is adjusted by the single 7pF to 60pF capacitor in the output of the CA3080A.

It must be emphasized that only the CA3080A is characterized for maximum output linearity in the current generator function.

Meter Driver and Buffer Amplifier

Figure 11 shows the CA3140 connected as a meter driver and buffer amplifier . Lo w driving impedance is required of the CA3080A current source to assure smooth operation of the Frequency Adjustment Control. This low-driving impedance requirement is easily met by using a CA3140 connected as a voltage follower. Moreover, a meter may be

placed across the input to the CA3080A to give a logarithmic analog indication of the function generator’s frequency.

Analog frequency readout is readily accomplished by the means described above because the output current of the CA3080A varies approximately one decad e for each 60mV change in the applied voltage, V

(voltage between

ABC

Terminals 5 and 4 of the CA3080A of the function generator). Therefore, six decades represent 360mV change in V

ABC

Now, only the reference voltage must be established to set the lower limit on the meter. The three remaining transistors from the CA3086 Array used in the sweep generator are used for this reference voltage. In addition, this reference generator arrangement tends to track ambient temperature variations, and thus compensates for the effects of the normal negative temperature coefficient of the CA3080A V

terminal voltage.

ABC

Another output voltage from the reference generator is used to insure temperature tracking of the lower end of the Frequency Adjustment Potentiometer. A large series resistance simulates a current source, assuring similar temperature coefficients at both ends of the Frequency Adjustment Control.

To calibrate this circuit, set the Frequency Adjustment Potentiometer at its low end. Then adjust the Minimum Frequency Calibration Control for the lowest frequency. To establish the upper frequency limit, set the Frequency Adjustment Potentiometer to its upper end and then adjust the Maximum Frequency Calibration Control for the maximum frequency. Because th ere is interaction among these controls, repetition of the adjustment procedure may be necessary. Two adjustments are used for the meter. The meter sensitivity control sets the meter scale width of each decade, while the meter position control adjusts the pointer on the scale with negligible effect on the sensitivity adjustment. Thus, the meter sensitivity adjustment control calibrates the meter so that it deflects

/6 of full scale for

each decade change in frequency.

Sine Wave Shaper

The circuit shown in Figure 12 uses a CA3140 as a voltage follower in combination with diodes from the CA3019 Array to convert the triangular signal from the function generator to a sine-wave output signal having typically less than 2% THD . The basic zero crossing slope is established by the 10kΩ potentiometer connected between Terminals 2 and 6 of the CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer from Terminal 2 to ground. Two break points are established by diodes D establishes the zero slope at the maximum and minimum levels of the sine wav e. This technique is necessary because the voltage follower configuration approaches unity gain rather than the zero gain required to shape the sine wave at the two extremes.

through D4. Positive feedback via D5 and D6

FN957.10

July 11, 2005

Page 11

CA3140, CA3140A

360Ω

SYMMETRY

FROM BUFFER METER

DRIVER (OPTIONAL)

2MΩ

-15V 100kΩ

THIS NETWORK IS USED WHEN THE OPTIONAL BUFFER CIRCUIT IS NOT USED

7.5kΩ

CA3080A

-15V

15kΩ

7-60

HIGH

FREQ.

SHAPE

10kΩ120Ω

+15V

39kΩ

-15V +15V

+15V+15V

CA3140

-15V

2kΩ

FREQUENCY ADJUSTMENT

OUTPUT

AMPLIFIER

FIGURE 10A. CIRCUIT

0.1 µF

5.1kΩ

0.1 µF

TO SINE WAVE SHAPER

HIGH FREQUENCY LEVEL

7-60pF

11kΩ

10kΩ

EXTERNAL

OUTPUT

CENTERING

-15V

910kΩ

11kΩ

10kΩ

62kΩ

13kΩ

CA3080

+15V

-15V

10kΩ

EXTERNAL OUTPUT

2.7kΩ

TO OUTPUT AMPLIFIER

1N914

Top Trace: Output at junction of 2.7Ω and 51Ω resistors;

5V/Div., 500ms/Div.

Center Trace: External output of triangular function generator;

2V/Div., 500ms/Div.

Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div.

FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING

1V/Div., 1s/Div.

Three tone test signals, highest frequency ≥0.5MHz. Note the slight asymmetry at the three second/cycle signal. This asymmetry is due to slightly different positive and negative integration from the CA3080A and from the PC board and component leakages at the 100 pA level.

FIGURE 10C. FUNCTION GENERATOR WITH FIXED

FREQUENCIES

FIGURE 10. FUNCTION GENERATOR

FREQUENCY

ADJUSTMENT

FINE

RATE

COARSE

METER DRIVER

RATE

AND BUFFER

AMPLIFIER

FUNCTION

GENERATOR

SINE WAVE

SHAPER

SWEEP

GENERA TOR

GATE SWEEP

OFF

V-

INT.

EXT.

SWEEP LENGTH

V-

SUPPL Y ±15V

DC LEVEL

ADJUST

FIGURE 10D. INTERCONNECTIONS

POWER

EXTERNAL INPUT

WIDEBAND LINE DRIVER

51Ω

+15V

-15V

FN957.10

July 11, 2005

Page 12

CA3140, CA3140A

500kΩ

FREQUENCY

ADJUSTMENT

10kΩ

SWEEP IN

FREQUENCY CALIBRATION MAXIMUM

620kΩ

51kΩ

3MΩ

2kΩ

CA3140

0.1µF

FREQUENCY

CALIBRATION

MINIMUM

510Ω

0.1µF

SUBSTRATE

OF CA3019

-15V

5.6kΩ

2856

CA3140

0.1µF

CA3019 DIODE ARRA Y

+15V

R3 10kΩ

TO CA3080A

OF FUNCTION

4.7kΩ

+15V

12kΩ

2.4kΩ

2.5 kΩ

ADJUSTMENT

GENERATOR

(FIGURE 10)

METER

SENSITIVITY

ADJUSTMENT

510Ω

2kΩ

METER

POSITION

/5 OF CA3086

3.6kΩ

CA3080A

620Ω

1kΩ

200µA METER

-15V

5.1kΩ

100

kΩ

+15V

-15V

1MΩ

9.1kΩ R

10kΩ

FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER

750kΩ

0.47µF

470pF

100Ω

1N914

0.047µF 4700pF

LOG

“LOG”

SAWTOOTH

CA3140 +

-15V

VIO

22MΩ

+15V

43kΩ

CA3140

25kΩ

-15V 390Ω

18MΩ

1MΩ

SAWT OO TH SYMMETRY

COARSE RATE

0.1 µF

3.9Ω

50kΩ LOG RATE ADJUST

100kΩ

FINE

100kΩ

RATE

8.2kΩ

SAWTOOTH

“LOG”

TRIANGLE

10kΩ

SWEEP WIDTH

-15V

51kΩ 6.8kΩ 91kΩ

SAWTOOTH AND

+15V

RAMP LOW LEVEL SET (-14.5V)

50kΩ

75kΩ

+15V

100kΩ

30kΩ

10kΩ

EXTERNAL OUTPUT

36kΩ

TO OUTPUT AMPLIFIER

CA3140 +

TO FUNCTION GENERATOR “SWEEP IN”

10kΩ

TRANSISTORS

FROM CA3086

ARRAY

51kΩ

+15V

-15V

10kΩ GATE

TRIANGLE

SAWTOOTH

“LOG”

PULSE OUTPUT

7.5kΩ TO

WIDEBAN

OUTPUT

AMPLIFIER

10kΩ

EXTERNAL OUTPUT

430Ω

1kΩ

FIGURE 13. SWEEPING GENERATOR

FN957.10

July 11, 2005

Page 13

CA3140, CA3140A

This circuit can be adjusted most easily with a distortion analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave generator. The initial slope is adjusted with the potentiometer R

, followed by an adjustment of R2. The final slope is

established by adjusting R segments that are contributed by these diodes. Because there is some interaction among these controls, repetition of the adjustment procedure may be necessary.

Sweeping Generator

Figure 13 shows a sweeping generator. Three CA3140s are used in this circuit. One CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines the starting and stopping points of th e sweep. A third CA3140 is used as a logarithmic shaping network for the log function. Rates and slopes, as well as sawtooth, triangle, and logarithmic sweeps are generated by this circuit.

Wideband Output Amplifier

Figure 14 shows a high slew rate, wideband amplifier suitable for use as a 50Ω transmission line driver. This circuit, when used in conjunction with the function generator and sine wave shaper circuits shown in Figures 10 and 12 provides 18V

output open circuited, or 9V

P-P

when terminated in 50Ω. The slew rate required of this amplifier is 28V/µs (18V

SIGNAL

LEVEL

ADJUSTMENT

2.5kΩ

200Ω

OUTPUT

DC LEVEL

ADJUSTMENT

+15V

-15V

3kΩ

200Ω

FIGURE 14. WIDEBAND OUTPUT AMPLIFIER

Power Supplies

High input impedance, common mode capability down to the negative supply and high output drive current capability are key factors in the design of wide range output voltage supplies that use a single input voltage to provide a regulated output voltage that can be adjusted from essentially 0V to 24V.

Unlike many regulator systems using comparators having a bipolar transistor input stage, a high impedance reference voltage divider from a single supply can be used in connection with the CA3140 (see Figure 15).

, thereby adding additional

x π x 0.5MHz).

P-P

50µF 25V

CA3140

2.4pF 2pF

1.8kΩ

50µF

25V

NOMINAL BANDWIDTH = 10MHz

2.2 kΩ

1N914

2.2 kΩ

P-P

+15V

2N3053

2.7Ω

2N4037

-15V

output

= 35ns

51Ω

OUT

VOLTAGE ADJUSTMENT

CA3140

REGULATED

OUTPUT

INPUT

REFERENCE

VOLTAGE

FIGURE 15. BASIC SINGLE SUPPL Y VOLTA GE REGULA T OR

SHOWING VOLTAGE FOLLOWER CONFIGURA TION

Essentially, the regulators, shown in Figures 16 and 17, are connected as non inverting power operational amplifiers with a gain of 3.2. An 8V reference input yields a maximum output voltage slightly greater than 25V. As a voltage follower, when the reference input goes to 0V the output will be 0V. Because the offset voltage is also multiplied by the 3.2 gain factor, a potentiometer is needed to null the offset voltage.

Series pass transistors with high I

levels will also

CBO

prevent the output voltage from reaching zero because there is a finite voltage drop (V

) across the output of the

CESAT

CA3140 (see Figure 2). This saturation voltage level may indeed set the lowest voltage obtainable.

The high impedance presented by Terminal 8 is advantageous in effecting current limiting. Thus, only a small signal transistor is required for the current-limit sensing amplifier. Resistive decoupling is provided for this transistor to minimize damage to it or the CA3140 in the event of unusual input or output transients on the supply rail.

Figures 16 and 17, show circuits in which a D2201 high spe ed diode is used for the current sensor . This diod e w as chosen for its slightly higher f orward voltage drop characteristic, thus giving greater sensitivity. It must be emphasized that heat sinking of this diode is essential to minimize variation of the current trip point due to internal heating of the diode. That is, 1A at 1V forward drop represents one wa tt which can result in significant regenerative changes in the curren t trip point as the diode temperature rises. Placing the small signal reference amplifier in the proximity of the current sensing diode also helps minimize the variability in the trip lev el due to the negative temperature coefficient of the diode . In spite of those limitations, the current limiting point can easi ly be adjusted over the range from 10mA to 1A with a single adjustment potentiometer. If the temper ature sta bility of the current limiting system is a serious consideration, the more usual current sampling resistor type of circuitry should be employed .

A power Darlington transistor (in a metal can with heatsink), is used as the series pass element for the conventional current limiting system, Figure 16, because high power Darlington dissipation will be encountered at low output voltage and high currents.

FN957.10

July 11, 2005

Page 14

CA3140, CA3140A

A small heat sink VERSAWATT transistor is used as the series pass element in the fold back current system, Figure 17, since dissipation levels will only approach 10W. In this system, the D2201 diode is used for current sampling. Foldback is provided by the 3kΩ and 100kΩ divider network connected to the base of the current sensing transistor.

Both regulators provide better than 0.02% load regulation. Because there is constant loop gain at all voltage settings, the

2N6385

POWER DARLINGTON

+30V

100Ω

10µF

2.7kΩ

INPUT

2.2kΩ

HUM AND NOISE OUTPUT <200µV

(MEASUREMENT BANDWIDTH ~10MHz)

LINE REGULATION 0.1 %/V

3 5

62kΩ

75Ω

3kΩ

100kΩ

CURRENT LIMITING ADJUST

CA3140

5µF

CA3086 1kΩ

RMS

D2201

1kΩ 1kΩ

1kΩ

2N2102

1kΩ

50kΩ

(NO LOAD TO F ULL LOAD)

180kΩ56pF

1kΩ

VOLTAGE

ADJUST

100kΩ

0.01µF

LOAD REGULATION

<0.02%

OUTPUT

0.1 ⇒ 24V AT 1A

82kΩ

250µF

regulation also remains constant. Line regulation is 0.1% per volt. Hum and noise voltage is less than 200µV as read with a meter having a 10MHz bandwidth.

Figure 18A shows the turn ON and turn OFF characteristics of both regulators. The slow turn on rise is due to the slow rate of rise of the reference voltage. Figure 18B shows the transient response of the regulator with the switching of a 20Ω load at 20V output.

“FOLDBACK” CURRENT

LIMITER

10µF

100kΩ

3 5

2N5294

62kΩ

100kΩ

5µF

CA3086

1kΩ

+30V

2.7kΩ

INPUT

2.2kΩ

HUM AND NOISE OUTPUT <200µV

(MEASUREMENT BANDWIDTH ~10 MHz)

LINE REGULATION 0.1%/ V

100kΩ

CA3140

50kΩ

RMS

1kΩ 200Ω

OUTPUT ⇒ 0V TO 25V 25V AT 1A “FOLDS BACK”

D2201

TO 40mA

3kΩ

2N2102

1kΩ

180kΩ56pF

1kΩ

(NO LOAD TO F ULL LOAD)

82kΩ

VOLTAGE

ADJUST

100kΩ

0.01µF

LOAD REGULATION

<0.02%

250µF

FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK”

CURRENT LIMITING

5V/Div., 1s/Div.

Top Trace: Output Voltage;

200mV/Div., 5µs/Div.

Bottom Trace: Collector of load switching transistor, load = 1A;

FIGURE 18A. SUPPLY TURN-ON AND TURNOFF

CHARACTERISTICS

5V/Div., 5µs/Div.

FIGURE 18B. TRANSIENT RESPONSE

FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17

FN957.10

July 11, 2005

Page 15

CA3140, CA3140A

Tone Control Circuits

High slew rate, wide bandwidth, high output voltage capability and high input impedance are all characteristics required of tone control amplifiers. Two tone control circuits that exploit these characteristics of the CA3140 are shown in Figures 19 and 20.

The first circuit, shown in Figure 20, is the Baxandall tone control circuit which provides unity gain at midband and uses standard linear potentiometers. The high input impedance of the CA3140 makes possible the use of lowcost, low-value, small size capacitors, as well as reduced load of the driving stage.

FOR SINGLE SUPPLY

+30V

CA3140

200kΩ

(LINEAR)

100 pF

10kΩ 1MΩ

CCW (LOG)

0.1µF 6

100pF

0.0022µF

100kΩ

0.005µF

5.1

MΩ

2.2MΩ

0.1 µF

2.2MΩ

BOOST TREBLE CUT

0.012µF0.001µF

18kΩ

0.022µF

2µF

- +

BOOST BASS CUT

TONE CONTROL NETWORK

Bass treble boost and cut are ±15dB at 100Hz and 10kHz, respectively. Full peak-to-peak output is available up to at least 20kHz due to the high slew rate of the CA3140. The amplifier gain is 3dB down from its “flat” position at 70kHz.

Figure 19 shows another tone control circuit with similar boost and cut specifications. The wideband gain of this circuit is equal to the ultimate boost or cut plus one, which in this case is a gain of eleven. For 20dB boost and cut, the input loading of this circuit is essentially equal to the value of the resistance from Terminal No. 3 to ground. A detailed analysis of this circuit is given in “An IC Operational T r ansconductance Amplifier (OTA) With Po wer Capability” by L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast and Television Receivers, Vol. BTR-18, No. 3, August, 1972.

NOTES:

5. 20dB Flat Position Gain.

6. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, respectively.

7. 25V

8. -3dB at 24kHz from 1kHz reference.

output at 20kHz.

P-P

0.005µF

5.1MΩ

FOR DUAL SUPPLIES

+15V

CA3140

-15V

TONE CONTROL NETWORK

0.1µF 6

0.1µF

0.047µF

FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)

FOR SINGLE SUPPLY

BOOST BASS CUT

(LINEAR)

240kΩ 5MΩ

750

51kΩ 5MΩ

(LINEAR)

BOOST TREBLE CUT

TONE CONTROL NETWORK

2.2MΩ

20pF

240kΩ

750 pF

51kΩ

FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES

FOR DUAL SUPPLIES

TONE CONTROL

NETWORK

0.1 µF

2.2MΩ

2.2 MΩ

+32V

+ CA3140

0.1 µF

0.047µF

ΝΟΤΕΣ:

9. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively.

10. 25V

Output at 20kHz.

P-P

11. -3dB at 70kHz from 1kHz Reference.

12. 0dB Flat Position Gain.

+15V

CA3140

-15V

0.1µF

FN957.10

July 11, 2005

Page 16

CA3140, CA3140A

Wien Bridge Oscillator

Another application of the CA3140 that makes e xcellent use of its high input impedance, high slew rate , an d high voltage qualities is the Wien Bridge sine wav e oscillator. A basic Wien Bridge oscillator is shown in Figure 21. When R and C

= C2 = C, the frequency equation reduces to the

familiar f = 1/(2πRC) and the gain required for oscillation, A

is equal to 3. Note that if C2 is increased by a factor of

OSC

four and R

is reduced by a factor of four, the gain required

for oscillation becomes 1.5, thus permitting a potentially higher operating frequency closer to the gain bandwidth product of the CA3140.

OUTPUT

NOTES:

OSC

FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT

USING AN OPERATIONAL AMPLIFIER

Oscillator stabilization takes on many forms. It must be precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. The element, R

, is commonly replaced with some variable

resistance element. Thus, through some control means, the value of R

is adjusted to maintain constant oscillator output.

A FET channel resistance, a thermistor, a lamp bulb, or other device whose resistance increases as the output amplitude is increased are a few of the elements often utilized.

Figure 22 shows another means of stabilizing the oscillator with a zener diode shunting the feedback resistor (R Figure 21). As the output signal amplitude increases, the zener diode impedance decreases resulting in more feedback with consequent reduction in gain; thus stabilizing the amplitude of the output signal. Furthe rmore, this combination of a monolithic zener diode and bridge rectifier circuit tends to provide a zero temperature coefficient for this regulating system. Because this bridge rectifier system has no time constant, i.e., thermal time constant for the lamp bulb, and RC time constant for filters often used in detector networks, there is no lower frequency limit. For example , with 1µF polycarbonate capacitors and 22MΩ for the frequency determining network, the operating frequency is 0.007Hz.

As the frequency is increased, the output amplitude must be reduced to prevent the output signal from becoming slewrate limited. An output frequency of 180kHz will reach a slew rate of approximately 9V/µs when its amplitude is 16V

------------------------------------------ -=

2π R

= R2 = R

1C1R2C2

++=

-------

------- -+=

P-P

2 1

OUTPUT

TO 22V

19V

R1 = R2 = R

+15V

7 + CA3140

-15V

1000pF

1000 pF

50Hz, R = 3.3MΩ

100Hz, R = 1.6MΩ

1kHz, R = 160MΩ

10kHz, R = 16MΩ

0.1µF 6

SUBSTRATE

OF CA3019

0.1µF 7

0.1µF

7.5kΩ

3.6kΩ

500Ω

P-P

THD <0.3%

CA3109

DIODE

ARRAY

P-P

5 4

1 3

30kHz, R = 5.1MΩ

FIGURE 22. WIEN BRIDGE OSCILLATOR CIRCUIT USING

CA3140

Simple Sample-and-Hold System

Figure 23 shows a very simple sample-and-hold system using the CA3140 as the readout amplifier for the storage capacitor. The CA3080A serves as both input buff er amplifier and low feed-through transmission switch (see Note 13). System offset nulling is accomplished with the CA3140 via its offset nulling terminals. A typical simulated load of 2kΩ and 30pF is shown in the schematic.

+15V

-15V

200pF

400Ω

INPUT

STROBE

2kΩ

30kΩ

1N914

0.1µF

2kΩ

200pF

+ CA3080A

FIGURE 23. SAMPLE AND HOLD CIRCUIT

In this circuit, the storage compensation capacitance (C

SAMPLE

HOLD-15

100kΩ

SIMULATED LOAD

NOT REQUIRED

+15V

7 + CA3140

2kΩ

0.1µF

-15V

0.1 µF

30pF

3.5kΩ

2kΩ

) is

only 200pF. Larger value capacitors provide longer “hold” periods but with slower slew rates. The slew rate is:

------

--- - 0.5mA 200pF⁄ 2.5V µs⁄== =

NOTE:

13. AN6668 “Applications of the CA3080 and CA 3080A High Performance Operational Transconductance Amplifiers”.

FN957.10

July 11, 2005

Page 17

CA3140, CA3140A

Pulse “droop” during the hold interval is 170pA/200pF which is

0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA represents the typical leakage current of the CA3080A when strobed off. If C

were increased to 2000pF, the “hold-droop” rate will

decrease to 0.085µV/µs, but the slew rate would decrease to

0.25V/µs. The parallel diode network connected between Terminal 3 of the CA3080A and T erminal 6 of the CA3140 prevents large input signal feedthrough across the input terminals of the CA3080A to the 200pF storage capacitor when the CA3080A is strobed off. Figure 24 shows dynamic characteristic waveforms of this sample-and-hold system.

Top Trace: Output; 50mV/Div., 200ns/Div.

Bottom Trace: Input; 50mV/Div., 200ns/Div.

Current Amplifier

The low input terminal current needed to drive the CA3140 makes it ideal for use in current amplifier applications such as the one shown in Figure 25 (see Note 14). In this circuit, low current is supplied at the input potential as the power supply to load resistor R the multiplication factor R monitored by the power supply meter M. Thus, if the load current is 100nA, with values shown, the load current presented to the supply will be 100µA; a much easier current to measure in many systems.

POWER

SUPPLY

FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT

MEASUREMENT SYSTEMS

. This load current is increased by

, when the load current is

2/R1

10kΩ

+15V

0.1µF

CA3140

100kΩ

4.3kΩ

-15V

0.1µF

10MΩ

Top Trace: Output Signal; 5V/Div, 2µs/Div.

Center Trace: Difference of Input and Output Signals through

Tektronix Amplifier 7A13; 5mV/Div., 2µs/Div.

Bottom Trace: Input Signal; 5V/Div., 2µs/Div.

LARGE SIGNAL RESPONSE AND SETTLING TIME

SAMPLING RESPONSE

Top Trace: Output; 100mV/Div., 500ns/Div.

Bottom Trace: Input; 20V/Div., 500ns/Div.

FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC

CHARACTERISTICS WAVEFORMS

Note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor.

The dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. Essentially, the necessary high frequency feedback is provided by the capacitor with the dotted series resistor providing load decoupling.

Full Wave Rectifier

Figure 26 shows a single supply, absolute value, ideal fullwave rectifier with associated waveforms. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the CA3140 functions as a normal inverting amplifier with a gain equal to -R

2/R1

. When the equality of the two equations shown in Figure 26 is satisfied, the full wave output is symmetrical.

NOTE:

14. “Operational Amplifiers Design and Applications”, J. G. Graeme,

McGraw-Hill Book Company, page 308, “Negative Immittance Converter Circuits”.

FN957.10

July 11, 2005

Page 18

CA3140, CA3140A

5kΩ

10kΩ

GAIN

FOR X 0.5

20V

===

-------



-----------------



1X–



10kΩ



Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V

P-P

-------------- -

10kΩ

0.75

-----------

0.5

5kΩ

-----------------------------

R1R2R3+

-------

15kΩ==

CA3140 +

2 1

+15V

100kΩ OFFSET ADJUST

0.1µF

1N914

+15V

0.1µF

CA3140

-15V

2kΩ

0.05µF

100pF

0.1µF

SIMULATED

LOAD

2kΩ

BW (-3dB) = 4.5MHz

SR = 9V/µs

INPUT

10kΩ

PEAK ADJUST 10kΩ

10kΩ

FIGURE 28A. TEST CIRCUIT

OUTPUT 0

INPUT 0

FIGURE 26. SINGLE SUPPL Y, ABSOLUTE VALUE, IDEAL

FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

+15V

0.01µF

1MΩ

BW (-3dB) = 140kHz TOTAL NO ISE VOLTAGE (REFERRED TO INPUT) = 48µV (TYP)

CA3140

-15V

0.01µF

NOISE VOLTAGE OUTPUT

30.1kΩ

1kΩ

FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR

WIDEBAND NOISE MEASUREMENT

Top Trace: Output; 50mV/Div., 200ns/Div.

Bottom Trace: Input; 50mV/Div., 200ns/Div.

FIGURE 28B. SMALL SIGNAL RESPONSE

(Measurement made with Tektronix 7A13 differential amplifier.)

Top Trace: Output Signal; 5V/Div., 5µs/Div.

Center Trace: Difference Signal; 5mV/Div., 5µs/Div.

Bottom Trace: Input Signal; 5V/Div., 5µs/Div.

FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME

FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST

CIRCUIT AND ASSOCIATED WAVEFORMS

FN957.10

July 11, 2005

Page 19

Typical Performance Curves

CA3140, CA3140A

= 2kΩ

TA = -55oC

125

100

OPEN-LOOP VOLTAGE GAIN (dB)

0 5 10 15 20

SUPPLY VOLTAGE (V)

25 125oC

FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY

VOLTAGE AND TEMPERATURE

= 2kΩ

= 100pF

TA = -55oC

125oC

= 2kΩ

= 100pF

TA = -55oC

GAIN BANDWIDTH PRODUCT (MHz)

0 5 10 15 20

SUPPLY VOLTAGE (V)

125oC

FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY

VOLTAGE AND TEMPERATURE

= ∞

TA = -55oC

25oC

125oC

SLEW RATE (V/µs)

5101520

SUPPLY VOLTAGE (V)

FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND

TEMPERATURE

SUPPLY VOLTAGE: VS = ±15V

= 25oC

)

P-P

OUTPUT SWING (V

10K 100K

FREQUENCY (Hz)

1M 4M

FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs

FREQUENCY

QUIESCENT SUPPLY CURRENT (mA)

0 5 10 15 20

SUPPLY VOLTAGE (V)

FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE AND TEMPERATURE

120

SUPPLY VOLTAGE: VS = ±15V

= 25oC

100

COMMON-MODE REJECTION RATIO (dB)

FREQUENCY (Hz)

FIGURE 34. COMMON MODE REJECTION RA TIO vs FREQUENCY

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July 11, 2005

Page 20

Typical Performance Curves (Continued)

CA3140, CA3140A

1000

SUPPLY VOLTA GE: VS = ±15V T

= 25oC

100

EQUIVALENT INPUT NOISE VOL TAGE (nV/√Hz)

110

FREQUENCY (Hz)

FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs

FREQUENCY

SUPPLY VOLTAGE: VS = ±15V T

= 25oC

100

POWER SUPPLY REJECTION RATIO (PSRR) = ∆V

POWER SUPPLY REJECTION RATIO (dB)

-PSRR

/∆V

FREQUENCY (Hz)

+PSRR

FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY

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Page 21

Metallization Mask Layout

CA3140, CA3140A

0 60

4-10

(0.102-0.254)

62-70

(1.575-1.778)

5040302010

Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10

-3

inch).

The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57

instead of 90ο with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

58-66

(1.473-1.676)

FN957.10

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Page 22

Dual-In-Line Plastic Packages (PDIP)

CA3140, CA3140A

-C-

-B-

INDEX

AREA

BASE

PLANE

SEATING

PLANE

12 3 N/2

-AD

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

pendicular to datum .

and eC are measured at the lead tips with the leads uncon-

strained. e

must be zero or greater.

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 D 0.355 0.400 9.01 10.16 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N8 89

NOTESMIN MAX MIN MAX

Rev. 0 12/93

FN957.10

July 11, 2005

Page 23

CA3140, CA3140A

Small Outline Plastic Packages (SOIC)

INDEX AREA

123

SEA TING PLANE

-AD

0.25(0.010) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

h x 45

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6 N8 87

Rev. 0 12/93

NOTESMIN MAX MIN MAX

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN957.10

July 11, 2005