Renesas 16-bit single-chip microcomputer, M16C/6NL, M16C/6NN User Manual

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REJ09B0126-0102

 

 

 

 

 

 

 

 

16

M16C/6N Group

(M16C/6NL, M16C/6NN)

 

 

Hardware Manual

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

M16C FAMILY / M16C/60 SERIES

Before using this material, please visit our website to verify that this is the most updated document available.

Rev. 1.02

 

Revision date: Jul. 01, 2005

www.renesas.com

Keep safety first in your circuit designs!

Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.

Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).

When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited.

Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

How to Use This Manual

1. Introduction

This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers.

Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.

2. Register Diagram

The symbols, and descriptions, used for bit function in each register are shown below.

XXX Register

b7

b6

b5

b4

b3

b2

b1

b0

*1

 

 

 

 

 

 

 

 

 

 

 

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Address

After Reset

*5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX

XXX

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit Name

 

 

Function

 

RW

 

 

 

 

 

 

 

 

 

Symbol

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX0

 

 

b1 b0

 

 

RW

*2

 

 

 

 

 

 

 

 

 

 

0 0: XXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX Bit

 

0 1: XXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 0: Do not set a value

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX1

 

 

 

RW

 

 

 

 

 

 

 

 

 

 

 

1 1: XXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

Nothing is assigned. When write, set to "0",

 

 

 

 

 

*3

 

 

 

 

 

 

 

 

(b2)

When read, its content is indeterminate.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

Reserved Bit

 

Set to "0"

 

 

WO

*4

 

 

 

 

 

 

 

 

(b4-b3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX5

 

 

Function varies depending on

 

RW

 

 

 

 

 

 

 

 

 

 

XXX Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX6

 

mode of operation

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXX7

XXX Bit

 

0: XXX

 

 

RO

 

 

 

 

 

 

 

 

 

 

1: XXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*1

Blank:Set to “0” or “1” according to the application 0 : Set to “0”

1 : Set to “1”

X : Nothing is assigned

*2

RW : Read and write RO : Read only WO: Write only

– : Nothing is assigned

*3

• Reserved bit

Reserved bit. Set to specified value.

*4

• Nothing is assigned

Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when writing to this bit.

• Do not set to this value

The operation is not guaranteed when a value is set.

• Function varies depending on mode of operation

Bit function varies depending on peripheral function mode. Refer to respective register for each mode.

*5

Follow the text in each manual for binary and hexadecimal notations.

3. M16C Family Documents

The following documents were prepared for the M16C family (1).

Document

Contents

 

 

Short Sheet

Hardware overview

 

 

Data Sheet

Hardware overview and electrical characteristics

 

 

Hardware Manual

Hardware specifications (pin assignments, memory maps, peripheral

 

specifications, electrical characteristics, timing charts)

 

 

Software Manual

Detailed description of assembly instructions and microcomputer

 

performance of each instruction

 

 

Application Note

• Application examples of peripheral functions

 

• Sample programs

 

• Introduction to the basic functions in the M16C family

 

• Programming method with Assembly and C languages

 

 

RENESAS TECHNICAL UPDATE

Preliminary report about the specification of a product, a document, etc.

 

 

NOTE:

 

1.Before using this material , please visit our website to verify that this is the most updated document available.

 

Table of Contents

 

SFR Page Reference ............................................................................................................

B-1

1. Overview ...............................................................................................................................

1

1.1 Applications ..................................................................................................................................................

1

1.2

Performance Outline ....................................................................................................................................

2

1.3

Block Diagram ..............................................................................................................................................

4

1.4

Product List ..................................................................................................................................................

5

1.5

Pin Configuration .........................................................................................................................................

6

1.6

Pin Description .............................................................................................................................................

8

2. Central Processing Unit (CPU) ...........................................................................................

10

2.1

Data Registers (R0, R1, R2, and R3) ........................................................................................................

10

2.2 Address Registers (A0 and A1) ..................................................................................................................

10

2.3

Frame Base Register (FB) .........................................................................................................................

11

2.4

Interrupt Table Register (INTB) ..................................................................................................................

11

2.5

Program Counter (PC) ...............................................................................................................................

11

2.6

User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ...........................................................................

11

2.7

Static Base Register (SB) ..........................................................................................................................

11

2.8

Flag Register (FLG) ...................................................................................................................................

11

 

2.8.1 Carry Flag (C Flag) ............................................................................................................................

11

 

2.8.2 Debug Flag (D Flag) ..........................................................................................................................

11

 

2.8.3 Zero Flag (Z Flag) ..............................................................................................................................

11

 

2.8.4 Sign Flag (S Flag) ..............................................................................................................................

11

 

2.8.5 Register Bank Select Flag (B Flag) ....................................................................................................

11

 

2.8.6 Overflow Flag (O Flag) .......................................................................................................................

11

 

2.8.7 Interrupt Enable Flag (I Flag) .............................................................................................................

11

 

2.8.8 Stack Pointer Select Flag (U Flag) .....................................................................................................

11

 

2.8.9 Processor Interrupt Priority Level (IPL) ..............................................................................................

11

 

2.8.10 Reserved Area .................................................................................................................................

11

3. Memory ...............................................................................................................................

12

4. Special Function Register (SFR) .........................................................................................

13

5. Reset ...................................................................................................................................

25

5.1

Hardware Reset .........................................................................................................................................

25

 

5.1.1 Reset on a Stable Supply Voltage .....................................................................................................

25

 

5.1.2 Power-on Reset .................................................................................................................................

25

5.2

Software Reset ..........................................................................................................................................

25

5.3

Watchdog Timer Reset ...............................................................................................................................

25

5.4

Oscillation Stop Detection Reset ...............................................................................................................

25

6. Processor Mode ..................................................................................................................

28

7. Clock Generating Circuit .....................................................................................................

31

7.1 Types of Clock Generating Circuit .............................................................................................................

31

 

7.1.1 Main Clock .........................................................................................................................................

39

 

7.1.2 Sub Clock ...........................................................................................................................................

40

 

7.1.3 On-chip Oscillator Clock ....................................................................................................................

41

 

7.1.4 PLL Clock ...........................................................................................................................................

41

A-1

7.2

CPU Clock and Peripheral Function Clock ................................................................................................

43

 

7.2.1 CPU Clock and BCLK ........................................................................................................................

43

 

7.2.2 Peripheral Function Clock ..................................................................................................................

43

7.3

Clock Output Function ...............................................................................................................................

43

7.4

Power Control ............................................................................................................................................

44

 

7.4.1 Normal Operation Mode .....................................................................................................................

44

 

7.4.2 Wait Mode ..........................................................................................................................................

46

 

7.4.3 Stop Mode ..........................................................................................................................................

48

7.5

Oscillation Stop and Re-oscillation Detection Function .............................................................................

53

 

7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) ....................................................

53

 

7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ........................

53

 

7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function ..................................................

54

8. Protection ............................................................................................................................

55

9. Interrupt ...............................................................................................................................

56

9.1 Type of Interrupts .......................................................................................................................................

56

9.2

Software Interrupts .....................................................................................................................................

57

 

9.2.1 Undefined Instruction Interrupt ...........................................................................................................

57

 

9.2.2 Overflow Interrupt ..............................................................................................................................

57

 

9.2.3 BRK Interrupt .....................................................................................................................................

57

 

9.2.4 INT Instruction Interrupt .....................................................................................................................

57

9.3

Hardware Interrupts ...................................................................................................................................

58

 

9.3.1 Special Interrupts ...............................................................................................................................

58

 

9.3.2 Peripheral Function Interrupts ............................................................................................................

58

9.4

Interrupts and Interrupt Vector ...................................................................................................................

59

 

9.4.1 Fixed Vector Tables ............................................................................................................................

59

 

9.4.2 Relocatable Vector Tables .................................................................................................................

59

9.5

Interrupt Control .........................................................................................................................................

61

 

9.5.1 I Flag ..................................................................................................................................................

63

 

9.5.2 IR Bit ..................................................................................................................................................

63

 

9.5.3 ILVL2 to ILVL0 Bits and IPL ...............................................................................................................

63

 

9.5.4 Interrupt Sequence ............................................................................................................................

64

 

9.5.5 Interrupt Response Time ....................................................................................................................

65

 

9.5.6 Variation of IPL when Interrupt Request is Accepted .........................................................................

65

 

9.5.7 Saving Registers ................................................................................................................................

66

 

9.5.8 Returning from an Interrupt Routine ..................................................................................................

67

 

9.5.9 Interrupt Priority .................................................................................................................................

67

 

9.5.10 Interrupt Priority Resolution Circuit ..................................................................................................

67

9.6

______

69

INT Interrupt ...............................................................................................................................................

9.7

______

73

NMI Interrupt ..............................................................................................................................................

9.8

Key Input Interrupt .....................................................................................................................................

73

9.9

CAN0 Wake-up Interrupt ............................................................................................................................

73

9.10 Address Match Interrupt ...........................................................................................................................

74

10. Watchdog Timer ................................................................................................................

76

10.1 Count Source Protective Mode ................................................................................................................

77

A-2

11. DMAC ................................................................................................................................

78

11.1 Transfer Cycle ..........................................................................................................................................

83

11.1.1 Effect of Source and Destination Addresses ....................................................................................

83

11.1.2 Effect of Software Wait .....................................................................................................................

83

11.2 DMA Transfer Cycles ................................................................................................................................

85

11.3 DMA Enable .............................................................................................................................................

86

11.4 DMA Request ...........................................................................................................................................

86

11.5 Channel Priority and DMA Transfer Timing ..............................................................................................

87

12. Timers ...............................................................................................................................

88

12.1 Timer A .....................................................................................................................................................

90

12.1.1 Timer Mode ......................................................................................................................................

94

12.1.2 Event Counter Mode ........................................................................................................................

95

12.1.3 One-shot Timer Mode ....................................................................................................................

100

12.1.4 Pulse Width Modulation (PWM) Mode ...........................................................................................

102

12.2 Timer B ...................................................................................................................................................

105

12.2.1 Timer Mode ....................................................................................................................................

108

12.2.2 Event Counter Mode ......................................................................................................................

109

12.2.3 Pulse Period and Pulse Width Measurement Mode ......................................................................

110

13. Three-Phase Motor Control Timer Function ....................................................................

113

14. Serial I/O .........................................................................................................................

124

14.1 UARTi .....................................................................................................................................................

124

14.1.1 Clock Synchronous Serial I/O Mode ..............................................................................................

134

14.1.2 Clock Asynchronous Serial I/O (UART) Mode ...............................................................................

142

14.1.3 Special Mode 1 (I2C Mode) ............................................................................................................

150

14.1.4 Special Mode 2 ..............................................................................................................................

159

14.1.5 Special Mode 3 (IE Mode) .............................................................................................................

164

14.1.6 Special Mode 4 (SIM Mode) (UART2) ...........................................................................................

166

14.2 SI/Oi .......................................................................................................................................................

171

14.2.1 SI/Oi Operation Timing ...................................................................................................................

175

14.2.2 CLK Polarity Selection ...................................................................................................................

175

14.2.3 Functions for Setting an SOUTi Initial Value ..................................................................................

176

15. A/D Converter ..................................................................................................................

177

15.1 Mode Description ...................................................................................................................................

181

15.1.1 One-shot Mode ..............................................................................................................................

181

15.1.2 Repeat Mode .................................................................................................................................

183

15.1.3 Single Sweep Mode .......................................................................................................................

185

15.1.4 Repeat Sweep Mode 0 ..................................................................................................................

187

15.1.5 Repeat Sweep Mode 1 ..................................................................................................................

189

15.2 Function .................................................................................................................................................

191

15.2.1 Resolution Select Function ............................................................................................................

191

15.2.2 Sample and Hold ...........................................................................................................................

191

15.2.3 Extended Analog Input Pins ...........................................................................................................

191

15.2.4 External Operation Amplifier (Op-Amp) Connection Mode ............................................................

191

15.2.5 Current Consumption Reducing Function ......................................................................................

192

15.2.6 Output Impedance of Sensor under A/D Conversion .....................................................................

192

16. D/A Converter ..................................................................................................................

194

17. CRC Calculation ..............................................................................................................

196

A-3

18. CAN Module ....................................................................................................................

198

18.1

CAN Module-Related Registers .............................................................................................................

199

18.1.1 CAN Message Box .........................................................................................................................

199

18.1.2 Acceptance Mask Registers ...........................................................................................................

199

18.1.3 CAN SFR Registers .......................................................................................................................

199

18.2 CAN0 Message Box ...............................................................................................................................

200

18.3 Acceptance Mask Registers ...................................................................................................................

202

18.4

CAN SFR Registers ...............................................................................................................................

203

18.5

Operational Modes .................................................................................................................................

210

18.5.1 CAN Reset/Initialization Mode .......................................................................................................

210

18.5.2 CAN Operation Mode .....................................................................................................................

211

18.5.3 CAN Sleep Mode ...........................................................................................................................

211

18.5.4 CAN Interface Sleep Mode ............................................................................................................

211

18.5.5 Bus Off State ..................................................................................................................................

212

18.6

Configuration CAN Module System Clock .............................................................................................

213

18.7

Bit Timing Configuration .........................................................................................................................

213

18.8

Bit-rate ...................................................................................................................................................

214

18.9 Acceptance Filtering Function and Masking Function ............................................................................

215

18.10 Acceptance Filter Support Unit (ASU) ..................................................................................................

216

18.11 Basic CAN Mode ..................................................................................................................................

217

18.12 Return from Bus off Function ...............................................................................................................

218

18.13 Time Stamp Counter and Time Stamp Function ..................................................................................

218

18.14 Listen-Only Mode .................................................................................................................................

218

18.15 Reception and Transmission ................................................................................................................

219

18.15.1 Reception .....................................................................................................................................

220

18.15.2 Transmission ................................................................................................................................

221

18.16 CAN Interrupt .......................................................................................................................................

222

19. Programmable I/O Ports .................................................................................................

223

19.1

PDi Register ...........................................................................................................................................

224

19.2

Pi Register, PC14 Register ....................................................................................................................

224

19.3

PURj Register ........................................................................................................................................

224

19.4

PCR Register .........................................................................................................................................

224

20. Flash Memory Version ....................................................................................................

235

20.1 Memory Map ..........................................................................................................................................

236

20.1.1 Boot Mode ......................................................................................................................................

237

20.2

Functions to Prevent Flash Memory from Rewriting ..............................................................................

237

20.2.1 ROM Code Protect Function ..........................................................................................................

237

20.2.2 ID Code Check Function ................................................................................................................

237

20.3

CPU Rewrite Mode ................................................................................................................................

239

20.3.1 EW0 Mode .....................................................................................................................................

240

20.3.2 EW1 Mode .....................................................................................................................................

240

20.3.3 FMR0, FMR1 Registers .................................................................................................................

241

20.3.4 Precautions on CPU Rewrite Mode ...............................................................................................

245

20.3.5 Software Commands .....................................................................................................................

247

20.3.6 Data Protect Function ....................................................................................................................

252

20.3.7 Status Register (SRD Register) .....................................................................................................

252

20.3.8 Full Status Check ...........................................................................................................................

254

A-4

20.4 Standard Serial I/O Mode ......................................................................................................................

256

20.4.1 ID Code Check Function ................................................................................................................

256

20.4.2 Example of Circuit Application in Standard Serial I/O Mode ..........................................................

260

20.5 Parallel I/O Mode ...................................................................................................................................

261

20.5.1 User ROM and Boot ROM Areas ...................................................................................................

261

20.5.2 ROM Code Protect Function ..........................................................................................................

261

20.6 CAN I/O Mode ........................................................................................................................................

262

20.6.1 ID Code Check Function ................................................................................................................

262

20.6.2 Example of Circuit Application in CAN I/O Mode ...........................................................................

265

21. Electrical Characteristics .................................................................................................

266

22. Usage Precaution ............................................................................................................

276

22.1 SFR ........................................................................................................................................................

276

22.2 External Clock ........................................................................................................................................

277

22.3 PLL Frequency Synthesizer ...................................................................................................................

278

22.4 Power Control ........................................................................................................................................

279

22.5 Oscillation Stop, Re-oscillation Detection Function ...............................................................................

281

22.6 Protection ...............................................................................................................................................

282

22.7 Interrupt ..................................................................................................................................................

283

22.7.1 Reading Address 00000h ...............................................................................................................

283

22.7.2 Setting SP ......................................................................................................................................

283

_______

283

22.7.3 NMI Interrupt ..................................................................................................................................

22.7.4 Changing Interrupt Generate Factor ..............................................................................................

284

_____

284

22.7.5 INT Interrupt ...................................................................................................................................

22.7.6 Rewrite Interrupt Control Register .................................................................................................

285

22.7.7 Watchdog Timer Interrupt ..............................................................................................................

285

22.8 DMAC ....................................................................................................................................................

286

22.8.1 Write to DMAE Bit in DMiCON Register ........................................................................................

286

22.9 Timers ....................................................................................................................................................

287

22.9.1 Timer A ...........................................................................................................................................

287

22.9.2 Timer B ...........................................................................................................................................

291

22.10 Thee-Phase Motor Control Timer Function ..........................................................................................

293

22.11 Serial I/O ..............................................................................................................................................

294

22.11.1 Clock Synchronous Serial I/O Mode ............................................................................................

294

22.11.2 Special Modes ..............................................................................................................................

295

22.11.3 SI/Oi .............................................................................................................................................

296

22.12 A/D Converter ......................................................................................................................................

297

22.13 CAN Module .........................................................................................................................................

299

22.13.1 Reading C0STR Register ............................................................................................................

299

22.13.2 Performing CAN Configuration ....................................................................................................

301

22.13.3 Suggestions to Reduce Power Consumption ..............................................................................

302

22.13.4 CAN Transceiver in Boot Mode ....................................................................................................

303

22.14 Programmable I/O Ports ......................................................................................................................

304

22.15 Dedicated Input Pin ..............................................................................................................................

305

22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers .....

306

22.17 Mask ROM Version .............................................................................................................................

307

A-5

22.18 Flash Memory Version .........................................................................................................................

308

22.18.1 Functions to Prevent Flash Memory from Rewriting ....................................................................

308

22.18.2 Stop Mode ....................................................................................................................................

308

22.18.3 Wait Mode ....................................................................................................................................

308

22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode .................

308

22.18.5 Writing Command and Data .........................................................................................................

308

22.18.6 Program Command ......................................................................................................................

308

22.18.7 Lock Bit Program Command ........................................................................................................

308

22.18.8 Operation Speed ..........................................................................................................................

309

22.18.9 Prohibited Instructions .................................................................................................................

309

22.18.10 Interrupt ......................................................................................................................................

309

22.18.11 How to Access ............................................................................................................................

309

22.18.12 Rewriting in User ROM Area ......................................................................................................

309

22.18.13 DMA Transfer .............................................................................................................................

309

22.19 Flash Memory Programming Using Boot Program ..............................................................................

310

22.19.1 Programming Using Serial I/O Mode ...........................................................................................

310

22.19.2 Programming Using CAN I/O Mode .............................................................................................

310

22.20 Noise ....................................................................................................................................................

311

Appendix 1. Package Dimensions ........................................................................................

312

Register Index .......................................................................................................................

313

Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

A-6

SFR Page Reference

Address

Register

Symbol

Page

0000h

 

 

 

0001h

 

 

 

0002h

 

 

 

0003h

 

 

 

0004h

Processor Mode Register 0

PM0

28

0005h

Processor Mode Register 1

PM1

29

0006h

System Clock Control Register 0

CM0

33

0007h

System Clock Control Register 1

CM1

34

0008h

 

 

 

0009h

Address Match Interrupt Enable Register

AIER

75

000Ah

Protect Register

PRCR

55

000Bh

 

 

 

000Ch

Oscillation Stop Detection Register

CM2

35

000Dh

 

 

 

000Eh

Watchdog Timer Start Register

WDTS

77

000Fh

Watchdog Timer Control Register

WDC

77

0010h

 

 

 

0011h

Address Match Interrupt Register 0

RMAD0

75

0012h

 

 

 

0013h

 

 

 

0014h

 

 

 

0015h

Address Match Interrupt Register 1

RMAD1

75

0016h

 

 

 

0017h

 

 

 

0018h

 

 

 

0019h

 

 

 

001Ah

 

 

 

001Bh

 

 

 

001Ch

PLL Control Register 0

PLC0

38

001Dh

 

 

 

001Eh

Processor Mode Register 2

PM2

37

001Fh

 

 

 

0020h

 

 

 

0021h

DMA0 Source Pointer

SAR0

82

0022h

 

 

 

0023h

 

 

 

0024h

 

 

 

0025h

DMA0 Destination Pointer

DAR0

82

0026h

 

 

 

0027h

 

 

 

0028h

DMA0 Transfer Counter

TCR0

82

0029h

 

 

 

002Ah

 

 

 

002Bh

 

 

 

002Ch

DMA0 Control Register

DM0CON

81

002Dh

 

 

 

002Eh

 

 

 

002Fh

 

 

 

0030h

 

 

 

0031h

DMA1 Source Pointer

SAR1

82

0032h

 

 

 

0033h

 

 

 

0034h

 

 

 

0035h

DMA1 Destination Pointer

DAR1

82

0036h

 

 

 

0037h

 

 

 

0038h

DMA1 Transfer Counter

TCR1

82

0039h

 

 

 

003Ah

 

 

 

003Bh

 

 

 

003Ch

DMA1 Control Register

DM1CON

81

003Dh

 

 

 

003Eh

 

 

 

003Fh

 

 

 

The blank areas are reserved.

Address

Register

Symbol

Page

0040h

 

 

 

0041h

CAN0 Wake-up Interrupt Control Register

C01WKIC

61

0042h

CAN0 Successful Reception Interrupt Control Register

C0RECIC

61

0043h

CAN0 Successful Transmission Interrupt Control Register

C0TRMIC

61

0044h

INT3 Interrupt Control Register

INT3IC

62

0045h

Timer B5 Interrupt Control Register

TB5IC

61

SI/O5 Interrupt Control Register

S5IC

61

 

0046h

Timer B4 Interrupt Control Register

TB4IC

61

UART1 Bus Collision Detection Interrupt Control Register

U1BCNIC

61

 

0047h

Timer B3 Interrupt Control Register

TB3IC

61

UART0 Bus Collision Detection Interrupt Control Register

U0BCNIC

61

 

0048h

SI/O4 Interrupt Control Register

S4IC

62

INT5 Interrupt Control Register

INT5IC

62

 

0049h

SI/O3 Interrupt Control Register

S3IC

62

INT4 Interrupt Control Register

INT4IC

62

 

004Ah

UART2 Bus Collision Detection Interrupt Control Register

U2BCNIC

61

004Bh

DMA0 Interrupt Control Register

DM0IC

61

004Ch

DMA1 Interrupt Control Register

DM1IC

61

004Dh

CAN0 Error Interrupt Control Register

C01ERRIC

61

004Eh

A/D Conversion Interrupt Control Register

ADIC

61

Key Input Interrupt Control Register

KUPIC

61

 

004Fh

UART2 Transmit Interrupt Control Register

S2TIC

61

0050h

UART2 Receive Interrupt Control Register

S2RIC

61

0051h

UART0 Transmit Interrupt Control Register

S0TIC

61

0052h

UART0 Receive Interrupt Control Register

S0RIC

61

0053h

UART1 Transmit Interrupt Control Register

S1TIC

61

0054h

UART1 Receive Interrupt Control Register

S1RIC

61

0055h

Timer A0 Interrupt Control Register

TA0IC

61

0056h

Timer A1 Interrupt Control Register

TA1IC

61

0057h

Timer A2 Interrupt Control Register

TA2IC

62

INT7 Interrupt Control Register

INT7IC

62

 

0058h

Timer A3 Interrupt Control Register

TA3IC

62

INT6 Interrupt Control Register

INT6IC

62

 

0059h

Timer A4 Interrupt Control Register

TA4IC

61

005Ah

Timer B0 Interrupt Control Register

TB0IC

61

SI/O6 Interrupt Control Register

S6IC

61

 

005Bh

Timer B1 Interrupt Control Register

TB1IC

62

INT8 Interrupt Control Register

INT8IC

62

 

005Ch

Timer B2 Interrupt Control Register

TB2IC

61

005Dh

INT0 Interrupt Control Register

INT0IC

62

005Eh

INT1 Interrupt Control Register

INT1IC

62

005Fh

INT2 Interrupt Control Register

INT2IC

62

0060h

 

 

 

0061h

 

 

 

0062h

CAN0 Message Box 0: Identifier / DLC

 

 

0063h

 

 

0064h

 

 

 

0065h

 

 

 

0066h

 

 

 

0067h

 

 

 

0068h

 

 

 

0069h

CAN0 Message Box 0: Data Field

 

 

006Ah

 

 

006Bh

 

 

 

006Ch

 

 

 

006Dh

 

 

 

006Eh

CAN0 Message Box 0: Time Stamp

 

200

006Fh

 

0070h

 

 

201

0071h

 

 

 

0072h

CAN0 Message Box 1: Identifier / DLC

 

 

0073h

 

 

0074h

 

 

 

0075h

 

 

 

0076h

 

 

 

0077h

 

 

 

0078h

 

 

 

0079h

CAN0 Message Box 1: Data Field

 

 

007Ah

 

 

007Bh

 

 

 

007Ch

 

 

 

007Dh

 

 

 

007Eh

CAN0 Message Box 1: Time Stamp

 

 

007Fh

 

 

B-1

Address

Register

Symbol

Page

0080h

 

 

 

0081h

 

 

 

0082h

CAN0 Message Box 2: Identifier / DLC

 

 

0083h

 

 

 

 

 

0084h

 

 

 

0085h

 

 

 

0086h

 

 

 

0087h

 

 

 

 

0088h

 

 

 

 

0089h

 

CAN0 Message Box 2: Data Field

 

 

008Ah

 

 

 

008Bh

 

 

 

 

008Ch

 

 

 

 

008Dh

 

 

 

 

008Eh

CAN0 Message Box 2: Time Stamp

 

 

008Fh

 

 

0090h

 

 

 

0091h

 

 

 

0092h

CAN0 Message Box 3: Identifier / DLC

 

 

0093h

 

 

0094h

 

 

 

0095h

 

 

 

0096h

 

 

 

0097h

 

 

 

0098h

 

 

 

0099h

CAN0 Message Box 3: Data Field

 

 

009Ah

 

 

009Bh

 

 

 

009Ch

 

 

 

009Dh

 

 

 

009Eh

CAN0 Message Box 3: Time Stamp

 

 

009Fh

 

200

00A0h

 

 

201

00A1h

 

 

 

00A2h

CAN0 Message Box 4: Identifier / DLC

 

 

00A3h

 

 

00A4h

 

 

 

00A5h

 

 

 

00A6h

 

 

 

00A7h

 

 

 

00A8h

 

 

 

00A9h

CAN0 Message Box 4: Data Field

 

 

00AAh

 

 

00ABh

 

 

 

00ACh

 

 

 

00ADh

 

 

 

00AEh

CAN0 Message Box 4: Time Stamp

 

 

00AFh

 

 

00B0h

 

 

 

00B1h

 

 

 

00B2h

CAN0 Message Box 5: Identifier / DLC

 

 

00B3h

 

 

00B4h

 

 

 

00B5h

 

 

 

00B6h

 

 

 

00B7h

 

 

 

00B8h

 

 

 

00B9h

CAN0 Message Box 5: Data Field

 

 

00BAh

 

 

00BBh

 

 

 

00BCh

 

 

 

00BDh

 

 

 

00BEh

CAN0 Message Box 5: Time Stamp

 

 

00BFh

 

 

Address

Register

Symbol

Page

00C0h

 

 

 

 

00C1h

 

 

 

 

00C2h

CAN0 Message Box 6: Identifier / DLC

 

 

 

00C3h

 

 

 

00C4h

 

 

 

 

00C5h

 

 

 

 

00C6h

 

 

 

 

00C7h

 

 

 

 

00C8h

 

 

 

 

00C9h

CAN0 Message Box 6: Data Field

 

 

 

00CAh

 

 

 

00CBh

 

 

 

 

00CCh

 

 

 

 

00CDh

 

 

 

 

00CEh

CAN0 Message Box 6: Time Stamp

 

 

 

00CFh

 

 

 

00D0h

 

 

 

 

00D1h

 

 

 

 

00D2h

CAN0 Message Box 7: Identifier / DLC

 

 

 

00D3h

 

 

 

00D4h

 

 

 

 

00D5h

 

 

 

 

00D6h

 

 

 

 

00D7h

 

 

 

 

00D8h

 

 

 

 

00D9h

CAN0 Message Box 7: Data Field

 

 

 

00DAh

 

 

 

00DBh

 

 

 

 

00DCh

 

 

 

 

00DDh

 

 

 

 

00DEh

CAN0 Message Box 7: Time Stamp

 

 

 

00DFh

 

200

00E0h

 

 

 

201

00E1h

 

 

 

 

00E2h

CAN0 Message Box 8: Identifier / DLC

 

 

 

00E3h

 

 

 

00E4h

 

 

 

 

00E5h

 

 

 

 

00E6h

 

 

 

 

00E7h

 

 

 

 

00E8h

 

 

 

 

00E9h

CAN0 Message Box 8: Data Field

 

 

 

00EAh

 

 

 

00EBh

 

 

 

 

00ECh

 

 

 

 

00EDh

 

 

 

 

00EEh

CAN0 Message Box 8: Time Stamp

 

 

 

00EFh

 

 

 

00F0h

 

 

 

 

00F1h

 

 

 

 

00F2h

CAN0 Message Box 9: Identifier / DLC

 

 

 

00F3h

 

 

 

 

 

 

 

00F4h

 

 

 

 

00F5h

 

 

 

 

00F6h

 

 

 

 

00F7h

 

 

 

 

00F8h

 

 

 

 

00F9h

CAN0 Message Box 9: Data Field

 

 

 

00FAh

 

 

 

00FBh

 

 

 

 

00FCh

 

 

 

 

00FDh

 

 

 

 

00FEh

CAN0 Message Box 9: Time Stamp

 

 

 

00FFh

 

 

 

B-2

Address

Register

Symbol

Page

0100h

 

 

 

0101h

 

 

 

0102h

CAN0 Message Box 10: Identifier / DLC

 

 

0103h

 

 

 

 

 

0104h

 

 

 

0105h

 

 

 

0106h

 

 

 

0107h

 

 

 

 

0108h

 

 

 

 

0109h

 

CAN0 Message Box 10: Data Field

 

 

010Ah

 

 

 

010Bh

 

 

 

 

010Ch

 

 

 

 

010Dh

 

 

 

 

010Eh

CAN0 Message Box 10: Time Stamp

 

 

010Fh

 

 

0110h

 

 

 

0111h

 

 

 

0112h

CAN0 Message Box 11: Identifier / DLC

 

 

0113h

 

 

 

 

 

0114h

 

 

 

0115h

 

 

 

0116h

 

 

 

0117h

 

 

 

0118h

 

 

 

0119h

CAN0 Message Box 11: Data Field

 

 

011Ah

 

 

011Bh

 

 

 

011Ch

 

 

 

011Dh

 

 

 

011Eh

CAN0 Message Box 11: Time Stamp

 

 

011Fh

 

200

0120h

 

 

201

0121h

 

 

 

0122h

CAN0 Message Box 12: Identifier / DLC

 

 

0123h

 

 

0124h

 

 

 

0125h

 

 

 

0126h

 

 

 

0127h

 

 

 

0128h

 

 

 

0129h

CAN0 Message Box 12: Data Field

 

 

012Ah

 

 

012Bh

 

 

 

012Ch

 

 

 

012Dh

 

 

 

012Eh

CAN0 Message Box 12: Time Stamp

 

 

012Fh

 

 

0130h

 

 

 

0131h

 

 

 

0132h

CAN0 Message Box 13: Identifier / DLC

 

 

0133h

 

 

0134h

 

 

 

0135h

 

 

 

0136h

 

 

 

0137h

 

 

 

0138h

 

 

 

0139h

CAN0 Message Box 13: Data Field

 

 

013Ah

 

 

013Bh

 

 

 

013Ch

 

 

 

013Dh

 

 

 

013Eh

CAN0 Message Box 13: Time Stamp

 

 

013Fh

 

 

The blank areas are reserved.

Address

Register

Symbol

Page

0140h

 

 

 

0141h

 

 

 

0142h

CAN0 Message Box 14: Identifier /DLC

 

 

0143h

 

 

0144h

 

 

 

0145h

 

 

 

0146h

 

 

 

0147h

 

 

 

 

0148h

 

 

 

 

0149h

 

CAN0 Message Box 14: Data Field

 

 

014Ah

 

 

 

014Bh

 

 

 

 

014Ch

 

 

 

 

014Dh

 

 

 

 

014Eh

CAN0 Message Box 14: Time Stamp

 

 

014Fh

 

200

0150h

 

 

201

0151h

 

 

 

0152h

CAN0 Message Box 15: Identifier /DLC

 

 

0153h

 

 

0154h

 

 

 

0155h

 

 

 

0156h

 

 

 

0157h

 

 

 

0158h

 

 

 

0159h

CAN0 Message Box 15: Data Field

 

 

015Ah

 

 

015Bh

 

 

 

015Ch

 

 

 

015Dh

 

 

 

015Eh

CAN0 Message Box 15: Time Stamp

 

 

015Fh

 

 

0160h

 

 

 

0161h

 

 

 

0162h

CAN0 Global Mask Register

C0GMR

202

0163h

0164h

 

 

 

0165h

 

 

 

0166h

 

 

 

0167h

 

 

 

0168h

CAN0 Local Mask A Register

C0LMAR

202

0169h

016Ah

 

 

 

016Bh

 

 

 

016Ch

 

 

 

016Dh

 

 

 

016Eh

CAN0 Local Mask B Register

C0LMBR

202

016Fh

0170h

 

 

 

0171h

 

 

 

0172h

 

 

 

0173h

 

 

 

0174h

 

 

 

0175h

 

 

 

0176h

 

 

 

0177h

 

 

 

0178h

 

 

 

0179h

 

 

 

017Ah

 

 

 

017Bh

 

 

 

017Ch

 

 

 

017Dh

 

 

 

017Eh

 

 

 

017Fh

 

 

 

B-3

Address

Register

Symbol

Page

0180h

 

 

 

0181h

 

 

 

0182h

 

 

 

0183h

 

 

 

0184h

 

 

 

0185h

 

 

 

0186h

 

 

 

0187h

 

 

 

0188h

 

 

 

0189h

 

 

 

018Ah

 

 

 

018Bh

 

 

 

018Ch

 

 

 

018Dh

 

 

 

018Eh

 

 

 

018Fh

 

 

 

0190h

 

 

 

0191h

 

 

 

0192h

 

 

 

0193h

 

 

 

0194h

 

 

 

0195h

 

 

 

0196h

 

 

 

0197h

 

 

 

0198h

 

 

 

0199h

 

 

 

019Ah

 

 

 

019Bh

 

 

 

019Ch

 

 

 

019Dh

 

 

 

019Eh

 

 

 

019Fh

 

 

 

01A0h

 

 

 

01A1h

 

 

 

01A2h

 

 

 

01A3h

 

 

 

01A4h

 

 

 

01A5h

 

 

 

01A6h

 

 

 

01A7h

 

 

 

01A8h

 

 

 

01A9h

 

 

 

01AAh

 

 

 

01ABh

 

 

 

01ACh

 

 

 

01ADh

 

 

 

01AEh

 

 

 

01AFh

 

 

 

01B0h

 

 

 

01B1h

 

 

 

01B2h

 

 

 

01B3h

 

 

 

01B4h

 

 

 

01B5h

Flash Memory Control Register 1

FMR1

241

01B6h

 

 

 

01B7h

Flash Memory Control Register 0

FMR0

241

01B8h

 

 

 

01B9h

Address Match Interrupt Register 2

RMAD2

75

01BAh

 

 

 

01BBh

Address Match Interrupt Enable Register 2

AIER2

75

01BCh

 

 

 

01BDh

Address Match Interrupt Register 3

RMAD3

75

01BEh

 

 

 

01BFh

 

 

 

The blank areas are reserved.

Address

Register

Symbol

Page

01C0h

Timer B3, B4, B5 Count Start Flag

TBSR

107

01C1h

 

 

 

01C2h

Timer A1-1 Register

TA11

118

01C3h

01C4h

Timer A2-1 Register

TA21

118

01C5h

01C6h

Timer A4-1 Register

TA41

118

01C7h

01C8h

Three-Phase PWM Control Register 0

INVC0

115

01C9h

Three-Phase PWM Control Register 1

INVC1

116

01CAh

Three-Phase Output Buffer Register 0

IDB0

117

01CBh

Three-Phase Output Buffer Register 1

IDB1

117

01CCh

Dead Time Timer

DTT

117

01CDh

Timer B2 Interrupt Occurrence Frequency Set Counter

ICTB2

119

01CEh

 

 

 

01CFh

Interrupt Cause Select Register 2

IFSR2

72

01D0h

Timer B3 Register

TB3

116

01D1h

01D2h

Timer B4 Register

TB4

106

01D3h

01D4h

Timer B5 Register

TB5

106

01D5h

01D6h

SI/O6 Transmit/Receive Register

S6TRR

172

01D7h

 

 

 

01D8h

SI/O6 Control Register

S6C

172

01D9h

SI/O6 Bit Rate Generator

S6BRG

172

01DAh

SI/O3, 4, 5, 6 Transmit/Receive Register

S3456TRR

173

01DBh

Timer B3 Mode Register

TB3MR

106

 

 

 

108

01DCh

Timer B4 Mode Register

TB4MR

109

01DDh

Timer B5 Mode Register

TB5MR

111

01DEh

Interrupt Cause Select Register 0

IFSR0

70

01DFh

Interrupt Cause Select Register 1

IFSR1

71

01E0h

SI/O3 Transmit/Receive Register

S3TRR

172

01E1h

 

 

 

01E2h

SI/O3 Control Register

S3C

172

01E3h

SI/O3 Bit Rate Generator

S3BRG

172

01E4h

SI/O4 Transmit/Receive Register

S4TRR

172

01E5h

 

 

 

01E6h

SI/O4 Control Register

S4C

172

01E7h

SI/O4 Bit Rate Generator

S4BRG

172

01E8h

SI/O5 Transmit/Receive Register

S5TRR

172

01E9h

 

 

 

01EAh

SI/O5 Control Register

S5C

172

01EBh

SI/O5 Bit Rate Generator

S5BRG

172

01ECh

UART0 Special Mode Register 4

U0SMR4

133

01EDh

UART0 Special Mode Register 3

U0SMR3

132

01EEh

UART0 Special Mode Register 2

U0SMR2

132

01EFh

UART0 Special Mode Register

U0SMR

131

01F0h

UART1 Special Mode Register 4

U1SMR4

133

01F1h

UART1 Special Mode Register 3

U1SMR3

132

01F2h

UART1 Special Mode Register 2

U1SMR2

132

01F3h

UART1 Special Mode Register

U1SMR

131

01F4h

UART2 Special Mode Register 4

U2SMR4

133

01F5h

UART2 Special Mode Register 3

U2SMR3

132

01F6h

UART2 Special Mode Register 2

U2SMR2

132

01F7h

UART2 Special Mode Register

U2SMR

131

01F8h

UART2 Transmit/Receive Mode Register

U2MR

129

01F9h

UART2 Bit Rate Generator

U2BRG

128

01FAh

UART2 Transmit Buffer Register

U2TB

128

01FBh

01FCh

UART2 Transmit/Receive Control Register 0

U2C0

129

01FDh

UART2 Transmit/Receive Control Register 1

U2C1

130

01FEh

UART2 Receive Buffer Register

U2RB

128

01FFh

B-4

Address

Register

Symbol

Page

0200h

CAN0 Message Control Register 0

C0MCTL0

 

0201h

CAN0 Message Control Register 1

C0MCTL1

 

0202h

CAN0 Message Control Register 2

C0MCTL2

 

0203h

CAN0 Message Control Register 3

C0MCTL3

 

0204h

CAN0 Message Control Register 4

C0MCTL4

 

0205h

CAN0 Message Control Register 5

C0MCTL5

 

0206h

CAN0 Message Control Register 6

C0MCTL6

 

0207h

CAN0 Message Control Register 7

C0MCTL7

203

0208h

CAN0 Message Control Register 8

C0MCTL8

 

0209h

CAN0 Message Control Register 9

C0MCTL9

 

020Ah

CAN0 Message Control Register 10

C0MCTL10

 

020Bh

CAN0 Message Control Register 11

C0MCTL11

 

020Ch

CAN0 Message Control Register 12

C0MCTL12

 

020Dh

CAN0 Message Control Register 13

C0MCTL13

 

020Eh

CAN0 Message Control Register 14

C0MCTL14

 

020Fh

CAN0 Message Control Register 15

C0MCTL15

 

0210h

CAN0 Control Register

C0CTLR

204

0211h

 

 

 

0212h

CAN0 Status Register

C0STR

206

0213h

0214h

CAN0 Slot Status Register

C0SSTR

207

0215h

0216h

CAN0 Interrupt Control Register

C0ICR

207

0217h

0218h

CAN0 Extended ID Register

C0IDR

207

0219h

021Ah

CAN0 Configuration Register

C0CONR

208

021Bh

021Ch

CAN0 Receive Error Count Register

C0RECR

209

021Dh

CAN0 Transmit Error Count Register

C0TECR

209

021Eh

CAN0 Time Stamp Register

C0TSR

209

021Fh

0220h

 

 

 

0221h

 

 

 

0222h

 

 

 

0223h

 

 

 

0224h

 

 

 

0225h

 

 

 

0226h

 

 

 

0227h

 

 

 

0228h

 

 

 

0229h

 

 

 

022Ah

 

 

 

022Bh

 

 

 

022Ch

 

 

 

022Dh

 

 

 

022Eh

 

 

 

022Fh

 

 

 

0230h

CAN1 Control Register

C1CTLR

205

0231h

0232h

 

 

 

0233h

 

 

 

0234h

 

 

 

0235h

 

 

 

0236h

 

 

 

0237h

 

 

 

0238h

 

 

 

0239h

 

 

 

023Ah

 

 

 

023Bh

 

 

 

023Ch

 

 

 

023Dh

 

 

 

023Eh

 

 

 

023Fh

 

 

 

The blank areas are reserved.

Address

Register

Symbol

Page

0240h

 

 

 

0241h

 

 

 

0242h

CAN0 Acceptance Filter Support Register

C0AFS

209

0243h

 

 

 

0244h

 

 

 

0245h

 

 

 

0246h

 

 

 

0247h

 

 

 

0248h

 

 

 

0249h

 

 

 

024Ah

 

 

 

024Bh

 

 

 

024Ch

 

 

 

024Dh

 

 

 

024Eh

 

 

 

024Fh

 

 

 

0250h

 

 

 

0251h

 

 

 

0252h

 

 

 

0253h

 

 

 

0254h

 

 

 

0255h

 

 

 

0256h

 

 

 

0257h

 

 

 

0258h

 

 

 

0259h

 

 

 

025Ah

 

 

 

025Bh

 

 

 

025Ch

 

 

 

025Dh

 

 

 

025Eh

Peripheral Clock Select Register

PCLKR

36

025Fh

CAN0 Clock Select Register

CCLKR

37

0260h

 

 

 

0261h

 

 

 

0262h

 

 

 

0263h

 

 

 

0264h

 

 

 

0265h

 

 

 

0266h

 

 

 

0267h

 

 

 

0268h

 

 

 

0269h

 

 

 

026Ah

 

 

 

026Bh

 

 

 

026Ch

 

 

 

026Dh

 

 

 

026Eh

 

 

 

026Fh

 

 

 

0270h

 

 

 

to

 

 

 

0372h

 

 

 

0373h

 

 

 

0374h

 

 

 

0375h

 

 

 

0376h

 

 

 

0377h

 

 

 

0378h

 

 

 

0379h

 

 

 

037Ah

 

 

 

037Bh

 

 

 

037Ch

 

 

 

037Dh

 

 

 

037Eh

 

 

 

037Fh

 

 

 

B-5

Address

Register

Symbol

 

Page

0380h

Count Start Flag

TABSR

92,107,120

0381h

Clock Prescaler Reset Flag

CPSRF

 

93,107

0382h

One-Shot Start Flag

ONSF

 

93

 

0383h

Trigger Select Register

TRGSR

 

93,120

0384h

Up/Down Flag

UDF

 

92

 

0385h

 

 

 

 

 

 

0386h

Timer A0 Register

TA0

 

91

 

0387h

 

 

0388h

Timer A1 Register

TA1

 

91

 

0389h

 

118

 

038Ah

Timer A2 Register

TA2

 

91

 

038Bh

 

118

 

038Ch

Timer A3 Register

TA3

 

91

 

038Dh

 

 

038Eh

Timer A4 Register

TA4

 

91

 

038Fh

 

118

 

0390h

Timer B0 Register

TB0

 

106

 

0391h

 

 

0392h

Timer B1 Register

TB1

 

106

 

0393h

 

 

0394h

Timer B2 Register

TB2

 

106

 

0395h

 

118

 

0396h

Timer A0 Mode Register

TA0MR

91

 

 

 

0397h

Timer A1 Mode Register

TA1MR

94

 

121

0398h

Timer A2 Mode Register

TA2MR

96

 

98,121

0399h

Timer A3 Mode Register

TA3MR

101

 

98

 

039Ah

Timer A4 Mode Register

TA4MR

103

 

98,121

039Bh

Timer B0 Mode Register

TB0MR

106,108

 

039Ch

Timer B1 Mode Register

TB1MR

109,111

 

039Dh

Timer B2 Mode Register

TB2MR

 

 

121

039Eh

Timer B2 Special Mode Register

TB2SC

 

119

 

039Fh

 

 

 

 

 

 

03A0h

UART0 Transmit/Receive Mode Register

U0MR

 

129

 

03A1h

UART0 Bit Rate Generator

U0BRG

 

128

 

03A2h

UART0 Transmit Buffer Register

U0TB

 

128

 

03A3h

 

 

03A4h

UART0 Transmit/Receive Control Register 0

U0C0

 

129

 

03A5h

UART0 Transmit/Receive Control Register 1

U0C1

 

130

 

03A6h

UART0 Receive Buffer Register

U0RB

 

128

 

03A7h

 

 

03A8h

UART1 Transmit/Receive Mode Register

U1MR

 

129

 

03A9h

UART1 Bit Rate Generator

U1BRG

 

128

 

03AAh

UART1 Transmit Buffer Register

U1TB

 

128

 

03ABh

 

 

03ACh

UART1 Transmit/Receive Control Register 0

U1C0

 

129

 

03ADh

UART1 Transmit/Receive Control Register 1

U1C1

 

130

 

03AEh

UART1 Receive Buffer Register

U1RB

 

128

 

03AFh

 

 

03B0h

UART Transmit/Receive Control Register 2

UCON

 

131

 

03B1h

 

 

 

 

 

 

03B2h

 

 

 

 

 

 

03B3h

 

 

 

 

 

 

03B4h

 

 

 

 

 

 

03B5h

 

 

 

 

 

 

03B6h

 

 

 

 

 

 

03B7h

 

 

 

 

 

 

03B8h

DMA0 Request Cause Select Register

DM0SL

 

80

 

03B9h

 

 

 

 

 

 

03BAh

DMA1 Request Cause Select Register

DM1SL

 

81

 

03BBh

 

 

 

 

 

 

03BCh

CRC Data Register

CRCD

 

196

 

03BDh

 

 

 

 

 

 

 

 

03BEh

CRC Input Register

CRCIN

 

196

 

03BFh

 

 

 

 

 

 

The blank areas are reserved.

Address

Register

Symbol

Page

03C0h

A/D Register 0

AD0

 

03C1h

 

 

 

03C2h

A/D Register 1

AD1

 

03C3h

 

 

 

03C4h

A/D Register 2

AD2

 

03C5h

 

 

 

03C6h

A/D Register 3

AD3

 

03C7h

180

 

03C8h

A/D Register 4

AD4

 

03C9h

 

 

 

03CAh

A/D Register 5

AD5

 

03CBh

 

 

 

03CCh

A/D Register 6

AD6

 

03CDh

 

 

 

03CEh

A/D Register 7

AD7

 

03CFh

 

 

 

03D0h

 

 

 

03D1h

 

 

 

03D2h

 

 

 

03D3h

 

 

 

03D4h

A/D Control Register 2

ADCON2

180

03D5h

 

 

 

03D6h

A/D Control Register 0

ADCON0

179,182,184

03D7h

A/D Control Register 1

ADCON1

186,188,190

03D8h

D/A Register 0

DA0

195

03D9h

 

 

 

03DAh

D/A Register 1

DA1

195

03DBh

 

 

 

03DCh

D/A Control Register

DACON

195

03DDh

 

 

 

03DEh

Port P14 Control Register

PC14

231

03DFh

Pull-Up Control Register 3

PUR3

233

03E0h

Port P0 Register

P0

231

03E1h

Port P1 Register

P1

231

03E2h

Port P0 Direction Register

PD0

230

03E3h

Port P1 Direction Register

PD1

230

03E4h

Port P2 Register

P2

231

03E5h

Port P3 Register

P3

231

03E6h

Port P2 Direction Register

PD2

230

03E7h

Port P3 Direction Register

PD3

230

03E8h

Port P4 Register

P4

231

03E9h

Port P5 Register

P5

231

03EAh

Port P4 Direction Register

PD4

230

03EBh

Port P5 Direction Register

PD5

230

03ECh

Port P6 Register

P6

231

03EDh

Port P7 Register

P7

231

03EEh

Port P6 Direction Register

PD6

230

03EFh

Port P7 Direction Register

PD7

230

03F0h

Port P8 Register

P8

231

03F1h

Port P9 Register

P9

231

03F2h

Port P8 Direction Register

PD8

230

03F3h

Port P9 Direction Register

PD9

230

03F4h

Port P10 Register

P10

231

03F5h

Port P11 Register

P11

231

03F6h

Port P10 Direction Register

PD10

230

03F7h

Port P11 Direction Register

PD11

230

03F8h

Port P12 Register

P12

231

03F9h

Port P13 Register

P13

231

03FAh

Port P12 Direction Register

PD12

230

03FBh

Port P13 Direction Register

PD13

230

03FCh

Pull-up Control Register 0

PUR0

232

03FDh

Pull-up Control Register 1

PUR1

232

03FEh

Pull-up Control Register 2

PUR2

232

03FFh

Port Control Register

PCR

233

B-6

Under development

This document is under development and its contents are subject to change

M16C/6N Group (M16C/6NL, M16C/6NN)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.02

Jul 01, 2005

1. Overview

The M16C/6N Group (M16C/6NL, M16C/6NN) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with one CAN (Controller Area Network) module in M16C/6N Group (M16C/6NL, M16C/6NN), the microcomputer is suited to car audio and industrial control systems. The CAN module complies with the 2.0B specification. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA and communication equipment which requires high-speed arithmetic/logic operations.

1.1 Applications

Car audio and industrial control systems, other

Rev.1.02 Jul 01, 2005 page 1 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

1.2 Performance Outline

Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN).

Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NL)

 

Item

 

Performance

 

 

 

 

CPU

Number of Basic Instructions

91 instructions

 

 

 

 

 

Minimum Instruction Execution Time

41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

 

 

 

 

 

Operation Mode

Single-chip mode

 

 

 

 

 

 

Address Space

 

1 Mbyte

 

 

 

 

 

Memory Capacity

See Table 1.3 Product List

Peripheral

Port

 

Input/Output: 87 pins, Input: 1 pin

 

 

 

 

Function

Multifunction Timer

Timer A: 16 bits 5 channels

 

 

 

 

Timer B: 16 bits 6 channels

 

 

 

 

Three-phase motor control circuit

 

Serial I/O

 

3 channels

 

 

 

 

Clock synchronous, UART, I2C-bus (1), IEBus (2)

 

 

 

 

2 channels

 

 

 

 

Clock synchronous

 

A/D Converter

 

10-bit A/D converter: 1 circuit, 26 channels

 

 

 

 

 

 

D/A Converter

 

8 bits 2 channels

 

 

 

 

 

 

DMAC

 

2 channels

 

 

 

 

 

CRC Calculation Circuit

CRC-CCITT

 

CAN Module

 

1 channel with 2.0B specification

 

 

 

 

 

Watchdog Timer

15 bits 1 channel (with prescaler)

 

 

 

 

 

 

Interrupt

 

Internal: 30 sources, External: 9 sources

 

 

 

 

Software: 4 sources, Priority level: 7 levels

 

 

 

 

 

Clock Generating Circuit

4 circuits

 

 

 

 

• Main clock oscillation circuit (*)

 

 

 

 

• Sub clock oscillation circuit (*)

 

 

 

 

• On-chip oscillator

 

 

 

 

• PLL frequency synthesizer

 

 

 

 

(*) Equipped with a built-in feedback resistor

 

 

 

 

 

Oscillation Stop Detection

Main clock oscillation stop and re-oscillation detection function

 

Function

 

 

 

 

 

 

 

Electrical

Supply Voltage

 

VCC = 3.0 to 5.5V

Characteristics

 

 

 

(f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

 

 

 

 

 

 

Power

 

Mask ROM

19mA (f(BCLK) = 24MHz, PLL operation, no division)

 

 

 

 

 

 

Consumption

 

Flash Memory

21mA (f(BCLK) = 24MHz, PLL operation, no division)

 

 

 

 

 

 

 

 

Mask ROM

3µA (f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

 

 

 

 

 

 

 

 

Flash Memory

0.8µA (Stop mode, Topr = 25°C)

Flash Memory

Program/Erase Supply Voltage

3.3 ± 0.3V or 5.0 ± 0.5V

Version

Program and Erase Endurance

100 times

 

 

 

 

I/O

I/O Withstand Voltage

5.0V

 

 

 

 

 

Characteristics

Output Current

 

5mA

Operating Ambient Temperature

-40 to 85°C

 

 

 

 

 

Device Configuration

 

CMOS high performance silicon gate

 

 

 

 

 

Package

 

 

 

100-pin plastic mold LQFP

NOTES:

 

 

 

 

1.I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2.IEBus is a registered trademark of NEC Electronics Corporation.

Rev.1.02 Jul 01, 2005 page 2 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NN)

 

 

 

 

 

 

 

 

 

Item

 

Performance

 

 

 

 

 

 

 

 

CPU

Number of Basic Instructions

91 instructions

 

 

 

 

 

 

 

 

 

Minimum Instruction Execution Time

41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

 

 

 

 

 

 

 

 

 

Operation Mode

Single-chip mode

 

 

 

 

 

 

 

 

 

 

Address Space

 

1 Mbyte

 

 

 

 

 

 

 

 

 

Memory Capacity

See Table 1.3 Product List

 

 

 

 

 

 

 

 

 

Peripheral

Port

 

Input/Output: 113 pins, Input: 1 pin

 

 

 

 

 

 

 

 

Function

Multifunction Timer

Timer A: 16 bits 5 channels

 

 

 

 

 

 

Timer B: 16 bits 6 channels

 

 

 

 

 

 

Three-phase motor control circuit

 

 

 

 

 

 

 

 

 

 

Serial I/O

 

3 channels

 

 

 

 

 

 

Clock synchronous, UART, I2C-bus (1), IEBus (2)

 

 

 

 

 

 

4 channels

 

 

 

 

 

 

Clock synchronous

 

 

 

 

 

 

 

 

 

 

A/D Converter

 

10-bit A/D converter: 1 circuit, 26 channels

 

 

 

 

 

 

 

 

 

 

D/A Converter

 

8 bits 2 channels

 

 

 

 

 

 

 

 

 

 

DMAC

 

2 channels

 

 

 

 

 

 

 

 

 

CRC Calculation Circuit

CRC-CCITT

 

 

 

 

 

 

 

 

 

 

CAN Module

 

1 channel with 2.0B specification

 

 

 

 

 

 

 

 

 

Watchdog Timer

15 bits 1 channel (with prescaler)

 

 

 

 

 

 

 

 

 

 

Interrupt

 

Internal: 32 sources, External: 12 sources

 

 

 

 

 

 

Software: 4 sources, Priority level: 7 levels

 

 

 

 

 

 

 

 

 

Clock Generating Circuit

4 circuits

 

 

 

 

 

 

• Main clock oscillation circuit (*)

 

 

 

 

 

 

• Sub clock oscillation circuit (*)

 

 

 

 

 

 

• On-chip oscillator

 

 

 

 

 

 

• PLL frequency synthesizer

 

 

 

 

 

 

(*) Equipped with a built-in feedback resistor

 

 

 

 

 

 

 

 

 

Oscillation Stop Detection

Main clock oscillation stop and re-oscillation detection function

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

Electrical

Supply Voltage

 

VCC = 3.0 to 5.5V

 

 

Characteristics

 

 

 

(f(BCLK) = 24MHz, 1/1 prescaler, without software wait)

 

 

 

 

 

 

 

 

 

 

Power

 

Mask ROM

19mA (f(BCLK) = 24MHz, PLL operation, no division)

 

 

 

 

 

 

 

 

 

 

Consumption

 

Flash Memory

21mA (f(BCLK) = 24MHz, PLL operation, no division)

 

 

 

 

 

 

 

 

 

 

 

 

Mask ROM

3µA (f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

 

 

 

 

 

 

 

 

 

 

 

 

Flash Memory

0.8µA (Stop mode, Topr = 25°C)

 

 

 

 

 

 

 

 

Flash Memory

Program/Erase Supply Voltage

3.3 ± 0.3V or 5.0 ± 0.5V

 

 

 

 

 

 

 

 

Version

Program and Erase Endurance

100 times

 

 

 

 

 

 

 

 

I/O

I/O Withstand Voltage

5.0V

 

 

 

 

 

 

 

 

 

Characteristics

Output Current

 

5mA

 

 

Operating Ambient Temperature

-40 to 85°C

 

 

 

 

 

 

 

 

 

Device Configuration

 

CMOS high performance silicon gate

 

 

 

 

 

 

 

 

 

Package

 

 

 

128-pin plastic mold LQFP

 

NOTES:

 

 

 

 

 

1.I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2.IEBus is a registered trademark of NEC Electronics Corporation.

Rev.1.02 Jul 01, 2005 page 3 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

1.3 Block Diagram

Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN).

 

8

 

 

8

 

 

8

 

 

8

 

 

8

 

 

8

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port P0

 

Port P1

 

Port P2

 

Port P3

 

Port P4

 

Port P5

 

Port P6

 

Internal peripheral functions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A/D converter

 

 

 

System clock generating circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(10 bits 8 channels

 

 

 

 

 

 

XIN-XOUT

 

 

 

 

 

Expandable up to 26 channels)

 

 

 

 

 

XCIN-XCOUT

 

 

Timer (16 bits)

 

 

 

 

 

 

 

 

 

 

 

PLL frequency synthesizer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

On-chip oscillator

 

 

Output (timer A): 5

 

 

 

 

UART or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock synchronous serial I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock synchronous serial I/O

 

 

Input (timer B): 6

 

 

 

 

(3 channels)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(8 bits 4 channels) (4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Three-phase motor

 

 

CRC arithmetic circuit (CCITT)

 

 

 

 

 

CAN module

 

 

control circuit

 

 

(Polynomial: X16+X12+X5+1)

 

 

 

 

 

 

(1 channel)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Watchdog timer

 

 

M16C/60 series CPU core

 

 

 

 

 

 

 

Memory

 

 

(15 bits)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R0H

 

R0L

 

 

 

 

SB

 

 

 

 

 

 

 

 

ROM (1)

 

 

 

 

 

R1H

 

R1L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USP

 

 

 

 

 

 

 

 

 

 

 

 

 

DMAC

 

 

R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAM (2)

 

 

(2 channels)

 

 

R3

 

 

 

 

 

ISP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D/A converter

 

 

A1

 

 

 

 

PC

 

 

 

 

 

 

 

Multiplier

 

 

 

 

 

FB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(8 bits 2 channels)

 

 

 

 

 

 

 

 

 

FLG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port P14

 

Port P13

 

Port P12

 

 

 

 

 

 

 

 

 

 

 

 

 

(3)

 

 

 

 

(3)

 

 

(3)

 

NOTES:

 

 

 

 

 

 

 

2

 

 

 

 

8

 

 

8

 

1: ROM size depends on microcomputer type.

 

 

 

 

 

 

 

 

 

 

 

 

2:RAM size depends on microcomputer type.

3:Ports P11 to P14 are only in the 128-pin version.

4:8 bits 2 channels in the 100-pin version.

P7Port

 

 

8

 

P8Port

 

 

7

 

5 P8Port

 

 

 

 

P9Port

 

 

8

 

P10Port

 

 

8

 

Port P11

(3)

8

Figure 1.1 Block Diagram

Rev.1.02 Jul 01, 2005 page 4 of 314 REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

1.4 Product List

Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.2 shows the type numbers, memory sizes and packages.

Table 1.3 Product List

 

 

 

 

 

 

As of Jul. 2005

Type No.

 

ROM Capacity

RAM Capacity

Package Type

Remarks

 

 

 

 

 

 

 

 

M306NLFHGP

 

384

K + 4 Kbytes

31

Kbytes

PLQP0100KB-A

Flash memory

 

 

 

 

 

 

 

 

M306NNFHGP

 

 

 

 

 

PLQP0128KB-A

version

 

 

 

 

 

 

 

 

M306NLFJGP

(D)

512

K + 4 Kbytes

31

Kbytes

PLQP0100KB-A

 

 

 

 

 

 

 

 

 

M306NNFJGP

 

 

 

 

 

PLQP0128KB-A

 

 

 

 

 

 

 

 

 

M306NLME-XXXGP

 

192

Kbytes

16

Kbytes

PLQP0100KB-A

Mask ROM version

 

 

 

 

 

 

 

 

M306NNME-XXXGP

 

 

 

 

 

PLQP0128KB-A

 

 

 

 

 

 

 

 

 

M306NLMG-XXXGP

 

256

Kbytes

20

Kbytes

PLQP0100KB-A

 

 

 

 

 

 

 

 

 

M306NNMG-XXXGP

 

 

 

 

 

PLQP0128KB-A

 

 

 

 

 

 

 

 

 

(D): Under development

 

 

 

 

 

 

 

Type No. M30 6N L M G - XXX GP

Package type:

GP: Package PLQP0100KB-A, PLQP0128KB-A

ROM No.

Omitted on flash memory version

ROM capacity:

E : 192 Kbytes

G: 256 Kbytes

H : 384 Kbytes

J : 512 Kbytes

Memory type:

M : Mask ROM version

F : Flash memory version

Shows the number of CAN module, pin count, etc.

6N Group

M16C Family

Figure 1.2 Type No., Memory Size, and Package

Rev.1.02 Jul 01, 2005 page 5 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

1.5 Pin Configuration

Figures 1.3 and 1.4 show the pin configuration (top view).

PIN CONFIGURATION (top view)

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

VCC2

P3_0

VSS

P2_7/AN2_7

P2_6/AN2_6

P2_5/AN2_5

P2_4/AN2_4

P2_3/AN2_3

P2_2/AN2_2

P2_1/AN2_1

P2_0/AN2_0

P1_7/INT5

P1_6/INT4

P1_5/INT3

P1_4

P1_3

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P1_2 76

P1_1 77

P1_0 78

P0_7/AN0_7 79

P0_6/AN0_6 80

P0_5/AN0_5 81

P0_4/AN0_4 82

P0_3/AN0_3 83

P0_2/AN0_2 84

P0_1/AN0_1 85

P0_0/AN0_0 86

P10_7/AN7/KI3 87

P10_6/AN6/KI2 88

P10_5/AN5/KI1 89

P10_4/AN4/KI0 90

P10_3/AN3 91

P10_2/AN2 92

P10_1/AN1 93

AVSS 94

P10_0/AN0 95

VREF 96

AVCC 97

P9_7/ADTRG/SIN4 98

P9_6/ANEX1/CTX0/SOUT4 99

P9_5/ANEX0/CRX0/CLK4 100

1 2 3 4

P9_4/DA1/TB4IN P9_3/DA0/TB3IN _2/TB2IN/SOUT3

P9_1/TB1IN/SIN3

P9

(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

P4_2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

 

 

 

P4_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

 

 

 

P4_4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

47

 

 

 

P4_5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

 

 

 

P4_6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

45

 

 

 

P4_7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

 

 

P5_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

43

 

 

 

P5_1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

 

 

 

P5_2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

41

 

 

 

P5_3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M16C/6N Group

40

 

 

 

P5_4

 

 

 

 

 

 

 

 

 

39

 

 

 

P5_5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(M16C/6NL)

38

 

 

 

P5_6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

 

 

 

P5_7/CLKOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

P6_0/CTS0/RTS0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

 

 

P6_1/CLK0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

 

 

P6_2/RXD0/SCL0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

P6_3/TXD0/SDA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

P6_4/CTS1/RTS1/CTS0/CLKS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

P6_5/CLK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

 

 

P6_6/RXD1/SCL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

P6_7/TXD1/SDA1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

P7_0/TXD2/SDA2/TA0OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

P7_1/RXD2/SCL2/TA0IN/TB5IN (1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

P7_2/CLK2/TA1OUT/V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P9 0/TB0IN/CLK3

BYTE

CNVSS

P8 7/XCIN

P8 6/XCOUT

RESET XOUT VSS XIN VCC1 P8 5/NMI P8 4/INT2/ZP P8 3/INT1 P8 2/INT0 P8 1/TA4IN/U P8 0/TA4OUT/U/(SIN4) P7 7/TA3IN P7 6/TA3OUT P7 5/TA2IN/W/(SOUT4) P7 4/TA2OUT/W/(CLK4)

P7 3/CTS2/RTS2/TA1IN/V

 

 

 

NOTE:

Package: PLQP0100KB-A

1. P7_1 and P9_1 are N channel open-drain pins.

 

 

Figure 1.3

Pin Configuration (Top View) (1)

Rev.1.02 Jul 01, 2005 page 6 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

PIN CONFIGURATION (top view)

P1_1

P1_2

P1_3 P1_4 P1_5/INT3 P1_6/INT4 P1_7/INT5 P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_3/AN2_3 P2_4/AN2_4 P2_5/AN2_5 P2_6/AN2_6 P2_7/AN2_7 VSS P3_0 VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 P4_2 P4_3 P4_4 P4_5 P4_6 P4_7

 

 

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72 71 70 69 68 67 66 65

 

P1_0

103

 

64

P12_5

P0_7/AN0_7

104

 

63

P12_6

P0_6/AN0_6

105

 

62

P12_7

P0_5/AN0_5

106

 

61

P5_0

P0_4/AN0_4

107

 

60

P5_1

P0_3/AN0_3

108

 

59

P5_2

P0_2/AN0_2

109

 

58

P5_3

P0_1/AN0_1

110

 

57

P13_0

P0_0/AN0_0

111

 

56

P13_1

P11_7/SIN6

112

 

55

P13_2

P11_6/SOUT6

113

 

54

P13_3

P11_5/CLK6

114

M16C/6N Group

53

P5_4

P11_4

115

52

P5_5

 

 

 

 

P11_3

116

(M16C/6NN)

51

P5_6

P11_2/SOUT5

117

50

P5_7/CLKOUT

P11_1/SIN5

118

 

49

P13_4

P11_0/CLK5

119

 

48

P13_5/INT6

P10_7/AN7/KI3

120

 

47

P13_6/INT7

P10_6/AN6/KI2

121

 

46

P13_7/INT8

P10_5/AN5/KI1

122

 

45

P6_0/CTS0/RTS0

P10_4/AN4/KI0

123

 

44

P6_1/CLK0

P10_3/AN3

124

 

43

P6_2/RXD0/SCL0

P10_2/AN2

125

 

42

P6_3/TXD0/SDA0

P10_1/AN1

126

 

41

P6_4/CTS1/RTS1/CTS0/CLKS1

AVSS

127

 

40

P6_5/CLK1

P10_0/AN0

128

 

39

VSS

1 2

VREF

AVCC

3 4 5

P9 7/ADTRG/SIN4

P96/ANEX1/CTX0/SOUT4 P95/ANEX0/CRX0/CLK4

6

P9 4/DA1/TB4IN_

7 8 9

P9_3/DA0/TB3IN _2/TB2IN/SOUT3

P9_1/TB1IN/SIN3

P9

(1)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

P90/TB0IN/CLK3 P141 P140 BYTE CNVSS P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC1 P85/NMI P84/INT2/ZP P83/INT1 P82/INT0 P81/TA4IN/U 0/TA4OUT/U/(SIN4)

P77/TA3IN P76/TA3OUT

P8_

 

30 31 32 33 34 35 36 37 38

P75/TA2IN/W/(SOUT4) P74/TA2OUT/W/(CLK4) P73/CTS2/RTS2/TA1IN/V

P7 2/CLK2/TA1OUT/V 1/RXD2/SCL2/TA0IN/TB5IN P7 0/TXD2/SDA2/TA0OUT P6 7/TXD1/SDA1

VCC1

P6 6/RXD1/SCL1

 

P7_

 

 

 

(1)

 

 

NOTE:

Package: PLQP0128KB-A

1. P7_1 and P9_1 are N channel open-drain pins.

Figure 1.4 Pin Configuration (Top View) (2)

Rev.1.02 Jul 01, 2005 page 7 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

1.6 Pin Description

Tables 1.4 and 1.5 list the pin descriptions.

Table 1.4

Pin Description (100-pin and 128-pin Versions) (1)

Signal Name

Pin Name

 

I/O Type

Description

 

 

 

 

 

Power supply

VCC1, VCC2,

 

I

Apply 3.0 to 5.5V to the VCC1 and VCC2 pins and 0V to the

input

 

VSS

 

 

 

VSS pin. The VCC apply condition is that VCC2 = VCC1 (1).

 

 

 

 

 

Analog power

AVCC, AVSS

 

I

Applies the power supply for the A/D converter. Connect the

supply input

_____________

 

 

AVCC pin to VCC1. Connect the AVSS pin to VSS.

Reset input

 

 

The microcomputer is in a reset state when applying “L” to the

RESET

 

I

 

 

 

 

 

 

this pin.

 

 

 

 

 

 

CNVSS

 

CNVSS

 

I

Connect this pin to VSS.

External data

BYTE

 

 

I

Connect this pin to VSS.

bus width

 

 

 

 

 

 

select input

 

 

 

 

 

 

 

 

 

 

 

Main clock

XIN

 

 

I

I/O pins for the main clock oscillation circuit. Connect a ceramic

input

 

 

 

 

 

resonator or crystal oscillator between XIN and XOUT (2).

 

 

 

 

 

To use the external clock, input the clock from XIN and leave

Main clock

XOUT

 

 

O

output

 

 

 

 

 

XOUT open.

 

 

 

 

 

 

 

Sub clock

 

XCIN

 

 

I

I/O pins for a sub clock oscillation circuit. Connect a crystal

input

 

 

 

 

 

oscillator between XCIN and XCOUT (2).

Sub clock

 

XCOUT

 

O

To use the external clock, input the clock from XCIN and leave

output

 

 

 

 

 

XCOUT open.

 

 

 

 

 

Clock output

CLKOUT

 

O

The clock of the same cycle as fC, f8, or f32 is output.

______

 

________

________

 

 

______

INT interrupt input

INT0 to INT8 (3)

 

I

Input pins for the INT interrupt.

_______

 

________

 

 

 

_______

NMI interrupt

NMI

 

 

I

Input pin for the NMI interrupt.

input

 

______

______

 

 

 

Key input

 

 

 

Input pins for the key input interrupt.

 

KI0 to KI3

 

I

interrupt input

 

 

 

 

 

 

 

 

 

 

Timer A

 

TA0OUT to TA4OUT

I/O

These are timer A0 to timer A4 I/O pins.

 

 

 

 

 

 

 

TA0IN to TA4IN

I

These are timer A0 to timer A4 input pins.

 

 

 

 

 

 

 

 

 

ZP

 

 

I

Input pin for the Z-phase.

Timer B

 

TB0IN to TB5IN

I

These are timer B0 to timer B5 input pins.

Three-phase motor

___

___

____

 

These are Three-phase motor control output pins.

U, U, V, V, W, W

O

control output

__________

__________

 

 

Serial I/O

 

I

These are send control input pins.

 

CTS0 to CTS2

 

 

 

__________

__________

O

These are receive control output pins.

 

 

RTS0 to RTS2

 

 

 

CLK0 to CLK6 (3)

I/O

These are transfer clock I/O pins.

 

 

RXD0 to RXD2

I

These are serial data input pins.

 

 

SIN3 to SIN6 (3)

 

I

These are serial data input pins.

 

 

TXD0 to TXD2

 

O

These are serial data output pins.

 

 

SOUT3 to SOUT6 (3)

O

These are serial data output pins.

 

 

CLKS1

 

O

This is output pin for transfer clock output from multiple pins function.

I2C mode

 

SDA0 to SDA2

I/O

These are serial data I/O pins.

 

 

SCL0 to SCL2

 

I/O

These are transfer clock I/O pins. (except SCL2 for the

 

 

 

 

 

 

N-channel open drain output.)

 

 

 

 

 

 

I: Input

O: Output

I/O: Input/Output

NOTES:

1.In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2.Ask the oscillator maker the oscillation characteristic.

________ ________

3. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.

Rev.1.02 Jul 01, 2005 page 8 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

1. Overview

Table 1.5

Pin Description (100-pin and 128-pin Versions) (2)

 

 

 

 

 

 

 

Signal Name

Pin Name

I/O Type

Description

 

 

 

 

 

 

 

 

 

 

Reference

 

VREF

 

I

Applies the reference voltage for the A/D converter and D/A

 

 

voltage input

 

 

 

converter.

 

 

 

 

 

 

 

 

 

A/D converter

AN0 to AN7

 

I

Analog input pins for the A/D converter.

 

 

 

 

AN0_0 to AN0_7

 

 

 

 

 

 

AN2_0 to AN2_7

 

 

 

 

 

 

_____________

 

 

 

 

 

 

 

ADTRG

 

I

This is an A/D trigger input pin.

 

 

 

 

ANEX0

 

I/O

This is the extended analog input pin for the A/D converter,

 

 

 

 

 

 

 

and is the output in external op-amp connection mode.

 

 

 

 

 

 

 

 

 

 

 

 

ANEX1

 

I

This is the extended analog input pin for the A/D converter.

 

 

 

 

 

 

 

 

 

D/A converter

DA0, DA1

 

O

These are the output pins for the D/A converter.

 

 

 

 

 

 

 

 

 

CAN module

CRX0

 

I

This is the input pin for the CAN module.

 

 

 

 

 

 

 

 

 

 

 

 

CTX0

 

O

This is the output pin for the CAN module.

 

 

 

 

 

 

 

 

 

I/O port

 

P0_0 to P0_7

I/O

8-bit I/O ports in CMOS, having a direction register to select

 

 

 

 

P1_0 to P1_7

 

an input or output.

 

 

 

 

P2_0 to P2_7

 

Each pin is set as an input port or output port. An input port

 

 

 

 

P3_0 to P3_7

 

can be set for a pull-up or for no pull-up in 4-bit unit by

 

 

 

 

P4_0 to P4_7

 

program.

 

 

 

 

P5_0 to P5_7

 

(except P7_1 and P9_1 for the N-channel open drain output.)

 

 

 

 

P6_0 to P6_7

 

 

 

 

 

 

P7_0 to P7_7

 

 

 

 

 

 

P8_0 to P8_4

 

 

 

 

 

 

P8_6, P8_7

 

 

 

 

 

 

 

P9_0 to P9_7

 

 

 

 

 

 

P10_0 to P10_7

 

 

 

 

 

 

P11_0 to P11_7 (1)

 

 

 

 

 

 

P12_0 to P12_7 (1)

 

 

 

 

 

 

P13_0 to P13_7 (1)

 

 

 

 

 

 

P14_0, P14_1 (1)

 

_______

 

 

Input port

 

P8_5

 

I

 

 

 

 

Input pin for the NMI interrupt.

 

 

 

 

 

 

 

Pin states can be read by the P8_5 bit in the P8 register.

 

 

 

 

 

 

 

 

 

I: Input

O: Output

I/O: Input/Output

NOTE:

1. Ports P11 to P14 are only in the 128-pin version.

Rev.1.02 Jul 01, 2005 page 9 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.

b31

b15

b8 b7

b0

R2

R0H (R0's high bits)

R0L (R0's low bits)

 

 

 

 

 

 

 

R3

R1H (R1's high bits)

R1L (R1's low bits)

 

 

 

 

 

 

 

 

 

 

R2

 

 

 

 

 

 

 

 

 

R3

 

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

FB

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Registers (1)

Address Registers (1)

Frame Base Registers (1)

b19

b15

b0

INTBH

INTBL

 

Interrupt Table Register

 

 

 

 

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

 

 

 

 

 

b19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FLG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b15

b8 b7

 

 

 

 

 

 

 

 

 

 

 

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPL

 

 

 

 

 

 

 

 

 

U

I

O

B

S

Z

D

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

1. These registers comprise a register bank. There are two register banks.

Program Counter

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

Flag Register

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Register Bank Select Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

Reserved Area

Figure 2.1 CPU Registers

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0.

In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Rev.1.02 Jul 01, 2005 page 10 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

2. Central Processing Unit (CPU)

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is set to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”.

The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt request is enabled.

2.8.10 Reserved Area

When white to this bit, write “0”. When read, its content is indeterminate.

Rev.1.02 Jul 01, 2005 page 11 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

3. Memory

3. Memory

Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN). The address space extends the 1 Mbyte from address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to M16C/60 and M16C/20 Series Software Manual.

 

 

 

 

 

00000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SFR

 

 

 

 

 

 

 

 

 

 

 

 

 

00400h

 

FFE00h

 

 

 

 

 

 

 

 

 

 

 

 

Internal RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXXXXh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved area

 

 

Special page

 

 

 

 

 

 

0F000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal ROM

 

 

vector table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0FFFFh

(data area) (1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10000h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FFFDCh

 

Undefined instruction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved area

 

 

Overflow

 

Internal RAM

 

Internal ROM (1)

 

 

 

BRK instruction

 

Capacity

Address XXXXXh

 

Capacity

Address YYYYYh

 

 

 

 

Address match

 

16 Kbytes

043FFh

 

192 Kbytes

D0000h

 

 

 

 

Single step

 

 

 

 

 

 

YYYYYh

 

 

 

Oscillation stop and re-oscillation

 

20 Kbytes

053FFh

 

256 Kbytes

C0000h

 

 

 

detection / watchdog timer

 

31 Kbytes

07FFFh

 

384 Kbytes

A0000h

 

Internal ROM

 

 

DBC

 

 

 

(program area) (3)

 

 

NMI

 

 

 

 

512 Kbytes

80000h

FFFFFh

 

FFFFFh

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.As for the flash memory version, 4-Kbyte space (block A) exists.

2.Shown here is a memory map for the case where the PM13 bit in the PM1 register is "1".

If the PM13 bit is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

3.When using the masked ROM version, write nothing to internal ROM area.

Figure 3.1 Memory Map

Rev.1.02 Jul 01, 2005 page 12 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

4. Special Function Register (SFR)

SFR (Special Function Register) is the control register of peripheral functions.

Tables 4.1 to 4.12 list the SFR information.

Table 4.1 SFR Information (1)

Address

Register

Symbol

After Reset

0000h

 

 

 

0001h

 

 

 

0002h

 

 

 

0003h

 

 

 

0004h

Processor Mode Register 0

PM0

00h

0005h

Processor Mode Register 1

PM1

00001000b

0006h

System Clock Control Register 0

CM0

01001000b

0007h

System Clock Control Register 1

CM1

00100000b

0008h

 

 

 

0009h

Address Match Interrupt Enable Register

AIER

XXXXXX00b

000Ah

Protect Register

PRCR

XX000000b

000Bh

 

 

 

000Ch

Oscillation Stop Detection Register (1)

CM2

0X000000b

000Dh

 

 

 

000Eh

Watchdog Timer Start Register

WDTS

XXh

000Fh

Watchdog Timer Control Register

WDC

00XXXXXXb

0010h

Address Match Interrupt Register 0

RMAD0

00h

0011h

00h

0012h

 

 

X0h

0013h

 

 

 

0014h

Address Match Interrupt Register 1

RMAD1

00h

0015h

00h

0016h

 

 

X0h

0017h

 

 

 

0018h

 

 

 

0019h

 

 

 

001Ah

 

 

 

001Bh

 

 

 

001Ch

PLL Control Register 0

PLC0

0001X010b

001Dh

 

 

 

001Eh

Processor Mode Register 2

PM2

XXX00000b

001Fh

 

 

 

0020h

 

 

XXh

0021h

DMA0 Source Pointer

SAR0

XXh

0022h

 

 

XXh

0023h

 

 

 

0024h

 

 

XXh

0025h

DMA0 Destination Pointer

DAR0

XXh

0026h

 

 

XXh

0027h

 

 

 

0028h

DMA0 Transfer Counter

TCR0

XXh

0029h

XXh

 

 

002Ah

 

 

 

002Bh

 

 

 

002Ch

DMA0 Control Register

DM0CON

00000X00b

002Dh

 

 

 

002Eh

 

 

 

002Fh

 

 

 

0030h

 

 

XXh

0031h

DMA1 Source Pointer

SAR1

XXh

0032h

 

 

XXh

0033h

 

 

 

0034h

 

 

XXh

0035h

DMA1 Destination Pointer

DAR1

XXh

0036h

 

 

XXh

0037h

 

 

 

0038h

DMA1 Transfer Counter

TCR1

XXh

0039h

XXh

 

 

003Ah

 

 

 

003Bh

 

 

 

003Ch

DMA1 Control Register

DM1CON

00000X00b

003Dh

 

 

 

003Eh

 

 

 

003Fh

 

 

 

X: Undefined

NOTES:

1.The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset.

2.The blank areas are reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 13 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.2 SFR Information (2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

Register

Symbol

After Reset

 

 

0040h

 

 

 

 

 

 

 

0041h

CAN0 Wake-up Interrupt Control Register

C01WKIC

XXXXX000b

 

 

 

0042h

CAN0 Successful Reception Interrupt Control Register

C0RECIC

XXXXX000b

 

 

 

0043h

CAN0 Successful Transmission Interrupt Control Register

C0TRMIC

XXXXX000b

 

 

 

0044h

INT3 Interrupt Control Register

INT3IC

XX00X000b

 

 

 

0045h

Timer B5 Interrupt Control Register

TB5IC

XXXXX000b

 

 

SI/O5 Interrupt Control Register (1)

S5IC

 

 

 

 

 

 

 

 

0046h

Timer B4 Interrupt Control Register

TB4IC

XXXXX000b

 

 

UART1 Bus Collision Detection Interrupt Control Register

U1BCNIC

 

 

 

 

 

 

 

 

0047h

Timer B3 Interrupt Control Register

TB3IC

XXXXX000b

 

 

UART0 Bus Collision Detection Interrupt Control Register

U0BCNIC

 

 

 

 

 

 

 

 

0048h

SI/O4 Interrupt Control Register

S4IC

XX00X000b

 

 

INT5 Interrupt Control Register

INT5IC

 

 

 

 

 

 

 

 

0049h

SI/O3 Interrupt Control Register

S3IC

XX00X000b

 

 

INT4 Interrupt Control Register

INT4IC

 

 

 

 

 

 

 

 

004Ah

UART2 Bus Collision Detection Interrupt Control Register

U2BCNIC

XXXXX000b

 

 

 

004Bh

DMA0 Interrupt Control Register

DM0IC

XXXXX000b

 

 

 

004Ch

DMA1 Interrupt Control Register

DM1IC

XXXXX000b

 

 

 

004Dh

CAN0 Error Interrupt Control Register

C01ERRIC

XXXXX000b

 

 

 

004Eh

A/D Conversion Interrupt Control Register

ADIC

XXXXX000b

 

 

Key Input Interrupt Control Register

KUPIC

 

 

 

 

 

 

 

 

004Fh

UART2 Transmit Interrupt Control Register

S2TIC

XXXXX000b

 

 

 

0050h

UART2 Receive Interrupt Control Register

S2RIC

XXXXX000b

 

 

 

0051h

UART0 Transmit Interrupt Control Register

S0TIC

XXXXX000b

 

 

 

0052h

UART0 Receive Interrupt Control Register

S0RIC

XXXXX000b

 

 

 

0053h

UART1 Transmit Interrupt Control Register

S1TIC

XXXXX000b

 

 

 

0054h

UART1 Receive Interrupt Control Register

S1RIC

XXXXX000b

 

 

 

0055h

Timer A0 Interrupt Control Register

TA0IC

XXXXX000b

 

 

 

0056h

Timer A1 Interrupt Control Register

TA1IC

XXXXX000b

 

 

 

0057h

Timer A2 Interrupt Control Register

TA2IC

XX00X000b

 

 

INT7 Interrupt Control Register (1)

INT7IC

 

 

 

 

 

 

 

 

0058h

Timer A3 Interrupt Control Register

TA3IC

XX00X000b

 

 

INT6 Interrupt Control Register (1)

INT6IC

 

 

 

 

 

 

 

 

0059h

Timer A4 Interrupt Control Register

TA4IC

XXXXX000b

 

 

 

005Ah

Timer B0 Interrupt Control Register

TB0IC

XXXXX000b

 

 

SI/O6 Interrupt Control Register (1)

S6IC

 

 

 

 

 

 

 

 

005Bh

Timer B1 Interrupt Control Register

TB1IC

XX00X000b

 

 

INT8 Interrupt Control Register (1)

INT8IC

 

 

 

 

 

 

 

 

005Ch

Timer B2 Interrupt Control Register

TB2IC

XXXXX000b

 

 

005Dh

INT0 Interrupt Control Register

INT0IC

XX00X000b

 

 

005Eh

INT1 Interrupt Control Register

INT1IC

XX00X000b

 

 

005Fh

INT2 Interrupt Control Register

INT2IC

XX00X000b

 

 

0060h

 

 

XXh

 

 

0061h

 

 

XXh

 

 

0062h

CAN0 Message Box 0: Identifier / DLC

 

XXh

 

 

0063h

 

XXh

 

 

 

 

 

 

0064h

 

 

XXh

 

 

0065h

 

 

XXh

 

 

0066h

 

 

XXh

 

 

 

0067h

 

 

XXh

 

 

0068h

 

 

XXh

 

 

0069h

CAN0 Message Box 0: Data Field

 

XXh

 

 

006Ah

 

XXh

 

 

 

 

 

 

006Bh

 

 

XXh

 

 

006Ch

 

 

XXh

 

 

006Dh

 

 

XXh

 

 

 

006Eh

CAN0 Message Box 0: Time Stamp

 

XXh

 

 

006Fh

 

XXh

 

 

 

 

 

 

 

0070h

 

 

XXh

 

 

0071h

 

 

XXh

 

 

0072h

CAN0 Message Box 1: Identifier / DLC

 

XXh

 

 

0073h

 

XXh

 

 

 

 

 

 

0074h

 

 

XXh

 

 

0075h

 

 

XXh

 

 

0076h

 

 

XXh

 

 

0077h

 

 

XXh

 

 

0078h

 

 

XXh

 

 

0079h

CAN0 Message Box 1: Data Field

 

XXh

 

 

007Ah

 

XXh

 

 

 

 

 

 

007Bh

 

 

XXh

 

 

007Ch

 

 

XXh

 

 

007Dh

 

 

XXh

 

 

 

007Eh

CAN0 Message Box 1: Time Stamp

 

XXh

 

 

007Fh

 

XXh

 

 

 

 

 

X: Undefined

NOTES:

1.These registers exist only in the 128-pin version.

2.The blank area is reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 14 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.3

SFR Information (3)

 

 

 

 

 

 

 

 

 

 

 

Address

 

Register

Symbol

After Reset

 

 

0080h

 

 

 

XXh

 

 

0081h

 

 

 

XXh

 

 

0082h

CAN0 Message Box 2: Identifier / DLC

 

XXh

 

 

0083h

 

XXh

 

 

 

 

 

 

 

0084h

 

 

 

XXh

 

 

0085h

 

 

 

XXh

 

 

0086h

 

 

 

XXh

 

 

0087h

 

 

 

XXh

 

 

0088h

 

 

 

XXh

 

 

0089h

CAN0 Message Box 2: Data Field

 

XXh

 

 

008Ah

 

XXh

 

 

 

 

 

 

 

008Bh

 

 

 

XXh

 

 

008Ch

 

 

 

XXh

 

 

008Dh

 

 

 

XXh

 

 

008Eh

CAN0 Message Box 2: Time Stamp

 

XXh

 

 

008Fh

 

XXh

 

 

 

 

 

 

 

0090h

 

 

 

XXh

 

 

0091h

 

 

 

XXh

 

 

0092h

CAN0 Message Box 3: Identifier / DLC

 

XXh

 

 

0093h

 

XXh

 

 

 

 

 

 

 

0094h

 

 

 

XXh

 

 

0095h

 

 

 

XXh

 

 

0096h

 

 

 

XXh

 

 

0097h

 

 

 

XXh

 

 

0098h

 

 

 

XXh

 

 

0099h

CAN0 Message Box 3: Data Field

 

XXh

 

 

009Ah

 

XXh

 

 

 

 

 

 

 

009Bh

 

 

 

XXh

 

 

009Ch

 

 

 

XXh

 

 

009Dh

 

 

 

XXh

 

 

009Eh

CAN0 Message Box 3: Time Stamp

 

XXh

 

 

009Fh

 

XXh

 

 

 

 

 

 

 

00A0h

 

 

 

XXh

 

 

00A1h

 

 

 

XXh

 

 

00A2h

CAN0 Message Box 4: Identifier / DLC

 

XXh

 

 

00A3h

 

XXh

 

 

 

 

 

 

 

00A4h

 

 

 

XXh

 

 

00A5h

 

 

 

XXh

 

 

00A6h

 

 

 

XXh

 

 

00A7h

 

 

 

XXh

 

 

00A8h

 

 

 

XXh

 

 

00A9h

CAN0 Message Box 4: Data Field

 

XXh

 

 

00AAh

 

XXh

 

 

 

 

 

 

 

00ABh

 

 

 

XXh

 

 

00ACh

 

 

 

XXh

 

 

00ADh

 

 

 

XXh

 

 

00AEh

CAN0 Message Box 4: Time Stamp

 

XXh

 

 

00AFh

 

XXh

 

 

 

 

 

 

 

00B0h

 

 

 

XXh

 

 

00B1h

 

 

 

XXh

 

 

00B2h

CAN0 Message Box 5: Identifier / DLC

 

XXh

 

 

00B3h

 

XXh

 

 

 

 

 

 

 

00B4h

 

 

 

XXh

 

 

00B5h

 

 

 

XXh

 

 

00B6h

 

 

 

XXh

 

 

00B7h

 

 

 

XXh

 

 

00B8h

 

 

 

XXh

 

 

00B9h

CAN0 Message Box 5: Data Field

 

XXh

 

 

00BAh

 

XXh

 

 

 

 

 

 

 

00BBh

 

 

 

XXh

 

 

00BCh

 

 

 

XXh

 

 

00BDh

 

 

 

XXh

 

 

00BEh

CAN0 Message Box 5: Time Stamp

 

XXh

 

 

00BFh

 

XXh

 

 

 

 

 

 

X: Undefined

Rev.1.02 Jul 01, 2005 page 15 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.4

SFR Information (4)

 

 

 

 

 

 

 

 

 

 

 

Address

 

Register

Symbol

After Reset

 

 

00C0h

 

 

 

XXh

 

 

00C1h

 

 

 

XXh

 

 

00C2h

CAN0 Message Box 6: Identifier / DLC

 

XXh

 

 

00C3h

 

XXh

 

 

 

 

 

 

 

00C4h

 

 

 

XXh

 

 

00C5h

 

 

 

XXh

 

 

00C6h

 

 

 

XXh

 

 

00C7h

 

 

 

XXh

 

 

00C8h

 

 

 

XXh

 

 

00C9h

CAN0 Message Box 6: Data Field

 

XXh

 

 

00CAh

 

XXh

 

 

 

 

 

 

 

00CBh

 

 

 

XXh

 

 

00CCh

 

 

 

XXh

 

 

00CDh

 

 

 

XXh

 

 

00CEh

CAN0 Message Box 6: Time Stamp

 

XXh

 

 

00CFh

 

XXh

 

 

 

 

 

 

 

00D0h

 

 

 

XXh

 

 

00D1h

 

 

 

XXh

 

 

00D2h

CAN0 Message Box 7: Identifier / DLC

 

XXh

 

 

00D3h

 

XXh

 

 

 

 

 

 

 

00D4h

 

 

 

XXh

 

 

00D5h

 

 

 

XXh

 

 

00D6h

 

 

 

XXh

 

 

00D7h

 

 

 

XXh

 

 

00D8h

 

 

 

XXh

 

 

00D9h

CAN0 Message Box 7: Data Field

 

XXh

 

 

00DAh

 

XXh

 

 

 

 

 

 

 

00DBh

 

 

 

XXh

 

 

00DCh

 

 

 

XXh

 

 

00DDh

 

 

 

XXh

 

 

00DEh

CAN0 Message Box 7: Time Stamp

 

XXh

 

 

00DFh

 

XXh

 

 

 

 

 

 

 

00E0h

 

 

 

XXh

 

 

00E1h

 

 

 

XXh

 

 

00E2h

CAN0 Message Box 8: Identifier / DLC

 

XXh

 

 

00E3h

 

XXh

 

 

 

 

 

 

 

00E4h

 

 

 

XXh

 

 

00E5h

 

 

 

XXh

 

 

00E6h

 

 

 

XXh

 

 

00E7h

 

 

 

XXh

 

 

00E8h

 

 

 

XXh

 

 

00E9h

CAN0 Message Box 8: Data Field

 

XXh

 

 

00EAh

 

XXh

 

 

 

 

 

 

 

00EBh

 

 

 

XXh

 

 

00ECh

 

 

 

XXh

 

 

00EDh

 

 

 

XXh

 

 

00EEh

CAN0 Message Box 8: Time Stamp

 

XXh

 

 

00EFh

 

XXh

 

 

 

 

 

 

 

00F0h

 

 

 

XXh

 

 

00F1h

 

 

 

XXh

 

 

00F2h

CAN0 Message Box 9: Identifier / DLC

 

XXh

 

 

00F3h

 

XXh

 

 

 

 

 

 

 

00F4h

 

 

 

XXh

 

 

00F5h

 

 

 

XXh

 

 

00F6h

 

 

 

XXh

 

 

00F7h

 

 

 

XXh

 

 

00F8h

 

 

 

XXh

 

 

00F9h

CAN0 Message Box 9: Data Field

 

XXh

 

 

00FAh

 

XXh

 

 

 

 

 

 

 

00FBh

 

 

 

XXh

 

 

00FCh

 

 

 

XXh

 

 

00FDh

 

 

 

XXh

 

 

00FEh

CAN0 Message Box 9: Time Stamp

 

XXh

 

 

00FFh

 

XXh

 

 

 

 

 

 

X: Undefined

Rev.1.02 Jul 01, 2005 page 16 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.5

SFR Information (5)

 

 

 

 

 

 

 

 

 

 

 

Address

 

Register

Symbol

After Reset

 

 

0100h

 

 

 

XXh

 

 

0101h

 

 

 

XXh

 

 

0102h

CAN0 Message Box 10: Identifier / DLC

 

XXh

 

 

0103h

 

XXh

 

 

 

 

 

 

 

0104h

 

 

 

XXh

 

 

0105h

 

 

 

XXh

 

 

0106h

 

 

 

XXh

 

 

0107h

 

 

 

XXh

 

 

0108h

 

 

 

XXh

 

 

0109h

CAN0 Message Box 10: Data Field

 

XXh

 

 

010Ah

 

XXh

 

 

 

 

 

 

 

010Bh

 

 

 

XXh

 

 

010Ch

 

 

 

XXh

 

 

010Dh

 

 

 

XXh

 

 

010Eh

CAN0 Message Box 10: Time Stamp

 

XXh

 

 

010Fh

 

XXh

 

 

 

 

 

 

 

0110h

 

 

 

XXh

 

 

0111h

 

 

 

XXh

 

 

0112h

CAN0 Message Box 11: Identifier / DLC

 

XXh

 

 

0113h

 

XXh

 

 

 

 

 

 

 

0114h

 

 

 

XXh

 

 

0115h

 

 

 

XXh

 

 

0116h

 

 

 

XXh

 

 

0117h

 

 

 

XXh

 

 

0118h

 

 

 

XXh

 

 

0119h

CAN0 Message Box 11: Data Field

 

XXh

 

 

011Ah

 

XXh

 

 

 

 

 

 

 

011Bh

 

 

 

XXh

 

 

011Ch

 

 

 

XXh

 

 

011Dh

 

 

 

XXh

 

 

011Eh

CAN0 Message Box 11: Time Stamp

 

XXh

 

 

011Fh

 

XXh

 

 

 

 

 

 

 

0120h

 

 

 

XXh

 

 

0121h

 

 

 

XXh

 

 

0122h

CAN0 Message Box 12: Identifier / DLC

 

XXh

 

 

0123h

 

XXh

 

 

 

 

 

 

 

0124h

 

 

 

XXh

 

 

0125h

 

 

 

XXh

 

 

0126h

 

 

 

XXh

 

 

0127h

 

 

 

XXh

 

 

0128h

 

 

 

XXh

 

 

0129h

CAN0 Message Box 12: Data Field

 

XXh

 

 

012Ah

 

XXh

 

 

 

 

 

 

 

012Bh

 

 

 

XXh

 

 

012Ch

 

 

 

XXh

 

 

012Dh

 

 

 

XXh

 

 

012Eh

CAN0 Message Box 12: Time Stamp

 

XXh

 

 

012Fh

 

XXh

 

 

 

 

 

 

 

0130h

 

 

 

XXh

 

 

0131h

 

 

 

XXh

 

 

0132h

CAN0 Message Box 13: Identifier / DLC

 

XXh

 

 

0133h

 

XXh

 

 

 

 

 

 

 

0134h

 

 

 

XXh

 

 

0135h

 

 

 

XXh

 

 

0136h

 

 

 

XXh

 

 

0137h

 

 

 

XXh

 

 

0138h

 

 

 

XXh

 

 

0139h

CAN0 Message Box 13: Data Field

 

XXh

 

 

013Ah

 

XXh

 

 

 

 

 

 

 

013Bh

 

 

 

XXh

 

 

013Ch

 

 

 

XXh

 

 

013Dh

 

 

 

XXh

 

 

013Eh

CAN0 Message Box 13: Time Stamp

 

XXh

 

 

013Fh

 

XXh

 

 

 

 

 

 

X: Undefined

Rev.1.02 Jul 01, 2005 page 17 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.6

SFR Information (6)

 

 

 

 

 

 

 

 

 

 

 

Address

 

Register

Symbol

After Reset

 

 

0140h

 

 

 

XXh

 

 

0141h

 

 

 

XXh

 

 

0142h

CAN0 Message Box 14: Identifier /DLC

 

XXh

 

 

0143h

 

XXh

 

 

 

 

 

 

 

0144h

 

 

 

XXh

 

 

0145h

 

 

 

XXh

 

 

0146h

 

 

 

XXh

 

 

0147h

 

 

 

XXh

 

 

0148h

 

 

 

XXh

 

 

0149h

CAN0 Message Box 14: Data Field

 

XXh

 

 

014Ah

 

XXh

 

 

 

 

 

 

 

014Bh

 

 

 

XXh

 

 

014Ch

 

 

 

XXh

 

 

014Dh

 

 

 

XXh

 

 

014Eh

CAN0 Message Box 14: Time Stamp

 

XXh

 

 

014Fh

 

XXh

 

 

 

 

 

 

 

0150h

 

 

 

XXh

 

 

0151h

 

 

 

XXh

 

 

0152h

CAN0 Message Box 15: Identifier /DLC

 

XXh

 

 

0153h

 

XXh

 

 

 

 

 

 

 

0154h

 

 

 

XXh

 

 

0155h

 

 

 

XXh

 

 

0156h

 

 

 

XXh

 

 

0157h

 

 

 

XXh

 

 

0158h

 

 

 

XXh

 

 

0159h

CAN0 Message Box 15: Data Field

 

XXh

 

 

015Ah

 

XXh

 

 

 

 

 

 

 

015Bh

 

 

 

XXh

 

 

015Ch

 

 

 

XXh

 

 

015Dh

 

 

 

XXh

 

 

015Eh

CAN0 Message Box 15: Time Stamp

 

XXh

 

 

015Fh

 

XXh

 

 

 

 

 

 

 

0160h

 

 

 

XXh

 

 

0161h

 

 

 

XXh

 

 

0162h

CAN0 Global Mask Register

C0GMR

XXh

 

 

0163h

XXh

 

 

 

 

 

 

 

0164h

 

 

 

XXh

 

 

0165h

 

 

 

XXh

 

 

0166h

 

 

 

XXh

 

 

0167h

 

 

 

XXh

 

 

0168h

CAN0 Local Mask A Register

C0LMAR

XXh

 

 

0169h

XXh

 

 

 

 

 

 

 

016Ah

 

 

 

XXh

 

 

016Bh

 

 

 

XXh

 

 

016Ch

 

 

 

XXh

 

 

016Dh

 

 

 

XXh

 

 

016Eh

CAN0 Local Mask B Register

C0LMBR

XXh

 

 

016Fh

XXh

 

 

 

 

 

 

 

0170h

 

 

 

XXh

 

 

0171h

 

 

 

XXh

 

 

0172h

 

 

 

 

 

 

0173h

 

 

 

 

 

 

0174h

 

 

 

 

 

 

0175h

 

 

 

 

 

 

0176h

 

 

 

 

 

 

0177h

 

 

 

 

 

 

0178h

 

 

 

 

 

 

0179h

 

 

 

 

 

 

017Ah

 

 

 

 

 

 

017Bh

 

 

 

 

 

 

017Ch

 

 

 

 

 

 

017Dh

 

 

 

 

 

 

017Eh

 

 

 

 

 

 

017Fh

 

 

 

 

 

 

X: Undefined

 

 

 

 

 

NOTE:

 

 

 

 

 

 

1. The blank areas are reserved and cannot be accessed by users.

 

 

 

Rev.1.02 Jul 01, 2005 page 18 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.7 SFR Information (7)

 

 

 

 

 

 

 

 

 

 

Address

Register

Symbol

After Reset

 

 

0180h

 

 

 

 

 

0181h

 

 

 

 

 

0182h

 

 

 

 

 

0183h

 

 

 

 

 

0184h

 

 

 

 

 

0185h

 

 

 

 

 

0186h

 

 

 

 

 

0187h

 

 

 

 

 

0188h

 

 

 

 

 

0189h

 

 

 

 

 

018Ah

 

 

 

 

 

018Bh

 

 

 

 

 

018Ch

 

 

 

 

 

018Dh

 

 

 

 

 

018Eh

 

 

 

 

 

018Fh

 

 

 

 

 

0190h

 

 

 

 

 

0191h

 

 

 

 

 

0192h

 

 

 

 

 

0193h

 

 

 

 

 

0194h

 

 

 

 

 

0195h

 

 

 

 

 

0196h

 

 

 

 

 

0197h

 

 

 

 

 

0198h

 

 

 

 

 

0199h

 

 

 

 

 

019Ah

 

 

 

 

 

019Bh

 

 

 

 

 

019Ch

 

 

 

 

 

019Dh

 

 

 

 

 

019Eh

 

 

 

 

 

019Fh

 

 

 

 

 

01A0h

 

 

 

 

 

01A1h

 

 

 

 

 

01A2h

 

 

 

 

 

01A3h

 

 

 

 

 

01A4h

 

 

 

 

 

01A5h

 

 

 

 

 

01A6h

 

 

 

 

 

01A7h

 

 

 

 

 

01A8h

 

 

 

 

 

01A9h

 

 

 

 

 

01AAh

 

 

 

 

 

01ABh

 

 

 

 

 

01ACh

 

 

 

 

 

01ADh

 

 

 

 

 

01AEh

 

 

 

 

 

01AFh

 

 

 

 

 

01B0h

 

 

 

 

 

01B1h

 

 

 

 

 

01B2h

 

 

 

 

 

01B3h

 

 

 

 

 

01B4h

 

 

 

 

 

01B5h

Flash Memory Control Register 1 (1)

FMR1

0X00XX0Xb

 

 

01B6h

 

 

 

 

 

01B7h

Flash Memory Control Register 0 (1)

FMR0

00000001b

 

 

01B8h

 

 

00h

 

 

01B9h

Address Match Interrupt Register 2

RMAD2

00h

 

 

01BAh

 

 

X0h

 

 

01BBh

Address Match Interrupt Enable Register 2

AIER2

XXXXXX00b

 

 

01BCh

 

 

00h

 

 

01BDh

Address Match Interrupt Register 3

RMAD3

00h

 

 

01BEh

 

 

X0h

 

 

01BFh

 

 

 

 

X: Undefined

NOTES:

1.These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.

2.The blank areas are reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 19 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.8 SFR Information (8)

 

 

 

 

 

 

 

 

 

 

Address

Register

Symbol

After Reset

 

 

01C0h

Timer B3, B4, B5 Count Start Flag

TBSR

000XXXXXb

 

 

01C1h

 

 

 

 

 

01C2h

Timer A1-1 Register

TA11

XXh

 

 

01C3h

XXh

 

 

 

 

 

 

01C4h

Timer A2-1 Register

TA21

XXh

 

 

01C5h

XXh

 

 

 

 

 

 

01C6h

Timer A4-1 Register

TA41

XXh

 

 

01C7h

XXh

 

 

 

 

 

 

01C8h

Three-Phase PWM Control Register 0

INVC0

00h

 

 

01C9h

Three-Phase PWM Control Register 1

INVC1

00h

 

 

01CAh

Three-Phase Output Buffer Register 0

IDB0

00h

 

 

01CBh

Three-Phase Output Buffer Register 1

IDB1

00h

 

 

01CCh

Dead Time Timer

DTT

XXh

 

 

01CDh

Timer B2 Interrupt Occurrence Frequency Set Counter

ICTB2

XXh

 

 

01CEh

 

 

 

 

 

01CFh

Interrupt Cause Select Register 2

IFSR2

X0000000b

 

 

01D0h

Timer B3 Register

TB3

XXh

 

 

01D1h

XXh

 

 

 

 

 

 

01D2h

Timer B4 Register

TB4

XXh

 

 

01D3h

XXh

 

 

 

 

 

 

01D4h

Timer B5 Register

TB5

XXh

 

 

01D5h

XXh

 

 

 

 

 

 

01D6h

SI/O6 Transmit/Receive Register (1)

S6TRR

XXh

 

 

01D7h

 

 

 

 

 

01D8h

SI/O6 Control Register (1)

S6C

01000000b

 

 

01D9h

SI/O6 Bit Rate Generator (1)

S6BRG

XXh

 

 

01DAh

SI/O3, 4, 5, 6 Transmit/Receive Register (2)

S3456TRR

XXXX0000b

 

 

01DBh

Timer B3 Mode Register

TB3MR

00XX0000b

 

 

01DCh

Timer B4 Mode Register

TB4MR

00XX0000b

 

 

01DDh

Timer B5 Mode Register

TB5MR

00XX0000b

 

 

01DEh

Interrupt Cause Select Register 0

IFSR0

00h

 

 

01DFh

Interrupt Cause Select Register 1

IFSR1

00h

 

 

01E0h

SI/O3 Transmit/Receive Register

S3TRR

XXh

 

 

01E1h

 

 

 

 

 

01E2h

SI/O3 Control Register

S3C

01000000b

 

 

01E3h

SI/O3 Bit Rate Generator

S3BRG

XXh

 

 

01E4h

SI/O4 Transmit/Receive Register

S4TRR

XXh

 

 

01E5h

 

 

 

 

 

01E6h

SI/O4 Control Register

S4C

01000000b

 

 

01E7h

SI/O4 Bit Rate Generator

S4BRG

XXh

 

 

01E8h

SI/O5 Transmit/Receive Register (1)

S5TRR

XXh

 

 

01E9h

 

 

 

 

 

01EAh

SI/O5 Control Register (1)

S5C

01000000b

 

 

01EBh

SI/O5 Bit Rate Generator (1)

S5BRG

XXh

 

 

01ECh

UART0 Special Mode Register 4

U0SMR4

00h

 

 

01EDh

UART0 Special Mode Register 3

U0SMR3

000X0X0Xb

 

 

01EEh

UART0 Special Mode Register 2

U0SMR2

X0000000b

 

 

01EFh

UART0 Special Mode Register

U0SMR

X0000000b

 

 

01F0h

UART1 Special Mode Register 4

U1SMR4

00h

 

 

01F1h

UART1 Special Mode Register 3

U1SMR3

000X0X0Xb

 

 

01F2h

UART1 Special Mode Register 2

U1SMR2

X0000000b

 

 

01F3h

UART1 Special Mode Register

U1SMR

X0000000b

 

 

01F4h

UART2 Special Mode Register 4

U2SMR4

00h

 

 

01F5h

UART2 Special Mode Register 3

U2SMR3

000X0X0Xb

 

 

01F6h

UART2 Special Mode Register 2

U2SMR2

X0000000b

 

 

01F7h

UART2 Special Mode Register

U2SMR

X0000000b

 

 

01F8h

UART2 Transmit/Receive Mode Register

U2MR

00h

 

 

01F9h

UART2 Bit Rate Generator

U2BRG

XXh

 

 

01FAh

UART2 Transmit Buffer Register

U2TB

XXh

 

 

01FBh

XXh

 

 

 

 

 

 

01FCh

UART2 Transmit/Receive Control Register 0

U2C0

00001000b

 

 

01FDh

UART2 Transmit/Receive Control Register 1

U2C1

00000010b

 

 

01FEh

UART2 Receive Buffer Register

U2RB

XXh

 

 

01FFh

XXh

 

 

 

 

 

X: Undefined

NOTES:

1.These registers exist only in the 128-pin version.

2.The S5TRF and S6TRF bits in the S3456TRR register are used in the 128-pin version.

3.The blank areas are reserved and cannot be accessed by users.

Rev.1.02 Jul 01, 2005 page 20 of 314

REJ09B0126-0102

Under development

This document is under development and its contents are subject to change.

M16C/6N Group (M16C/6NL, M16C/6NN)

4. Special Function Register (SFR)

Table 4.9 SFR Information (9)

 

 

 

 

 

 

 

 

 

 

Address

Register

Symbol

After Reset

 

 

0200h

CAN0 Message Control Register 0

C0MCTL0

00h

 

 

0201h

CAN0 Message Control Register 1

C0MCTL1

00h

 

 

0202h

CAN0 Message Control Register 2

C0MCTL2

00h

 

 

0203h

CAN0 Message Control Register 3

C0MCTL3

00h

 

 

0204h

CAN0 Message Control Register 4

C0MCTL4

00h

 

 

0205h

CAN0 Message Control Register 5

C0MCTL5

00h

 

 

0206h

CAN0 Message Control Register 6

C0MCTL6

00h

 

 

0207h

CAN0 Message Control Register 7

C0MCTL7

00h

 

 

0208h

CAN0 Message Control Register 8

C0MCTL8

00h

 

 

0209h

CAN0 Message Control Register 9

C0MCTL9

00h

 

 

020Ah

CAN0 Message Control Register 10

C0MCTL10

00h

 

 

020Bh

CAN0 Message Control Register 11

C0MCTL11

00h

 

 

020Ch

CAN0 Message Control Register 12

C0MCTL12

00h

 

 

020Dh

CAN0 Message Control Register 13

C0MCTL13

00h

 

 

020Eh

CAN0 Message Control Register 14

C0MCTL14

00h

 

 

020Fh

CAN0 Message Control Register 15

C0MCTL15

00h

 

 

0210h

CAN0 Control Register

C0CTLR

X0000001b

 

 

0211h

XX0X0000b

 

 

 

 

 

 

0212h

CAN0 Status Register

C0STR

00h

 

 

0213h

X0000001b

 

 

 

 

 

 

0214h

CAN0 Slot Status Register

C0SSTR

00h

 

 

0215h

00h

 

 

 

 

 

 

0216h

CAN0 Interrupt Control Register

C0ICR

00h

 

 

0217h

00h

 

 

 

 

 

 

0218h

CAN0 Extended ID Register

C0IDR

00h

 

 

0219h

00h

 

 

 

 

 

 

021Ah

CAN0 Configuration Register

C0CONR

XXh

 

 

021Bh

XXh

 

 

 

 

 

 

021Ch

CAN0 Receive Error Count Register

C0RECR

00h

 

 

021Dh

CAN0 Transmit Error Count Register

C0TECR

00h

 

 

021Eh

CAN0 Time Stamp Register

C0TSR

00h

 

 

021Fh

00h

 

 

 

 

 

 

0220h

 

 

 

 

 

0221h

 

 

 

 

 

0222h

 

 

 

 

 

0223h

 

 

 

 

 

0224h

 

 

 

 

 

0225h

 

 

 

 

 

0226h

 

 

 

 

 

0227h

 

 

 

 

 

0228h

 

 

 

 

 

0229h

 

 

 

 

 

022Ah