Renesas 8T49N285 Datasheet

FemtoClock® NG Octal Universal Frequency Translator

8T49N285

Datasheet

Description

The 8T49N285 has a fractional-feedback PLL that can be used as a jitter attenuator or frequency translator. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 different output frequencies, ranging from 8kHz to 1GHz. Three of these frequencies are completely independent of each other and the inputs. The other five are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.

This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G, and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device may also behave as a frequency synthesizer.

The 8T49N285 accepts up to two differential or single-ended input clocks and a crystal input. The PLL can lock to either input clock, but both input clocks must be related in frequency.

The device supports hitless reference switching between input clocks. The device monitors both input clocks for Loss of Signal (LOS). It generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks.

The 8T49N285 supports holdover with an initial accuracy of ±50ppB from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point that may be returned to in holdover at a limited phase slope.

The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.709 (2009), most with 0ppm conversion error.

The PLL has a register-selectable loop bandwidth from 1.4Hz to 360Hz.

Each output supports individual phase delay settings to allow output-output alignment.

The device supports Output Enable inputs and Lock, Holdover and LOS status outputs.

The device is programmable through an I

C master capability to allow the register configuration to be read

I from an external EEPROM.

C interface. It also supports

Typical Applications

• OTN or SONET / SDH equipment Line cards (up to OC-192, and

supporting FEC ratios)

• OTN de-mapping (Gapped Clock and DCO mode)

• Gigabit and Terabit IP switches / routers including support of

Synchronous Ethernet

• SyncE (G.8262) applications

• Wireless base station baseband

• Data communications

• 100G Ethernet

Features

• Supports SDH/SONET and Synchronous Ethernet clocks

including all FEC rate conversions

• <0.3ps RMS typical jitter (including spurs),12kHz to 20MHz

• Operating modes: locked to input signal, holdover and free-run

• Initial holdover accuracy of ±50ppb

• Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS

input clocks

• Accepts frequencies ranging from 8kHz up to 875MHz

• Auto and manual input clock selection with hitless switching

• Clock input monitoring, including support for gapped clocks

• Phase-Slope Limiting and Fully Hitless Switching options to

control output phase transients

• Operates from a 10MHz to 40MHz fundamental-mode crystal

• Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks

• Output frequencies ranging from 8kHz up to 1.0GHz (diff)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

• Four General Purpose I/O pins with optional support for status &

control:

• Four Output Enable control inputs may be mapped to any of the

eight outputs

• Lock, Holdover & Loss-of-Signal status outputs

• Open-drain Interrupt pin

• Nine programmable PLL loop bandwidth settings from 1.4Hz to

360Hz.

• Optional Fast Lock function

• Programmable output phase delays in steps as small as 16ps

• Register programmable through I

• Bypass clock paths for system tests

• Power supply modes

/ V

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

CCA

/ V

CCO

• -40°C to 85°C ambient operating temperature

• Package: 56QFN, lead-free RoHs (6)

C or via external I2C EEPROM

8T49N285 Block Diagram

IntN Output

Divider

IntN Output

Divider

FracN Output

Divider

FracN Output

Divider

Fractional Feedback

APLL

Input Clock Monitoring,

Priority,

Selection

Status Registers

Control Registers

GPIO Logic

Lock

Holdover

OSC

XTAL

CLK0

OTP

I2C Master

I2C Slave

Reset

Logic

SCLK SDATA

Serial EEPROM

LOS

CLK1

nINT

IntN

SA0

PLL_BYP

GPIO

nRST

8T49N285 Datasheet

Figure 1. 8T49N285 Functional Block Diagram

Pin Assignment

56-pin, 8mm x 8mm VFQFN Package

nQ1

CCO1

nRST

nQ0

CCO0

nINT

CCA

CAP_REF

CAP

PLL_BYP

CCA

nQ2

CCO2

GPIO[0]

CCO3

GPIO[1]

CCA

RESERVED

CCA

CCAVCCA

OSCI

OSCO

S_A0

CLK0

nCLK0

CLK1

nCLK1

SDATA

SCLK

CCA

nQ3

GPIO[2]

CCO4

nQ4

CCO5

nQ5

CCO6

nQ6

CCO7

nQ7

GPIO[3]

8T49N285

13 14

37 36

35 34

30 29

8T49N285 Datasheet

Figure 2. Pin-out Drawing

8T49N285 Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number Name Type Description

4OSCOO

5 S_A0 I Pulldown I

12 SDATA I/O Pullup I

13 SCLK I/O Pullup I

7 CLK0 I Pulldown Non-inverting differential clock input.

8nCLK0 I

9 CLK1 I Pulldown Non-inverting differential clock input.

10 nCLK1 I

48, 47 Q0, nQ0 O Universal Output Clock 0. Please refer to the Output Drivers section for more details.

44, 43 Q1, nQ1 O Universal Output Clock 1. Please refer to the Output Drivers section for more details.

27, 28 Q2, nQ2 O Universal Output Clock 2. Please refer to the Output Drivers section for more details.

23, 24 Q3, nQ3 O Universal Output Clock 3. Please refer to the Output Drivers section for more details.

40, 39 Q4, nQ4 O Universal Output Clock 4. Please refer to the Output Drivers section for more details.

37, 36 Q5, nQ5 O Universal Output Clock 5. Please refer to the Output Drivers section for more details.

34, 33 Q6, nQ6 O Universal Output Clock 6. Please refer to the Output Drivers section for more details.

31, 30 Q7, nQ7 O Universal Output Clock 7. Please refer to the Output Drivers section for more details.

OSCI

nRST

Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a 12pF fundamental mode, parallel-resonant crystal.

Crystal Output. This pin should be connected to a crystal. If an oscillator is connected to OSCI, then this pin must be left unconnected.

C lower address bit A0.

C interface bi-directional Data.

C interface bi-directional Clock.

Pullup /

Pulldown

Pullup /

Pulldown

Inverting differential clock input. V pullup and pulldown resistors.)

Inverting differential clock input. VCC/2 when left floating (set by the internal pullup and pulldown resistors.)

/2 when left floating (set by the internal

Master Reset input. LVTTL / LVCMOS interface levels.

I Pullup

0 = All registers and state machines are reset to their default values 1 = Device runs normally

29, 42, 21, 25

6, ePad V

2, 14, 15, 16,

1, 51, 55, 56

nINT

GPIO[3:0]

PLL_BYP

CCA

CCO0

CCO1

CCO2

CCO3

CCO4

I/O Pullup

I Pulldown

Power

Open-drain

with pullup

Interrupt output.

General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain output. Pulled-up with 5.1k resistor to V

CC.

Bypass Selection. Allow input references to bypass the PLL. LVTTL / LVCMOS interface levels

Negative supply voltage. All V

pins and ePad must be connected before

any positive supply voltage is applied.

Power Core and digital functions supply voltage.

Power Analog functions supply voltage for core analog functions.

Power Analog functions supply voltage for analog functions associated with PLL.

Power High-speed output supply voltage for output pair Q0, nQ0.

Power High-speed output supply voltage for output pair Q1, nQ1.

Power High-speed output supply voltage for output pair Q2, nQ2.

Power High-speed output supply voltage for output pair Q3, nQ3.

Power High-speed output supply voltage for output pair Q4, nQ4.

Table 1. Pin Descriptions1 (Continued)

Number Name Type Description

53 52

18,

CCO5

CCO6

CCO7

CAP,

CAP_REF

RESERVED

NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Power High-speed output supply voltage for output pair Q5, nQ5.

Power High-speed output supply voltage for output pair Q6, nQ6.

Power High-speed output supply voltage for output pair Q7, nQ7.

Analog PLL External Capacitance.

Reserved Reserved pins.

8T49N285 Datasheet

Table 2. Pin Characteristics, VCC = V

= 3.3V±5% or 2.5V±5%

CCOX

Symbol Parameter Test Conditions Minimum Typical Maximum Units

PULLUP

Input Capacitance

Internal Pullup Resistor

nRST, SDATA, SCLK

3.5 pF

51 k

nINT 50 k

GPIO[3:0] 5.1 k

PULLDOWN

Internal Pulldown Resistor 51 k

Power Dissipation Capacitance (per output pair)

LVCMOS Q[0:1], Q[4:7]

LVCMOS Q[2:3] V

LVCMOS Q[0:1], Q[4:7]

LVCMOS Q[2:3] V

LVCMOS Q[0:1], Q[4:7]

LVCMOS Q[2:3] V

= 3.465V 14.5 pF

CCOX

= 3.465V 18.5 pF

CCOX

= 2.625V 13 pF

CCOX

= 2.625V 17.5 pF

CCOX

= 1.89V 12.5 pF

CCOX

= 1.89V 17 pF

CCOX

LVDS, HCSL or LVPECL Q[0:1],

= 3.465V or 2.625V 2 pF

CCOx

Q[4:7]

OUT

NOTE 1: V

CCOX

Output Impedance

denotes: V

LVDS, HCSL or LVPECL Q[2:3]

GPIO [3:0]

LVCMOS Q[0:7], nQ[0:7]

CCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.

= 3.465V or 2.625V 4.5 pF

CCOx

Output HIGH 5.1 k

Output LOW 25 

20 

NOTE 2: This specification does not apply to OSCI and OSCO pins.

Principles of Operation

The 8T49N285 can be locked to either of the input clocks and generate a wide range of synchronized output clocks.

It could be used for example in either the transmit or receive path of Synchronous Ethernet equipment.

The 8T49N285 accepts up to two differential input clocks ranging from 8kHz up to 875MHz. It generates up to 8 output clocks ranging from 8kHz up to 1.0GHz.

The PLL path within the 8T49N285 supports three states: Lock, Holdover and Free-run. Lock & holdover status may be monitored on register bits and pins. The PLL also supports automatic and manual hitless reference switching. In the locked state, the PLL locks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accuracy of the input clock. In the Holdover state, the PLL will output a clock which is based on the selected holdover behavior. The PLL within the 8T49N285 has an initial holdover frequency offset of ±50ppb. In the Free-run state, the PLL outputs a clock with the same frequency accuracy as the external crystal.

Upon power up, the PLL will enter Free-run state, in this state it generates output clocks with the same frequency accuracy as the external crystal. The 8T49N285 continuously monitors each input for activity (signal transitions).

In automatic reference switching, when an input clock has been validated the PLL will transition to the locked state. If the selected input clock fails and there are no other valid input clocks, the PLL will quickly detect that and go into holdover. In the Holdover state, the PLL will output a clock which is based on the selected holdover behavior. If the selected input clock fails and another input clock is available then the 8T49N285 will hitlessly switch to that input clock. The reference switch can be either revertive or non-revertive.

The device supports conversion of any input frequencies to three different, independent output frequencies on the Q0 and Q[2:3] outputs. Additionally, a further five output frequencies may be generated that are integer-related to the three independent frequencies. These additional five frequencies are on the Q1 and Q[4:7] outputs.

The 8T49N285 has a programmable loop bandwidth from 1.4Hz to 360Hz.

The device monitors all input clocks and generates an alarm when an input clock failure is detected.

The device supports programmable individual output phase adjustments in order to allow control of input to output phase adjustments and output to output phase alignment.

The device is programmable through an I autonomously read its register settings from an internal One-Time Programmable (OTP) memory or an external serial I

Crystal Input

The crystal input on the 8T49N285 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of 10MHz - 40MHz.

C and may also

C EEPROM.

8T49N285 Datasheet

The oscillator input also supports being driven by a single-ended crystal oscillator or reference clock.

The initial holdover frequency offset is set by the device, but the long term drift depends on the quality of the crystal or oscillator attached to this port.

Bypass Path

For system test purposes, the PLL may be bypassed. When PLL_BYP is asserted the CLK0 input reference will be presented to the Q4 output dividers and the CLK1 Input reference will be presented to the Q5 output dividers.

Additionally, CLK0 or CLK1 may be used as a clock source for the output dividers of Q[4:7]. This may only be done for input frequencies of 250MHz or less.

Input Clock Selection

The 8T49N285 accepts up to two input clocks with frequencies ranging from 8kHz up to 875MHz. Each input can accept LVPECL, LVDS, LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V logic levels. To use LVCMOS inputs, refer to the Application Note,

Wiring the Differential Input to Accept Single-Ended Levels for

biasing instructions.

In Manual mode, only one of the inputs may be chosen and if that input fails the PLL will enter holdover.

Manual mode may be operated by directly selecting the desired input reference in the REFSEL register field. It may also operate via pin-selection of the desired input clock by selecting that mode in the RE FSE L register fie ld. In tha t cas e, GP IO[2 ] mus t be u sed as a Clock Select input (CSEL). CSEL = 0 will select the CLK0 input and CSEL = 1 will select the CLK1 input.

In addition, the crystal frequency may be passed directly to the output dividers for Q[4:7] to use as a reference.

Inputs do not support transmission of spread-spectrum clocking sources. Since this family is intended for high-performance applications, it will assume input reference sources to have stabilities

100ppm or better, except where gapped clock inputs are used.

of +

If the PLL is working in automatic mode, then each of the input reference sources is assigned a priority of 1-2. At power-up or if the currently selected input reference fails, the PLL will switch to the highest priority input reference that is valid at that time (seeInput

Clock Monitor for details).

Automatic mode has two sub-options: revertive or non-revertive. In revertive mode, the PLL will switch to a reference with a higher priority setting whenever one becomes valid. In non-revertive mode the PLL remains with the currently selected source as long as it remains valid.

The clock input selection is based on the input clock priority set by the Clock Input Priority control registers. It is recommended that all input references be given different priority settings in the Clock Input Priority control register.

8T49N285 Datasheet

Input Clock Monitor

Each clock input is monitored for Loss of Signal (LOS). If no activity has been detected on the clock input within a user-selectable time period then the clock input is considered to be failed and an internal Loss-of-Signal status flag is set, which may cause an input switchover depending on other settings. The user-selectable time period has sufficient range to allow a gapped clock missing many consecutive edges to be considered a valid input.

User-selection of the clock monitor time-period is based on a counter driven by a monitor clock. The monitor clock is fixed at the frequency of the PLL’s VCO divided by 8. With a VCO range of 3GHz - 4GHz, the monitor clock has a frequency range of 375MHz to 500MHz.

The monitor logic for each input reference will count the number of monitor clock edges indicated in the appropriate Monitor Control register. If an edge is received on the input reference being monitored, then the count resets and begins again. If the target edge count is reached before an input reference edge is received, then an internal soft alarm is raised and the count re-starts. During the soft alarm period, the PLL tracking will not be adjusted. If an input reference edge is received before the count expires for the second time, then the soft alarm status is cleared and the PLL will resume adjustments. If the count expires again without any input reference edge being received, then a Loss-of-Signal alarm is declared.

It is expected that for normal (non-gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer than the nominal period of that input reference. A margin of 2-3 monitor clock periods should give a reasonably quick reaction time and yet prevent false alarms.

For gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest expected clock gap period. The monitor count registers support 17-bit count values, which will support at least a gap length of two clock periods for any supported input reference frequency, with longer gaps being supported for faster input reference frequencies. Since gapped clocks usually occur on input reference frequencies above 100MHz, gap lengths of thousands of periods can be supported.

Using this configuration for a gapped clock, the PLL will continue to adjust while the normally expected gap is present, but will freeze once the expected gap length has been exceeded and alarm after twice the normal gap length has passed.

Once a LOS on any of the input clocks is detected, the appropriate internal LOS alarm will be asserted and it will remain asserted until that input clock returns and is validated once 8 rising edges have been received on that input reference. If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over.

Each LOS flag may also be reflected on one of the GPIO[3:0] outputs. Changes in status of any reference can also generate an interrupt if not masked.

Holdover

8T49N285 supports a small initial holdover frequency offset in non-gapped clock mode. When the input clock monitor is set to support gapped clock operation, this initial holdover frequency offset is indeterminate since the desired behavior with gapped clocks is for the PLL to continue to adjust itself even if clock edges are missing. In

gapped clock mode, the PLL will not enter holdover until the input is missing for two LOS monitor periods.

The holdover performance characteristics of a clock are referred as its accuracy and stability, and are characterized in terms of the fractional frequency offset. The 8T49N285 can only control the initial frequency accuracy. Longer-term accuracy and stability are determined by the accuracy and stability of the external oscillator.

When the PLL loses all valid input references, it will enter the holdover state. In fast average mode, the PLL will initially maintain its most recent frequency offset setting and then transition at a rate dictated by its selected phase-slope limit setting to a frequency offset setting that is based on historical settings. This behavior is intended to compensate for any frequency drift that may have occurred on the input reference before it was detected to be lost.

The historical holdover value will have three options:

• Return to center of tuning range within the VCO band

• Instantaneous mode - the holdover frequency will use the DPLL current frequency 100msec before it entered holdover. The accuracy is shown in the AC Characteristics

Table, Table 11A.

• Fast average mode - an internal IIR (Infinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to nominal a period of 20 minutes. The accuracy is shown

in the AC Characteristics Table, Table 11A.

When entering holdover, the PLL will set a separate internal HOLD alarm internally. This alarm may be read from internal status register, appear on the appropriate GPIO pin and/or assert the nINT output.

While the PLL is in holdover, its frequency offset is now relative to the crystal input and so the output clocks will be tracing their accuracy to the local oscillator or crystal. At some point in time, depending on the stability & accuracy of that source, the clock(s) will have drifted outside of the limits of the holdover state and the system will be considered to be in a free-run state. Since this borderline is defined outside the PLL and dictated by the accuracy and stability of the external local crystal or oscillator, the 8T49N285 cannot know or influence when that transition occurs. remain in the Holdover state internally.

As a result, the 8T49N285 will

Input to Output Clock Frequency

The 8T49N285 is designed to accept any frequency within its input range and generate eight different output frequencies that are independent from the input frequencies. The internal architecture of the device ensures that most translations will result in the exact output frequency specified. Where exact frequency translation is not possible, the frequency translation error will be minimized. Please contact Renesas for configuration software or other assistance in determining if a desired configuration will be supported exactly.

Synthesizer Mode Operation

The device may also act as a frequency synthesizer with the PLL generating its operating frequency from just the crystal input. By setting the SYN_MODE register bit and setting the STATE[1:0] field to Freerun, no input clock references are required to generate the desired output frequencies.

8T49N285 Datasheet

Loop Filter and Bandwidth

When operating in Synthesizer Mode as described above, the 8T49N285 has a fixed loop bandwidth of approximately 200kHz. When Operating in all other modes, the following information applies:

The 8T49N285 uses no external components to support a range of loop bandwidths:1.40625Hz, 2.8125Hz, 5.625Hz, 11.25Hz, 22.5Hz, 45Hz, 90Hz, 180Hz or 360Hz.

The device supports two different loop bandwidth settings: acquisition and locked. These loop bandwidths are selected from the list of options described above. If enabled, the acquisition bandwidth is used while lock is being acquired to allow the PLL to “fast-lock”. Once locked the PLL will use the locked bandwidth setting. If the acquisition bandwidth setting is not used, the PLL will use the locked bandwidth setting at all times.

Output Dividers

The 8T49N285 supports eight output dividers. Six of the output

dividers will have IntN capability only (see Table 3) and the other two

will support FracN division.

Integer Output Divider Programming (Q0, Q1, Q[4:7] only)

Each integer output divider block consists of two divider stages in a series to achieve the desired total output divider ratio. The first stage divider may be set to divide by 4, 5 or 6. The second stage of the divider may be bypassed (i.e. ÷1) or programmed to any even divider ratio from 2 to 131,070. The total divide ratios, settings and possible

output frequencies are shown in Table 3.

In addition, the first divider stage for the Q[4:7] outputs support a bypass (i.e. ÷1) operation for some clock sources.

Fractional Output Divider Programming (Q2, Q3 only)

For the FracN output dividers Q2, Q3, the output divide ratio is given by:

Output Divide Ratio = (N.F)x2 N = Integer Part: 4, 5, ...(2

F = Fractional Part: [0, 1, 2, ...(2 For integer operation of these output dividers, N = 3 is also supported.

-1)

-1)]/(228)

Table 3. Q[0:1], Q[4:7] Output Divide Ratios

1st-Stage

Divide

4 1 4 750 1000

5 1 5 600 800

6 1 6 500 666.7

4 2 8 375 500

5 2 10 300 400

6 2 12 250 333.3

4 4 16 187.5 250

5 4 20 150 200

6 4 24 125 166.7

4 131,070 524,280 0.0057 0.0076

5 131,070 655,350 0.0046 0.0061

6 131,070 786,420 0.0038 0.0051

NOTE: Above frequency ranges for Q[4:7] apply when driven directly

2nd-Stage

Divide

from the PLL.

Total

Divide

...

Minimum

MHz

OUT

Maximum F

MHz

OUT

Output Divider Frequency Sources

Output dividers associated with the Q[0:3] outputs take their input frequency directly from the PLL.

Output dividers associated with the Q[4:7] outputs can take their input frequencies from the PLL, Q2 or Q3 output dividers, CLK0 or CLK1 input reference frequency or the crystal frequency.

Output Banks

Outputs of the 8T49N285 are divided into three banks for purposes of output skew measurement:

• Q0, nQ0, Q1, nQ1

• Q4, nQ4, Q5, nQ5

• Q6, nQ6, Q7, nQ7

8T49N285 Datasheet

Output Phase Control on Switchover

When the 8T49N285 switches between input references or enters or leaves the holdover state, there are two options on how the output phase can be controlled in these events: phase-slope limiting or fully hitless switching (sometimes called phase build-out) may be selected. The SWMODE bit selects which behavior is to be followed.

If fully hitless switching is selected, then the output phase will remain unchanged under any of these conditions. Note that fully hitless switching is not supported when external loopback is being used. Fully hitless switching should not be used unless all input references are in the same clock domain. Note that use of this mode may prevent an output frequency and phase from being able to trace its alignment back to a primary reference source.

If phase-slope limiting is selected, then the output phase will adjust from its previous value until it is tracking the new condition at a rate dictated by the SLEW[1:0] bits. Phase-slope limiting should be used if all input references are not in the same clock domain or users wish to retain traceability to a primary reference source.

Input-Output Delay Control

When using the 8T49N285 in external loopback or in a situation where input-output delay needs to be known and controlled, it is necessary to examine the exact signal path through the device. Due to the flexibility of the device, there are a large number of potential signal paths from input to output through it that depend on the desired configuration. Each of those potential paths may include or exclude logic blocks from the path and change the absolute value of the delay (Static Phase Offset or SPO) through the device. Considering the range of SPO values to cover all those potential paths would not be useful in achieving the target delays for any specific user configuration. Please contact Renesas for the specific SPO value associated with a desired input-output path. Note that events such as switchovers, entering or leaving holdover or re-configuring the signal path can result in one-time changes to the SPO due to that path

re-configuration. The AC Characteristics table (Table 11A) indicates

the maximum variation in SPO that could be expected for a particular path through the device.

Output Phase Alignment

The device has a programmable output to output phase alignment for each of the eight output dividers. After power-up and the PLL has achieved lock, the device will be in a state where the outputs are synchronized with a deterministic offset relative to each other. After synchronization, the output alignment will depend on the particular configuration of each output according to the following rules. The step size is defined as the period of the clock to that divider:

1) Only outputs derived from the same source will be aligned with each other. 'Source' means the reference selected to drive the output divider as controlled by the CLK_SELn bit for each output.

2) For integer dividers (Q[0:1], Q[4:7]) when both divider stages are active, edges are aligned. This case is used as a baseline to compare the other cases here.

3) For integer dividers where the 1st-stage divider is bypassed (only Q[4:7] support this), coarse delay adjustments can't be performed. The output phase will be one step earlier than in Case 2.

4) Fractional output dividers (Q2 or Q3) do not guarantee any specific phase on power-up or after a synchronization event.

5) Integer dividers using Q2 or Q3 as a source (Q[4:7] support this option) will be aligned to their source divider's output (Q2 or Q3). Note that the output skews described above are not included in any of the phase adjustments described here.

Once the device is in operation, the outputs may have their phase adjustments re-synced in one of two ways:

1) If the PLL becomes unlocked, the coarse phase adjustments will be reset and the fine phase adjustments will be re-loaded once it becomes locked again.

2) Toggling of PLL_SYN bit may also be used to force a re-sync / re-load for the outputs.

The user may apply adjustments that are proportional to the period of the clock source each output divider is operating from. For example, if the divider associated with Output Q3 is running off the PLL, which has a VCO frequency of 4GHz, then the appropriate period would be 250ps. The output phase may be adjusted in these steps across the full period of the output.

• Coarse Adjustment: all Output Dividers may have their phase

adjusted in steps of the source clock period. For example a 4GHz VCO gives a step size of 250ps. The user may request an adjustment of phase of up to 31 steps using a single register write. The phase will be adjusted by lengthening the period of the output by 250ps at a time. This process will be repeated every four output clock periods until the full requested adjustment has been achieved. A busy signal will remain asserted in the phase delay register until the requested adjustment is complete. Then a further adjustment may be setup and triggered by toggling the trigger bit.

• Fine Adjustment: For the Fractional Output Dividers associated

with the Q2 and Q3 outputs, the phase of those outputs may be further adjusted with a granularity of 1/16th of the VCO period. For example a 4GHz VCO frequency gives a granularity of 16ps. This is performed by directly writing the required offset (from the nominal rising edge position) in units of 1/16th of the output period into a register. Then the PLL_SYN bit must be toggled to load the new value. Note that toggling this bit will clear all Coarse Delays for all outputs associated with the PLL, so Fine Delays should be set first. The output will then jump directly to that new offset value. For this reason, this adjustment should be made as the input is initially programmed or in High-Impedance.

Each output has the capability of being inverted (180° phase shift).

Jitter and Wander Tolerance

The 8T49N285 can be used as a line card device and therefore is expected to tolerate the jitter and wander output of a timing card PLL (e.g. 82P33714).

8T49N285 Datasheet

Output Drivers

The Q[0:7] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register, any of these outputs can support LVCMOS, LVPECL, HCSL or LVDS logic levels.

The operating voltage ranges of each output is determined by its independent output power pin (V

) and thus each can have

CCO

different output voltage levels. Output voltage levels of 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, the LVCMOS output operation supports 1.8V (V

CCO

Each output may be enabled or disabled by register bits and/or GPIO pins configured as Output Enables. The outputs will be enabled if the register bit and the associated OE pin are both asserted (high). When disabled an output will be in a high impedance state.

LVCMOS O p eratio n

When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All the previously described configuration and control apply equally to both outputs. Frequency, phase alignment, voltage levels and enable / disable status apply to both the Q and nQ pins. When LVCMOS levels are selected, the Q and nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another. Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power consumption. It is recommended that use of this selection be kept to a minimum.

Power-Saving Modes

To allow the device to consume the least power possible for a given application, the following functions are included under register control:

• Any unused output, including all output divider and phase

adjustment logic, can be individually powered-off.

• Clock gating on logic that is not being used.

Status / Control Signals and Interrupts

General-Purpose I/Os & Interrupts

The 8T49N285 provides four General Purpose Input / Output (GPIO) pins for miscellaneous status & control functions. Each GPIO may be configured as an input or an output. Each GPIO may be directly controlled from register bits or be used as a predefined function as

shown in Table 4. Note that the default state prior to configuration

being loaded from internal OTP or external EEPROM will be to set each GPIO to function as an Output Enable.

If used in the Fixed Function mode of operation, the GPIO bits will reflect the real-time status of their respective status bits as shown in

Table 4. Note that the LOL signal represents the lock status of the

PLL. It does not account for the process of synchronization of the output dividers associated with that PLL. The output dividers programmed to operate from that PLL will automatically go through a re-synchronization process when the PLL locks or re-locks or if the user triggers a re-sync manually via register bit PLL_SYN. This synchronization process may result in a period of instability on the affected outputs for a duration of up to 350ns after the re-lock (LOL de-asserts) or the PLL_SYN bit is de-asserted.

Table 4. GPIO Configuration

Configured as Input

Fixed Function

Output

GPIO Pin

Enable

(default)

3 OE[3] OE[7] - GPI[3] LOS[1] GPO[3]

2 OE[2] OE[6] CSEL GPI[2] LOS[0] GPO[2]

1 OE[1] OE[5] - GPI[1] HOLD GPO[1]

0 OE[0] OE[4] - GPI[0] LOL GPO[0]

Output Enable

Clock

Select

General

Purpose

Configured as

Output

Fixed

Function

General

Purpose

Interrupt Functionality

Interrupt functionality includes an interrupt status flag for the PLL Loss-of-Lock Status (LOL), PLL Holdover Status (HOLD) and Input Reference Status (LOS[1:0]) that is set whenever there is an alarm on any of those signals. The Status Flag will remain set until the alarm has been cleared and a ‘1’ has been written to the Status Flag’s register location or if a reset occurs. Each Status Flag will also have an Interrupt Enable bit that will determine if that Status Flag is allowed to cause the Interrupt Status to be affected (enabled) or not (disabled). All Interrupt Enable bits will be in the disabled state after reset. The Device Interrupt Status flag and nINT output pin are asserted if any of the enabled Interrupt Status flags are set.

Device Hardware Configuration

The 8T49N285 supports an internal One-Time Programmable (OTP) memory that can be pre-programmed at the factory with one complete device configuration. If the device is set to read a configuration from an external, serial EEPROM, then the values read will overwrite the OTP-defined values.

This configuration can be over-written using the serial interface once reset is complete. Any configuration written via the programming interface needs to be re-written after any power cycle or reset. Please contact Renesas if a specific factory-programmed configuration is desired.

8T49N285 Datasheet

S Dev Addr + R

Current Read

From slave to master

Data 0 A

From master to sl ave

Sr = Repeated sta rt

S = Start

A = Acknowledge

Data 1 A A Data n P

P = Stop

A = Non-ackn owledge

S Dev Addr + W

Seq uenti al Re ad

A A Data 0 A A Data n PAOffset Addr MSB

Offset Addr LSB A Dev Addr + R A Data 1 A

S Dev Addr + W

Seq uenti al W rite

A A Da ta 0 A A Data n PAOffset Addr MSB Offset Addr LSB A Data 1 A

Device Start-up and Reset Behavior

The 8T49N285 has an internal power-up reset (POR) circuit and a Master Reset input pin nRST. If either is asserted, the device will be in the Reset State.

For highly programmable devices, it is common practice to reset the device immediately after the initial power-on sequence. Renesas recommends connecting the nRST input pin to a programmable logic source for optimal functionality. It is recommended that a minimum pulse width of 10ns be used to drive the nRST input pin.

While in the reset state (nRST input asserted or POR active), the device will operate as follows:

• All registers will return to & be held in their default states as

indicated in the applicable register description.

• All internal state machines will be in their reset conditions.

• The serial interface will not respond to read or write cycles.

• The GPIO signals will be configured as OE[3:0] inputs.

• All clock outputs will be disabled.

• All interrupt status and Interrupt Enable bits will be cleared,

negating the nINT signal.

Upon the latter of the internal POR circuit expiring or the nRST input negating, the device will exit reset and begin self-configuration.

The device will load an initial block of its internal registers using the configuration stored in the internal One-Time Programmable (OTP) memory. Once this step is complete, the 8T49N285 will check the register settings to see if it should load the remainder of its configuration from an external I continue loading from OTP. See the section on I2C Boot-up

Initialization Mode for details on how this is performed.

Once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the PLL to the selected source and begin operation. Once the PLL is locked, all the outputs derived from it will be synchronized and output phase adjustments can then be applied if desired.

C EEPROM at a defined address or

Serial Control Port Description

Serial Control Port Configuration Description

The device has a serial control port capable of responding as a slave

C compatible configuration to allow access to any of the

in an I internal registers for device programming or examination of internal status. All registers are configured to have default values. See the specifics for each register for details.

The device has the additional capability of becoming a master on the

C bus only for the purpose of reading its initial register

I configurations from a serial EEPROM on the I configuration to the serial EEPROM must be performed by another device on the same I2C bus or pre-programmed into the device prior to assembly.

I2C Mode Operation

The I2C interface is designed to fully support v2.1 of the I2C Specification for Normal and Fast mode operations. The device acts as a slave device on the I address defined in the Serial Interface Control register (0006h), as modified by the S_A0 input pin setting. The interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the block write will be written simultaneously.

For full electrical I

pull-up resistors for SDATA and SCLK. The internal pull-up resistors have a size of 51k typical.

C bus at 100kHz or 400kHz using the

C compliance, it is recommended to use external

C bus. Writing of the

Figure 3. I2C Slave Read and Write Cycle Sequencing

I2C Master Mode

From slave to master

From master to sl ave

Sr = Repeated sta rt

S = Start

A = Acknowledge

P = Stop

A = Non-ackn owledge

S Dev Addr + W

Seq uenti al Re ad (1-B yte O ff set Add res s)

A Data 0 A A Data n PAOffset AddrSrA Dev Addr + R A Data 1 A

S Dev Addr + W

Seq uen tial Re ad (2- Byte Of fset Add res s)

A A Data 0 A A Data n POffset Addr MSB Offset Addr LSB A Data 1 A

Dev Addr + R A

When operating in I2C mode, the 8T49N285 has the capability to become a bus master on the I2C bus for the purposes of reading its configuration from an external I will be supported.

As an I

C bus master, the 8T49N285 will support the following

functions:

• 7-bit addressing mode

• Base address register for EEPROM

• Validation of the read block via CCITT-8 CRC check against value

stored in last byte (E0h) of EEPROM

• Support for 100kHz and 400kHz operation with speed negotiation.

If bit d0 is set at Byte address 05h in the EEPROM, this will shift from 100kHz operation to 400kHz operation.

• Support for 1- or 2-byte addressing mode

• Master arbitration with programmable number of retries

C EEPROM. Only a block read cycle

8T49N285 Datasheet

• Fixed-period cycle response timer to prevent permanently hanging

the I

C bus.

• Read will abort with an alarm (BOOTFAIL) if any of the following conditions occur: Slave NACK, Arbitration Fail, Collision during Address Phase, CRC failure, Slave Response time-out

The 8T49N285 will not support the following functions:

•I

C General Call

• Slave clock stretching

C Start Byte protocol

•I

• EEPROM Chaining

• CBUS compatibility

• Responding to its own slave address when acting as a master

• Writing to external I used for booting

C devices including the external EEPROM

Figure 4. I2C Master Read Cycle Sequencing

I2C Boot-up Initialization Mode

If enabled (via the BOOT_EEP bit in the Startup register), once the nRST input has been de-asserted (high) and its internal power-up reset sequence has completed, the device will contend for ownership

of the I location on the I2C bus. The address of that memory location is kept in non-volatile memory in the Startup register. During the boot-up process, the device will not respond to serial control port accesses. Once the initialization process is complete, the contents of any of the device’s registers can be altered. It is the responsibility of the user to make any desired adjustments in initial values directly in the serial bus memory.

C bus to read its initial register settings from a memory

If a NACK is received to any of the read cycles performed by the device during the initialization process, or if the CRC does not match the one stored in address E0h of the EEPROM the process will be aborted and any uninitialized registers will remain with their default values. The BOOTFAIL bit (021Eh) in the Global Interrupt Status register will also be set in this event.

If the BOOTFAIL bit is set, then the LOL indicator will be set.

Contents of the EEPROM should be as shown in Table 5.

Table 5. External Serial EEPROM Contents

EEPROM Offset

(Hex)

00 1111111 1

01 1111111 1

02 1111111 1

03 1111111 1

04 1111111 1

05 1111111

06 1 8T49N285 Device I

07 0000000 0

08 - DF Desired contents of Device Registers 08h - DFh

E0 Serial EEPROM CRC

E1 - FF Unused

D7 D6 D5 D4 D3 D2 D1 D0

Contents

C Address [6:2] 0 1

8T49N285 Datasheet

Serial EEPROM

Speed Select

0 = 100kHz 1 = 400kHz

Register Descriptions

Table 6A. Register Blocks

0000 - 0001 Startup Control Registers

0002 - 0005 Device ID Control Registers

0006 - 0007 Serial Interface Control Registers

0008 - 003A Digital PLL Control Registers

003B - 006D Reserved

006E - 0076 GPIO Control Registers

0077 - 00AB Output Clock Control Registers

00AC - 00AF Analog PLL Control Registers

00B0 - 00B3 Reserved

00B4 - 00B8 Power-Down Control Registers

00B9 - 00C6 Input Monitor Control Register

00C7 Interrupt Enable Register

00C8 - 00CB Digital Phase Detector Control Registers

00CC - 01FF Reserved

0200 - 0203 Interrupt Status Registers

0204 Output Phase Adjustment Status Register

0205 - 020E Digital PLL Status Registers

020F - 0218 Reserved

0219 General-Purpose Input Status Register

021A - 021F Global Interrupt and Boot Status Register

0220 - 03FF Reserved

NOTE 1: Reserved. Always write 0 to this bit location. Read values are not defined.

8T49N285 Datasheet

Table 6B. Startup Control Register Bit Field Locations and Descriptions

Startup Control Register Block Field Locations

Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0

0000 EEP_RTY[4:0] Rsvd nBOOT_OTP nBOOT_EEP

0001 EEP_A15 EEP_ADDR[6:0]

Startup Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

EEP_RTY[4:0] R/W 00001b

nBOOT_OTP R/W NOTE 1

nBOOT_EEP R/W NOTE 1

EEP_A15 R/W NOTE 1 Serial EEPROM supports 15-bit addressing mode (multiple pages).

EEP_ADDR[6:0] R/W NOTE 1 I

Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined.

Select number of times arbitration for the I retried before being aborted. Note that this number does not include the original try.

Internal One-Time Programmable (OTP) memory usage on power-up: 0 = Load power-up configuration from OTP 1 = Only load 1st eight bytes from OTP

External EEPROM usage on power-up: 0 = Load power-up configuration from external serial EEPROM (overwrites OTP values) 1 = Don’t use external EEPROM

C base address for serial EEPROM.

C bus to read the serial EEPROM will be

NOTE 1: These values are specific to the device configuration and can be customized when ordering. Please refer to the FemtoClock NG

Universal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details.

Table 6C. Device ID Control Register Bit Field Locations and Descriptions

Device ID Register Control Block Field Locations

Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0

0002 REV_ID[3:0] DEV_ID[15:12]

0003 DEV_ID[11:4]

0004 DEV_ID[3:0] DASH_CODE[10:7]

0005 DASH_CODE[6:0] 1

Device ID Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

REV_ID[3:0] R/W 0000b Device revision.

DEV_ID[15:0] R/W 0603h Device ID code.

Device Dash Code:

DASH_CODE

[10:0]

NOTE 1: These values are specific to the device configuration and can be customized when ordering. Please refer to the FemtoClock NG

Universal Frequency Translator Ordering Product Information guide or custom datasheet addendum for more details.

R/W NOTE 1

Decimal value assigned by Renesas to identify the configuration loaded at the

factory. May be over-written by users at any time. Refer to FemtoClock NG Universal Frequency Translator Ordering Product Information guide to identify major

configuration parameters associated with this Dash Code value.

8T49N285 Datasheet

Table 6D. Serial Interface Control Register Bit Field Locations and Descriptions

Serial Interface Control Block Field Locations

Address (Hex)D7D6D5D4D3D2D1D0

0006 Rsvd UFTADD[6:2] UFTADD[1] UFTADD[0]

0007 Rsvd 1

Device ID Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

UFTADD[6:2] R/W NOTE 1 Configurable portion of I

UFTADD[1] R/O 0b I

UFTADD[0] R/O 0b

C Base Address bit 1. This bit is fixed as 0.

C Base Address bit 0. This address bit reflects the status of the S_A0 external input

pin. See Table 1, Pin Description Table.

Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined.

C Base Address (bits 6:2) for this device.

NOTE 1: These values are specific to the device configuration and can be customized when ordering. Generic dash codes -900 through -908,

-998 and-999 are available and programmed with the default I

C address of 1111100b. Please refer to the FemtoClock NG Universal

Frequency Translator Ordering Product Information guide for more details.

8T49N285 Datasheet

Table 6E. Digital PLL Input Control Register Bit Field Locations and Descriptions

Digital PLL Input Control Register Block Field Locations

Address (Hex)D7D6D5D4D3D2D1D0

0008 REFSEL[2:0] FBSEL[2:0] RVRT SWMODE

0009 11 10 PRI_1[1:0] PRI_0[1:0]

000A 1 1 REFDIS_1 REFDIS_0 Rsvd Rsvd STATE0[1:0]

000B Rsvd PRE_0[20:16]

000C PRE_0[15:8]

000D PRE_0[7:0]

000E Rsvd PRE_1[20:16]

000F PRE_1[15:8]

0010 PRE_1[7:0]

0011 Rsvd Rsvd

0012 Rsvd

0013 Rsvd

0014 Rsvd Rsvd

0015 Rsvd

0016 Rsvd

Digital PLL Input Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Input reference selection for Digital PLL: 000 = Automatic selection 001 = Manual selection by GPIO inputs

REFSEL[2:0] R/W 000b

FBSEL[2:0] R/W 000b

RVRT R/W 1b

SWMODE R/W 1b

PRI_0[1:0] R/W 00b

010 through 011 = Reserved 100 = Force selection of Input Reference 0 101 = Force selection of Input Reference 1 110 = Do not use 111 = Do not use

Feedback mode selection for Digital PLL: 000 through 011 = internal feedback divider 100 = external feedback from Input Reference 0 101 = external feedback from Input Reference 1 110 = do not use 111 = do not use

Automatic switching mode for Digital PLL: 0 = non-revertive switching 1 = revertive switching

Controls how Digital PLL adjusts output phase when switching between input references: 0 = Absorb any phase differences between old and new input references at the PLL output. Recommended for use when both input references are in the same clock domain. 1 = Limit the maximum rate of phase change at the PLL output when adjusting to a new input reference’s phase/frequency using phase-slope limiting as set in the SLEWn bits. Recommended for use when the input references are not in the same clock domain.

Switchover priority for Input Reference 0 when used by Digital PLL: 00 = 1st priority 01 = 2nd priority 10 = do not use 11 = do not use

Digital PLL Input Control Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Switchover priority for Input Reference 1 when used by Digital PLL: 00 = 1st priority

PRI_1[1:0] R/W 01b

REFDIS_0 R/W 0b

REFDIS_1 R/W 0b

STATE0[1:0] R/W 00b

PRE_0[20:0] R/W 000000h Pre-divider ratio for Input Reference 0 when used by Digital PLL.

PRE_1[20:0] R/W 000000h Pre-divider ratio for Input Reference 1 when used by Digital PLL.

Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined.

01 = 2nd priority 10 = do not use 11 = do not use

Input Reference 0 Switching Selection Disable for Digital PLL: 0 = Input Reference 0 is included in the switchover sequence for Digital PLL 1 = Input Reference 0 is not included in the switchover sequence for Digital PLL

Input Reference 1 Switching Selection Disable for Digital PLL: 0 = Input Reference 1 is included in the switchover sequence for Digital PLL 1 = Input Reference 1 is not included in the switchover sequence for Digital PLL

Digital PLL State Machine Control: 00 = Run automatically 01 = Force FREERUN state - set this if in Synthesizer Mode for PLL. 10 = Force NORMAL state 11 = Force HOLDOVER state

8T49N285 Datasheet

Table 6F. Digital PLL Feedback Control Register Bit Field Locations and Descriptions

Digital PLL Feedback Control Register Block Field Locations

Address (Hex)D7D6D5D4D3D2D1 D0

0017 M1_0[23:16]

0018 M1_0[15:8]

0019 M1_0[7:0]

001A M1_1[23:16]

001B M1_1[15:8]

001C M1_1[7:0]

001D Rsvd

001E Rsvd

001F Rsvd

0020 Rsvd

0021 Rsvd

0022 Rsvd

0023 LCKBW[3:0] ACQBW[3:0]

0024 LCKDAMP[2:0] ACQDAMP[2:0] PLLGAIN[1:0]

0025 Rsvd Rsvd Rsvd Rsvd

0026 Rsvd

0027 Rsvd

0028 Rsvd Rsvd

0029 Rsvd

002A Rsvd

002B FFh

002C FFh

002D FFh

002E FFh

002F SLEW[1:0] Rsvd HOLD[1:0] Rsvd HOLDAVG FASTLCK

0030 LOCK[7:0]

0031 Rsvd DSM_INT[8]

0032 DSM_INT[7:0]

0033 Rsvd DSMFRAC[20:16]

0034 DSMFRAC[15:8]

0035 DSMFRAC[7:0]

0036 Rsvd

0037 01h

0038 Rsvd

0039 Rsvd

003A DSM_ORD[1:0] DCXOGAIN[1:0] Rsvd DITHGAIN[2:0]

8T49N285 Datasheet

Digital PLL Feedback Configuration Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

M1_0[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 0 when used by Digital PLL.

M1_1[23:0] R/W 070000h M1 Feedback divider ratio for Input Reference 1 when used by Digital PLL.

Digital PLL Loop Bandwidth while locked: 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz

LCKBW[3:0] R/W 0111b

ACQBW[3:0] R/W 0111b

LCKDAMP[2:0] R/W 011b

ACQDAMP[2:0] R/W 011b

PLLGAIN[1:0] R/W 01b

0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved

Digital PLL Loop Bandwidth while locked: 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = 1.40625Hz 0100 = 2.8125Hz 0101 = 5.625Hz 0110 = 11.25Hz 0111 = 22.5Hz 1000 = 45Hz 1001 = 90Hz 1010 = 180Hz 1011 = 360Hz 1100 through 1111 = Reserved

Damping factor for Digital PLL while locked: 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved

Damping factor for Digital PLL while in acquisition (not locked): 000 = Reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = Reserved 111 = Reserved

Digital Loop Filter Gain Settings for Digital PLL: 00 = 0.5 01 = 1 10 = 1.5 11 = 2

Digital PLL Feedback Configuration Register Block Field Descriptions

Bit Field Name Field Type Default Value Description

Phase-slope control for Digital PLL: 00 = no limit - controlled by loop bandwidth of Digital PLL

SLEW[1:0] R/W 00b

01 = 83 µsec / sec 10 = 13 µsec / sec 11 = Reserved

Holdover Averaging mode selection for Digital PLL: 00 = Instantaneous mode - uses historical value 100ms prior to entering holdover

HOLD[1:0] R/W 00b

01 = Fast Average Mode 10 = Reserved 11 = Set VCO control voltage to VCC/2

Holdover Averaging Enable for Digital PLL:

HOLDAVG R/W 0b

0 = Holdover averaging disabled 1 = Holdover averaging enabled as defined in HOLD[1:0]

Enables Fast Lock operation for Digital PLL:

FASTLCK R/W 0b

0 = Normal locking using LCKBW & LCKDAMP fields in all cases 1 = Fast Lock mode using ACQBW & ACQDAMP when not phase locked and LCKBW & LCKDAMP once phase locked

LOCK[7:0] R/W 3Fh

Lock window size for Digital PLL. Unsigned 2’s complement binary number in steps of

2.5ns, giving a total range of 640ns. Do not program to 0.

Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This

DSM_INT[8:0] R/W 02Dh

implies that for crystal frequencies lower than 16MHz, the doubler circuit must be enabled.

DSMFRAC[20:0] R/W 000000h

Fractional portion of Delta-Sigma Modulator value. Divide this number by 2 determine the actual fraction.

Delta-Sigma Modulator Order for Digital PLL: 00 = Delta-Sigma Modulator disabled

DSM_ORD[1:0] R/W 11b

01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation

Multiplier applied to instantaneous frequency error before it is applied to the Digitally Controlled Oscillator in Digital PLL:

DCXOGAIN[1:0] R/W 01b

00 = 0.5 01 = 1 10 = 2 11 = 4

Dither Gain setting for Digital PLL: 000 = no dither 001 = Least Significant Bit (LSB) only 010 = 2 LSBs

DITHGAIN[2:0] R/W 000b

011 = 4 LSBs 100 = 8 LSBs 101 = 16 LSBs 110 = 32 LSBs 111 = 64 LSBs

Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined.

NOTE 1: Settings other than “00” may result in a significant increase in initial lock time.

8T49N285 Datasheet

+ 47 hidden pages

Renesas 8T49N285 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Description

Typical Applications

Features

8T49N285 Block Diagram

Pin Assignment

Pin Description and Pin Characteristic Tables

Principles of Operation

Crystal Input

Bypass Path

Input Clock Selection

Input Clock Monitor

Holdover

Input to Output Clock Frequency

Loop Filter and Bandwidth

Output Dividers

Output Divider Frequency Sources

Output Banks

Output Phase Control on Switchover

Input-Output Delay Control

Output Phase Alignment

Jitter and Wander Tolerance

Output Drivers

Power-Saving Modes

Status / Control Signals and Interrupts

Device Hardware Configuration

Device Start-up and Reset Behavior

Serial Control Port Description

Register Descriptions