Renesas 78K0/FB2-L, 78K0/FA2-L, 78K0/FY2-L User Manual

User’s Manual

78K0/Fx2-L

User’s Manual: Hardware

8-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

www.renesas.com

Rev.2.03 Jun 2012

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

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“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

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Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a

reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the tra nsition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If

an input pin is unconnected, it is possible that an internal input level may be generate d due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-do wn circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause

destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should b e used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be gr oun ded usin g a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS

device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the e xternal power suppl y after switching on th e internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse po wer on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degr adation of internal elements due to the passage of an abnormal current. The correct po wer on/off sequence must be judged separately for each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply

while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

How to Use This Manual

Readers This manual is intended for user engineers who wish to understand the functions of the

78K0/Fx2-L microcontrollers and design and develop application system s and programs for these devices.

The target products are as follows.

• 78K0/FY2-L:

• 78K0/FA2-L:

• 78K0/FB2-L:

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The manual for the 78K0/Fx2-L microcontrollers is separated into two parts: this manual

and the instructions edition (common to the 78K0 microcontrollers).

PD78F0854, 78F0855, 78F0856

PD78F0857, 78F0858, 78F0859

PD78F0864, 78F0865

78K0/Fx2-L

User’s Manual

(This Manual)

78K/0 Series

User’s Manual

Instructions

• Pin functions

• Internal block functions

• Interrupts

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• To gain a general understanding of functions: → Read this manual in the order of the CONTENTS. The mark “<R>” shows major

revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what.” field.

• How to interpret the register format: → For a bit number enclosed in angle brackets, the bit name is defined as a reserved

word in the RA78K0, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.

• To know details of the 78K0 microcontroller instructions: → Refer to the separate document 78K/0 Series Instructions User’s Manual

(U12326E).

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representations: Binary Decimal Hexadecimal

• CPU functions

• Instruction set

• Explanation of each instruction

...

×××× or ××××B

...

××××

...

××××H

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No. 78K0/Fx2-L User’s Manual U19856E 78K/0 Series Instructions User’s Manual U12326E 78K0 Microcontrollers User’s Manual Self Programming Library Type 01 U18274E 78K0 Microcontrollers Self Programming Library Type 01 Ver. 3.10 Operating Precautions (Notification

Document) 78K0 Microcontrollers User’s Manual EEPROM™ Emulation Library Type 01 78K0 Microcontrollers EEPROM Emulation Library Type 01 Ver.2.10 Operating Precautions (Notification

Document)

ZUD-CD-09-0122-E

U18275E ZUD-CD-09-0165-E

Documents Related to Development Tools (Hardware) (User’ s Manual)

Document Name Document No. QB-78K0FX2L In-Circuit Emulator To be prepared QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E QB-Programmer Programming GUI Operation U18527E

Documents Related to Flash Memory Programming (User’s Manual)

Document Name Document No. PG-FP5 Flash Memory Programmer U18865E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

Documents Related to Development Tools (Software)

Document Name Document No.

Note 1

Operation U17199E Language U17198E Structured Assembly Language U17197E

Note 1

Operation U17201E Language U17200E

Note 2

Operation U18601E SM+ System Simulator User’s Manual User Open Interface U18212E

ZUD-CD-07-0181-E

ZUD-CD-07-0103-E

U16934E U18416E

RA78K0 Ver.3.80 Assembler Package User’s Manual

78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document) CC78K0 Ver.3.70 C Compiler User’s Manual

78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification Document)

ID78K0-QB Ver.2.94 Integrated Debugger User’s Manual Operation U18330E ID78K0-QB Ver.3.00 Integrated Debugger User’s Manual Operation U18492E PM plus Ver.5.20 PM+ Ver.6.30

Note 3

Note 4

User’s Manual

Note 2

Notes 1. This document is installed into the PC together with the tool when installing RA78K0 Ver. 4.01. For

descriptions not included in “78K0 Assembler Package RA78K0 Ver. 4.01 Operating Prec autions”, refer to the user’s manual of RA78K0 Ver. 3.80.

2. This document is installed into the PC together with the tool when installing CC78K0 Ver. 4.00. For descriptions not included in “78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions”, refer to the user’s manual of CC78K0 Ver. 3.70.

3. PM plus Ver. 5.20 is the integrated development environment included with RA78K0 Ver. 3.80.

4. PM+ Ver. 6.30 is the integrated development environment included with RA78K0 Ver. 4.01. Software tool (assembler, C compiler, debugger, and simulator) products of different versions can be managed.

Other Documents

Document Name Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www2.renesas.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. Windows is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

CHAPTER 1 OUTLINE.............................................................................................................................15

1.1 Features......................................................................................................................................... 15

1.2 Ordering Information....................................................................................................................17

1.3 Pin Configuration (Top View)......................................................................................................19

1.3.1 78K0/FY2-L (16 pins)......................................................................................................................... 19

1.3.2 78K0/FA2-L (20 pins)......................................................................................................................... 20

1.3.3 78K0/FB2-L (30 pins)......................................................................................................................... 21

1.4 Block Diagram .............................................................................................................................. 22

1.4.1 78K0/FY2-L (16 pins)......................................................................................................................... 22

1.4.2 78K0/FA2-L (20 pins)......................................................................................................................... 23

1.4.3 78K0/FB2-L (30 pins)......................................................................................................................... 24

1.5 Outline of Functions.....................................................................................................................25

CHAPTER 2 PIN FUNCTIONS...............................................................................................................27

2.1 Pin Function List .......................................................................................................................... 27

2.1.1 78K0/FY2-L ....................................................................................................................................... 28

2.1.2 78K0/FA2-L ....................................................................................................................................... 30

2.1.3 78K0/FB2-L ....................................................................................................................................... 32

2.2 Description of Pin Functions ...................................................................................................... 35

2.2.1 P00 to P02 (port 0) ............................................................................................................................ 35

2.2.2 P20 to P27 (port 2) ............................................................................................................................ 36

2.2.3 P30 to P37 (port 3) ............................................................................................................................ 37

2.2.4 P60 and P61 (port 6) ......................................................................................................................... 39

2.2.5 P70 (port 7)........................................................................................................................................ 40

2.2.6 P121 and P122 (port 12) ................................................................................................................... 40

2.2.7 AVREF, AVSS, VDD, VSS........................................................................................................................ 42

2.2.8 RESET............................................................................................................................................... 42

2.2.9 REGC................................................................................................................................................42

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins...........................................43

CHAPTER 3 CPU ARCHITECTURE......................................................................................................47

3.1 Memory Space..............................................................................................................................47

3.1.1 Internal program memory space........................................................................................................ 51

3.1.2 Internal data memory space ..............................................................................................................53

3.1.3 Special function register (SFR) area.................................................................................................. 53

3.1.4 Data memory addressing................................................................................................................... 54

3.2 Processor Registers.....................................................................................................................57

3.2.1 Control registers ................................................................................................................................ 57

3.2.2 General-purpose registers................................................................................................................. 61

3.2.3 Special function registers (SFRs) ...................................................................................................... 62

3.3 Instruction Address Addressing.................................................................................................68

3.3.1 Relative addressing...........................................................................................................................68

3.3.2 Immediate addressing ....................................................................................................................... 69

3.3.3 Table indirect addressing................................................................................................................... 70

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3.3.4 Register addressing........................................................................................................................... 71

3.4 Operand Address Addressing .................................................................................................... 71

3.4.1 Implied addressing............................................................................................................................. 71

3.4.2 Register addressing........................................................................................................................... 72

3.4.3 Direct addressing............................................................................................................................... 73

3.4.4 Short direct addressing...................................................................................................................... 74

3.4.5 Special function register (SFR) addressing ....................................................................................... 75

3.4.6 Register indirect addressing .............................................................................................................. 76

3.4.7 Based addressing.............................................................................................................................. 77

3.4.8 Based indexed addressing ................................................................................................................ 78

3.4.9 Stack addressing...............................................................................................................................79

CHAPTER 4 PORT FUNCTIONS...........................................................................................................80

4.1 Port Functions..............................................................................................................................80

4.2 Port Configuration........................................................................................................................84

4.2.1 Port 0................................................................................................................................................. 85

4.2.2 Port 2................................................................................................................................................. 88

4.2.3 Port 3................................................................................................................................................. 94

4.2.4 Port 6............................................................................................................................................... 103

4.2.5 Port 7............................................................................................................................................... 106

4.2.6 Port 12............................................................................................................................................. 108

4.3 Registers Controlling Port Function ........................................................................................ 110

4.4 Port Function Operations..........................................................................................................120

4.4.1 Writing to I/O port............................................................................................................................. 120

4.4.2 Reading from I/O port......................................................................................................................120

4.4.3 Operations on I/O port.....................................................................................................................120

4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function...........121

4.6 Cautions on 1-bit Memory Manipulation Instruction for Port Register n (Pn) ..................... 127

CHAPTER 5 CLOCK GENERATOR ....................................................................................................128

5.1 Functions of Clock Generator...................................................................................................128

5.2 Configuration of Clock Generator ............................................................................................ 129

5.3 Registers Controlling Clock Generator....................................................................................131

5.4 System Clock Oscillator ............................................................................................................140

5.4.1 X1 oscillator.....................................................................................................................................140

5.4.2 Internal high-speed oscillator........................................................................................................... 141

5.4.3 Internal low-speed oscillator ............................................................................................................ 142

5.4.4 Prescaler ......................................................................................................................................... 142

5.4.5 PLL (Phase Locked Loop)...............................................................................................................142

5.5 Clock Generator Operation ....................................................................................................... 144

5.6 Controlling Clock........................................................................................................................147

5.6.1 Example of controlling high-speed system clock ............................................................................. 147

5.6.2 Example of controlling internal high-speed oscillation clock ............................................................ 150

5.6.3 Example of controlling internal low-speed oscillation clock.............................................................. 152

5.6.4 CPU clock status transition diagram................................................................................................ 153

5.6.5 Condition before changing CPU clock and processing after changing CPU clock........................... 156

5.6.6 Time required for switchover of CPU clock and main system clock................................................. 157

5.6.7 Conditions before clock oscillation is stopped ................................................................................. 158

5.6.8 Peripheral hardware and source clocks........................................................................................... 158

R01UH0068EJ0203 Rev.2.03 8 Jun 29, 2012

CHAPTER 6 16-BIT TIMERS X0 AND X1.........................................................................................159

6.1 Functions of 16-bit Timers X0 and X1......................................................................................159

6.2 Configuration of 16-bit Timers X0 and X1................................................................................ 161

6.3 Registers Controlling 16-bit Timers X0 and X1.......................................................................166

6.4 Operation of 16-Bit Timer/Event Counter 00............................................................................182

6.5 Operation of PWM output operation of 16-Bit Timers X0 and X1.......................................... 191

6.6 Interlocking Function with Comparator or INTP0 ...................................................................210

6.7 High-Impedance Output Control Function................................................................................219

6.7.1 Configuration of high-impedance output controller .......................................................................... 219

6.7.2 Registers controlling high-impedance output controller...................................................................220

6.7.3 High-impedance output control circuit setting procedure.................................................................224

CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00........................................................................... 226

7.1 Functions of 16-bit Timer/Event Counter 00............................................................................ 226

7.2 Configuration of 16-bit Timer/Event Counter 00 .....................................................................227

7.3 Registers Controlling 16-bit Timer/Event Counter 00.............................................................233

7.4 Operation of 16-bit Timer/Event Counter 00............................................................................241

7.4.1 Interval timer operation.................................................................................................................... 241

7.4.2 Square-wave output operation......................................................................................................... 244

7.4.3 External event counter operation..................................................................................................... 247

7.4.4 Operation in clear & start mode entered by TI000 pin valid edge input ........................................... 251

7.4.5 Free-running timer operation ........................................................................................................... 264

7.4.6 PPG output operation......................................................................................................................273

7.4.7 One-shot pulse output operation...................................................................................................... 277

7.4.8 Pulse width measurement operation................................................................................................ 282

7.5 Special Use of TM00................................................................................................................... 290

7.5.1 Rewriting CR010 during TM00 operation......................................................................................... 290

7.5.2 Setting LVS00 and LVR00............................................................................................................... 290

7.6 Cautions for 16-bit Timer/Event Counter 00............................................................................292

CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51............................................................................. 297

8.1 Functions of 8-bit Timer/Event Counter 51.............................................................................. 297

8.2 Configuration of 8-bit Timer/Event Counter 51.......................................................................297

8.3 Registers Controlling 8-bit Timer/Event Counter 51...............................................................299

8.4 Operations of 8-bit Timer/Event Counter 51............................................................................302

8.4.1 Operation as interval timer............................................................................................................... 302

8.4.2 Operation as external event counter................................................................................................ 304

8.5 Cautions for 8-bit Timer/Event Counter 51..............................................................................305

CHAPTER 9 8-BIT TIMER H1 ............................................................................................................. 306

9.1 Functions of 8-bit Timer H1.......................................................................................................306

9.2 Configuration of 8-bit Timer H1 ................................................................................................ 306

9.3 Registers Controlling 8-bit Timer H1........................................................................................309

9.4 Operation of 8-bit Timer H1....................................................................................................... 313

9.4.1 Operation as interval timer/square-wave output .............................................................................. 313

9.4.2 Operation as PWM output ............................................................................................................... 316

9.4.3 Carrier generator operation ............................................................................................................. 322

R01UH0068EJ0203 Rev.2.03 9 Jun 29, 2012

CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 329

10.1 Functions of Watchdog Timer................................................................................................. 329

10.2 Configuration of Watchdog Timer..........................................................................................330

10.3 Register Controlling Watchdog Timer....................................................................................331

10.4 Operation of Watchdog Timer.................................................................................................332

10.4.1 Controlling operation of watchdog timer ........................................................................................ 332

10.4.2 Setting overflow time of watchdog timer........................................................................................333

10.4.3 Setting window open period of watchdog timer.............................................................................. 334

CHAPTER 11 A/D CONVERTER .........................................................................................................336

11.1 Function of A/D Converter....................................................................................................... 336

11.2 Configuration of A/D Converter..............................................................................................338

11.3 Registers Used in A/D Converter............................................................................................340

11.4 A/D Converter Operations.......................................................................................................355

11.4.1 Basic operations of A/D converter (software trigger mode) ........................................................... 355

11.4.2 Basic operation of A/D converter (timer trigger mode)................................................................... 357

11.4.3 Input voltage and conversion results ............................................................................................. 359

11.4.4 A/D converter trigger mode selection............................................................................................. 360

11.4.5 A/D converter operation mode....................................................................................................... 360

11.5 How to Read A/D Converter Characteristics Table............................................................... 364

11.6 Cautions for A/D Converter..................................................................................................... 366

CHAPTER 12 COMPARATORS............................................................................................................370

12.1 Features of Comparator........................................................................................................... 370

12.2 Configurations of Comparator................................................................................................372

12.3 Registers Controlling Comparators ....................................................................................... 372

12.4 Operations of Comparators..................................................................................................... 388

12.4.1 Starting comparator operation (using internal reference voltage for comparator reference

voltage).......................................................................................................................................... 388

12.4.2 Starting comparator operation (using input voltage from CMPCOM pin for comparator

reference voltage).......................................................................................................................... 390

12.4.3 Stopping comparator operation...................................................................................................... 390

CHAPTER 13 SERIAL INTERFACE UART6 ......................................................................................391

13.1 Functions of Serial Interface UART6...................................................................................... 391

13.2 Configuration of Serial Interface UART6................................................................................395

13.3 Registers Controlling Serial Interface UART6.......................................................................398

13.4 Operation of Serial Interface UART6......................................................................................409

13.4.1 Operation stop mode.....................................................................................................................409

13.4.2 Asynchronous serial interface (UART) mode................................................................................. 410

13.4.3 Dedicated baud rate generator......................................................................................................424

13.4.4 Calculation of baud rate................................................................................................................. 426

CHAPTER 14 SERIAL INTERFACE IICA...........................................................................................431

14.1 Functions of Serial Interface IICA...........................................................................................431

14.2 Configuration of Serial Interface IICA .................................................................................... 434

14.3 Registers Controlling Serial Interface IICA............................................................................ 437

R01UH0068EJ0203 Rev.2.03 10 Jun 29, 2012

14.4 I2C Bus Mode Functions ..........................................................................................................450

14.4.1 Pin configuration............................................................................................................................ 450

14.4.2 Setting transfer clock by using IICWL and IICWH registers........................................................... 451

14.5 I2C Bus Definitions and Control Methods..............................................................................452

14.5.1 Start conditions.............................................................................................................................. 452

14.5.2 Addresses...................................................................................................................................... 453

14.5.3 Transfer direction specification......................................................................................................453

14.5.4 Acknowledge (ACK)....................................................................................................................... 454

14.5.5 Stop condition................................................................................................................................ 455

14.5.6 Wait ............................................................................................................................................... 456

14.5.7 Canceling wait ............................................................................................................................... 458

14.5.8 Interrupt request (INTIICA0) generation timing and wait control.................................................... 459

14.5.9 Address match detection method .................................................................................................. 460

14.5.10 Error detection............................................................................................................................. 460

14.5.11 Extension code............................................................................................................................460

14.5.12 Arbitration .................................................................................................................................... 461

14.5.13 Wakeup function.......................................................................................................................... 463

14.5.14 Communication reservation.........................................................................................................466

14.5.15 Cautions ...................................................................................................................................... 470

14.5.16 Communication operations..........................................................................................................471

14.5.17 Timing of I2C interrupt request (INTIICA0) occurrence ................................................................ 479

14.6 Timing Charts ...........................................................................................................................500

CHAPTER 15 SERIAL INTERFACE CSI11 ........................................................................................507

15.1 Functions of Serial Interface CSI11........................................................................................ 507

15.2 Configuration of Serial Interface CSI11..................................................................................507

15.3 Registers Controlling Serial Interface CSI11.........................................................................509

15.4 Operation of Serial Interface CSI11........................................................................................513

15.4.1 Operation stop mode.....................................................................................................................513

15.4.2 3-wire serial I/O mode.................................................................................................................... 514

CHAPTER 16 MULTIPLIER................................................................................................................... 525

16.1 Functions of Multiplier.............................................................................................................525

16.2 Configuration of Multiplier ...................................................................................................... 526

16.3 Operation of Multiplier.............................................................................................................528

CHAPTER 17 INTERRUPT FUNCTIONS.............................................................................................529

17.1 Interrupt Function Types.........................................................................................................529

17.2 Interrupt Sources and Configuration ..................................................................................... 529

17.3 Registers Controlling Interrupt Functions............................................................................. 534

17.4 Interrupt Servicing Operations ............................................................................................... 551

17.4.1 Maskable interrupt acknowledgment ............................................................................................. 551

17.4.2 Software interrupt request acknowledgment.................................................................................. 553

17.4.3 Multiple interrupt servicing............................................................................................................. 554

17.4.4 Interrupt request hold..................................................................................................................... 557

CHAPTER 18 STANDBY FUNCTION..................................................................................................558

18.1 Standby Function and Configuration..................................................................................... 558

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18.1.1 Standby function............................................................................................................................ 558

18.1.2 Registers controlling standby function...........................................................................................559

18.2 Standby Function Operation................................................................................................... 561

18.2.1 HALT mode.................................................................................................................................... 561

18.2.2 STOP mode................................................................................................................................... 565

CHAPTER 19 RESET FUNCTION........................................................................................................ 573

19.1 Register for Confirming Reset Source................................................................................... 582

CHAPTER 20 POWER-ON-CLEAR CIRCUIT...................................................................................... 583

20.1 Functions of Power-on-Clear Circuit......................................................................................583

20.2 Configuration of Power-on-Clear Circuit ............................................................................... 584

20.3 Operation of Power-on-Clear Circuit...................................................................................... 584

20.4 Cautions for Power-on-Clear Circuit......................................................................................587

CHAPTER 21 LOW-VOLTAGE DETECTOR.......................................................................................589

21.1 Functions of Low-Voltage Detector........................................................................................ 589

21.2 Configuration of Low-Voltage Detector ................................................................................. 590

21.3 Registers Controlling Low-Voltage Detector......................................................................... 590

21.4 Operation of Low-Voltage Detector........................................................................................593

21.4.1 When used as reset....................................................................................................................... 594

21.4.2 When used as interrupt.................................................................................................................. 597

21.5 Cautions for Low-Voltage Detector........................................................................................600

CHAPTER 22 REGULATOR ................................................................................................................. 603

22.1 Regulator Overview.................................................................................................................. 603

22.2 Registers Controlling Regulator............................................................................................. 603

22.3 Cautions for Self Programming..............................................................................................604

CHAPTER 23 OPTION BYTE...............................................................................................................605

23.1 Functions of Option Bytes ......................................................................................................605

23.2 Format of Option Byte..............................................................................................................606

CHAPTER 24 FLASH MEMORY.......................................................................................................... 611

24.1 Internal Memory Size Switching Register.............................................................................. 611

24.2 Writing with Flash Memory Programmer...............................................................................612

24.3 Programming Environment.....................................................................................................613

24.4 Connection of Pins on Board..................................................................................................614

24.4.1 TOOL pins ..................................................................................................................................... 614

24.4.2 RESET pin..................................................................................................................................... 615

24.4.3 Port pins ........................................................................................................................................ 615

24.4.4 REGC pin ...................................................................................................................................... 615

24.4.5 Other signal pins............................................................................................................................ 615

24.4.6 Power supply.................................................................................................................................615

24.4.7 On-board writing when connecting crystal/ceramic resonator ....................................................... 616

24.5 Programming Method ..............................................................................................................617

24.5.1 Controlling flash memory............................................................................................................... 617

R01UH0068EJ0203 Rev.2.03 12 Jun 29, 2012

24.5.2 Flash memory programming mode................................................................................................ 617

24.5.3 Communication commands ........................................................................................................... 617

24.6 Security Settings......................................................................................................................619

24.7 Processing Time for Each Command When PG-FP5 Is Used (Reference)......................... 621

24.8 Flash Memory Programming by Self-Programming.............................................................623

24.8.1 Register controlling self programming mode ................................................................................. 624

24.8.2 Flow of self programming (Rewriting Flash Memory)..................................................................... 624

24.8.3 Boot swap function ........................................................................................................................ 626

24.9 Creating ROM Code to Place Order for Previously Written Product .................................. 628

24.9.1 Procedure for using ROM code to place an order.......................................................................... 628

CHAPTER 25 ON-CHIP DEBUG FUNCTION .....................................................................................629

25.1 Connecting QB-MINI2 to 78K0/Fx2-L Microcontrollers ........................................................ 629

25.2 On-Chip Debug Security ID .....................................................................................................632

25.3 Securing of User Resources...................................................................................................633

CHAPTER 26 INSTRUCTION SET.......................................................................................................634

26.1 Conventions Used in Operation List......................................................................................634

26.1.1 Operand identifiers and specification methods..............................................................................634

26.1.2 Description of operation column .................................................................................................... 635

26.1.3 Description of flag operation column.............................................................................................. 635

26.2 Operation List...........................................................................................................................636

26.3 Instructions Listed by Addressing Type................................................................................ 644

CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)..................................647

CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................673

CHAPTER 29 PACKAGE DRAWINGS................................................................................................699

29.1 78K0/FY2-L............................................................................................................... .................699

29.2 78K0/FA2-L................................................................................................................................700

29.3 78K0/FB2-L................................................................................................................................701

CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS...........................................................702

CHAPTER 31 CAUTIONS FOR WAIT.................................................................................................703

31.1 Cautions for Wait......................................................................................................................703

31.2 Peripheral Hardware That Generates Wait ............................................................................703

APPENDIX A DEVELOPMENT TOOLS...............................................................................................705

A.1 Software Package......................................................................................................................708

A.2 Language Processing Software...............................................................................................708

A.3 Flash Memory Programming Tools..........................................................................................709

A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 ........................................................ 709

A.3.2 When using on-chip debug emulator with programming function QB-MINI2...................................709

A.4 Debugging Tools (Hardware).................................................................................................... 710

R01UH0068EJ0203 Rev.2.03 13 Jun 29, 2012

A.4.1 When using in-circuit emulator........................................................................................................710

A.4.2 When using on-chip debug emulator with programming function QB-MINI2...................................710

A.5 Debugging Tools (Software).....................................................................................................710

APPENDIX B REVISION HISTORY ..................................................................................................... 711

B.1 Major Revisions in This Edition ............................................................................................... 711

B.2 Revision History of Preceding Editions ..................................................................................712

R01UH0068EJ0203 Rev.2.03 14 Jun 29, 2012

78K0/Fx2-L RENESAS MCU

R01UH0068EJ0203

Jun 29, 2012

CHAPTER 1 OUTLINE

1.1 Features

 78K0 CPU core  I/O ports, ROM and RAM capacities

Item Products 78K0/FY2-L (16 pins) 11 (CMOS I/O: 9, CMOS input: 2) 4 KB to 16 KB 384 bytes to 768 bytes 78K0/FA2-L (20 pins) 15 (CMOS I/O: 13, CMOS input: 2) 78K0/FB2-L (30 pins) 24 (CMOS I/O: 22, CMOS input: 2)

I/O Ports

Program Memory

(Flash Memory)

8 KB and 16 KB 512 bytes and 768 bytes

 Low power consumption (VDD = 3.0 V, TA = −40 to +85°C)

• Internal high-speed oscillator operation mode: 220 μA (TYP.) (fCPU = 1 MHz operation)

• STOP mode: 0.65

A (TYP.) (fIL = 30 kHz operation)

 Clock

• High-speed system clock … Selected from the following three sources

- Ceramic/crystal resonator: 2 to 20 MHz

- External clock: 2 to 20 MHz

- Internal high-speed oscillator:

4 MHz ±2% (−20 to +70°C), 4 MHz ±3% (−40 to +85°C), or 8 MHz ±3% (−40 to +85°C)

• Internal low-speed oscillator 30 kHz (TYP.) … Watchdog timer, timer clock in intermittent operation

 Timer

• 16-bit timer X … PWM output, operation in conjunction with an external signal, synchronous output of up to four channels (available only in 78K0/FB2-L), A/D conversion trigger generation

• 16-bit timer/event counter … PPG output, capture input, external event co unter input

• 8-bit timer H1 … PWM output, operable with low-speed internal oscillation clock

• 8-bit timer/event counter 51 … PWM output, external event counter input

• Watchdog timer … Operable with internal low-speed oscillation clock

Item Products 78K0/FY2-L (16 pins) 78K0/FA2-L (20 pins) 78K0/FB2-L (30 pins) 2 ch

1 ch

16-bit Timer

16-bit Timer/

Event Counter

1 ch Timer H1: 1 ch

8-bit Timer Watchdog Timer

Timer 51: 1 ch

Data Memory (Internal

High-Speed RAM)

1 ch

Rev.2.03

R01UH0068EJ0203 Rev.2.03 15 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

 Serial interface

• UART6 … Asynchronous 2-wire serial interface

• IICA … Clock synchronous 2-wire serial interface, multimaster supported, standby can be released upon address match in slave mode

• CSI11 … Clock synchronous 3-wire serial interface, operable as SPI in slave mode

Item Products

78K0/FY2-L (16 pins) 78K0/FA2-L (20 pins) 78K0/FB2-L (30 pins)

 Multiplier (8 bits × 8 bits = 16 bits, 16 bits × 16 bits = 32 bits, 1-clock operation)  10-bit resolution A/D conversion

• 78K0/FY2-L: 4 ch

• 78K0/FA2-L: 6 ch

• 78K0/FB2-L: 9 ch  Comparator

• 78K0/FY2-L: 1 ch

• 78K0/FA2-L: 3 ch

• 78K0/FB2-L: 3 ch

 Power-on-clear (POC) circuit  Low-voltage detector (LVI) circuit (An interrupt/reset (selectable) is generated when the detection voltage is

reached))

• Detection voltage: Selectable from sixteen levels between 1.91 and 4.22 V  Single-power-supply flash memory

• Flash self programming enabled

• Software protection function: Protected from outside party copying (no flash reading command)  Safety function

• Watchdog timer operated by clock independent from CPU

… A hang-up can be detected even if the system clock stops

• Supply voltage drop detectable by LVI … Appropriate processi ng can be executed before the supply voltage drops below the operation voltage

• Equipped with option byte function … Important system operation settings set in hardware

 On-chip debug function …Available to control for the target device, and to reference memory  Assembler and C language supported  Enhanced development environment

• Support for full-function emulator (IECUBE), and simplified emulator (MINICUBE2)

 Power supply voltage: V  Operating ambient temperature: • (A) grade products: T

• (A2) grade products: TA = −40 to +125°C

UART6 IICA CSI11

1 ch 1 ch

1 ch

DD = 1.8 to 5.5 V

A = −40 to +85°C

−

R01UH0068EJ0203 Rev.2.03 16 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.2 Ordering Information

[Part Number]

PD78F08xy ΔΔ × - ××× -×

Product Type F Flash memory version

[Example of Part Number]

PD78F08 54 MA-A-FAA-G

Semiconductor G

Quality Grade A Special (TA = −40 to +85°C) A2 Special (TA = −40 to +125°C)

54, 55, 56 (FY2-L)

57, 58, 59 (FA2-L)

64, 65 (FB2-L)

54, 57 384 bytes 4 KB 55, 58, 64 512 bytes 8 KB 56, 59, 65 768 bytes 16 KB

Leadfree

xy ΔΔ - xxx Package Type

Lead-free Special 16-pin plastic SSOP (5.72 mm (225))

High-speed RAM: 384 bytes, flash Memory: 4 KB

Flash memory version

Product contains no lead in any area (Terminal finish is Ni/Pd/Au plating)

MA-FAA 16-pin plastic SSOP (5.72 mm (225))

MC-CAA 20-pin plastic SSOP (7.62 mm (300))

MC-CAB 30-pin plastic SSOP (7.62 mm (300))

High-speed

RAM Capacity

Flash Memory

Capacity

R01UH0068EJ0203 Rev.2.03 17 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

[List of Part Number]

78K0/Fx2-L

microcontrollers

78K0/FY2-L

78K0/FA2-L

78K0/FB2-L

Package Part Number

16-pin plastic SSOP (5.72 mm (225))

20-pin plastic SSOP (7.62 mm (300))

30-pin plastic SSOP (7.62 mm (300))

PD78F0854MAA-FAA-G, 78F0855MAA-FAA-G, 78F0856MAA-FAA-G,

78F0854MAA2-FAA-G, 78F0855MAA2-FAA-G, 78F0856MAA2-FAA-G

PD78F0857MCA-CAA-G, 78F0858MCA-CAA-G, 78F0859MCA-CAA-G,

78F0857MCA2-CAA-G, 78F0858MCA2-CAA-G, 78F0859MCA2-CAA-G

PD78F0864MCA-CAB-G, 78F0865MCA-CAB-G,

78F0864MCA2-CAB-G, 78F0865MCA2-CAB-G

R01UH0068EJ0203 Rev.2.03 18 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.3 Pin Configuration (Top View)

1.3.1 78K0/FY2-L (16 pins)

• 16-pin plastic SSOP (5.72 mm (225))

P60/SCLA0/TxD6

P61/SDAA0/RxD6

RESET

P122/X2/EXCLK/TOOLD0

P121/X1/TOOLC0

REGC

V V

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

REF

AV ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23/CMP2+ P00/TI000/INTP0 P01/TO00/TI010 P30/TOH1/TI51/INTP1

ANI0 to ANI3: Analog Input RESET: Reset

REF: Analog Reference RxD6: Receive Data

AV Voltage SCLA0: Serial Clock Input/Output CMP2+: Comparator Input SDAA0: Serial Data Input/Output EXCLK: External Clock Input TI000, TI010, TI51: Timer Input (Main System Clock) TO00, TOH1: Timer Output INTP0, INTP1: External Interrupt TOOLC0: Clock Input for Tool Input TOOLD0: Data Input/Output for Tool P00, P01: Port 0 TxD6: Transmit Data P20 to P23: Port 2 V P30: Port 3 V P60, P61: Port 6 X1, X2: Crystal Oscillator P121, P122: Port 12 (Main System Clock) REGC: Regulator Capacitance

DD: Power Supply SS: Ground

Cautions 1. V

SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to

a stabilized GND (= 0 V).

2. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

F).

3. ANI0/P20, ANI1/P21, ANI2/P22, and ANI3/P23/CMP2+ are set in the analog input mode after release of reset.

R01UH0068EJ0203 Rev.2.03 19 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.3.2 78K0/FA2-L (20 pins)

• 20-pin plastic SSOP (7.62 mm (300))

ANI5/P25/CMP1+ ANI4/P24/CMP0+

P60/SCLA0/TxD6 P61/SDAA0/RxD6

RESET

P122/X2/EXCLK/TOOLD0

P121/X1/TOOLC0

REGC

1 2 3 4 5 6 7 8

9 10

20 19 18 17 16 15 14 13 12 11

ANI0 to ANI5: Analog Input RESET: Reset

REF: Analog Reference RxD6: Receive Data

AV Voltage SCLA0: Serial Clock Input/Output CMP0+ to CMP2+: Comparator Input SDAA0: Serial Data Input/Output EXCLK: External Clock Input TI000, TI010, TI51: Timer Input (Main System Clock) TO00, TOH1: Timer Output INTP0 to INTP3: External Interrupt TOOLC0, TOOLC1: Clock Input for Tool Input TOOLD0, TOOLD1: Data Input/Output for Tool P00, P01: Port 0 TOX00, TOX01: Timer Output P20 to P25: Port 2 TxD6: Transmit Data P30 to P32: Port 3 V P60, P61: Port 6 V P121, P122: Port 12 X1, X2: Crystal Oscillator REGC: Regulator Capacitance (Main System Clock)

DD: Power Supply SS: Ground

Cautions 1. V

SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to

a stabilized GND (= 0 V).

2. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

3. ANI0/P20, ANI1/P21, ANI2/P22, ANI3/P23/CMP2+, ANI4/P24/CMP0+, and ANI5/P25/CMP1+ are set in the analog input mode after release of reset.

REF

ANI0/P20 ANI1/P21 ANI2/P22 ANI3/P23/CMP2+

P00/TI000/INTP0 P01/TI010/TO00 P30/TOH1/TI51/INTP1 P31/TOX00/INTP2/TOOLC1 P32/TOX01/INTP3/TOOLD1

F).

R01UH0068EJ0203 Rev.2.03 20 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.3.3 78K0/FB2-L (30 pins)

• 30-pin plastic SSOP (7.62 mm (300))

ANI6/P26/CMPCOM

ANI5/P25/CMP1+ ANI4/P24/CMP0+ P60/SCLA0/TxD6

P61/SDAA0/RxD6

P02/SSI11/INTP5

RESET

P122/X2/EXCLK/TOOLD0

P121/X1/TOOLC0/<TI000>/<INTP0>

REGC

V V

P37/SO11

P36/SI11

P35/SCK11

1 2 3 4 5 6 7 8 9 10

11 12 13

30 29 28 27 26 25 24 23 22 21 20 19 18 1714

ANI8/P70 ANI7/P27 AV

REF

ANI0/P20 ANI1/P21 ANI2/P22

ANI3/P23/CMP2+ P00/TI000/INTP0 P01/TO00/TI010 P30/TOH1/TI51/INTP1 P31/TOX00/INTP2/TOOLC1 P32/TOX01/INTP3/TOOLD1

P33/TOX10 P34/TOX11/INTP4

ANI0 to ANI8: Analog Input RxD6: Receive Data

REF: Analog Reference Voltage SCLA0, SCK11: Serial Clock Input/Output

SS: Analog Ground SDAA0: Serial Data Input/Output

AV CMP0+ to CMP2+: Comparator Input SI11: Serial Data Input

SO11: Serial Data Output EXCLK: External Clock Input

(Main System Clock) SSI11: Serial Interface Chip CMPCOM: Comparator Common Input TI000, TI010, TI51: Timer Input INTP0 to INTP5: External Interrupt Input TO00, TOH1: Timer Output P00 to P02: Port 0 TOOLC0, TOOLC1: Clock Input for Tool P20 to P27: Port 2 TOOLD0, TOOLD1: Data Input/Output for Tool P30 to P37: Port 3 TOX00, TOX01, P60, P61: Port 6 TOX10, TOX11: Timer Output P70: Port 7 TxD6: Transmit Data P121, P122: Port 12 V REGC: Regulator Capacitance V RESET: Reset X1, X2: Crystal Oscillator (Main System Clock)

DD: Power Supply SS: Ground

Cautions 1. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

F).

2. ANI0/P20, ANI1/P21, ANI2/P22, ANI3/P23/CMP2+, ANI4/P24/CMP0+, ANI5/P25/CMP1+, ANI6/P26/CMPCOM, ANI7/P27, and ANI8/P70 are set in the analog input mode after release of reset.

Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL).

R01UH0068EJ0203 Rev.2.03 21 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.4 Block Diagram

1.4.1 78K0/FY2-L (16 pins)

TO00/TI010/P01

TI000/P00

RxD6/P61<LINSEL>

TI51/P30

TOH1/P30

RxD6/P61

TxD6/P60

SDAA0/P61

SCLA0/P60

REF

ANI0/P20-ANI3/P23

CMP2+/P23

16-bit TIMER

16-bit TIMER/ EVENT COUNTER 00

8-bit TIMER

INTERNAL

LOW-SPEED

OSCILLATOR

WATCHDOG TIMER

SERIAL INTERFACE UART6

LINSEL

SERIAL INTERFACE IICA

A/D CONVERTER

COMPARATOR

78K/0

CPU

CORE

INTERNAL

HIGH-SPEED

RAM

FLASH

MEMORY

PORT 0

PORT 2

PORT 3

PORT 6

PORT 12

POWER ON CLEAR/

LOW VOLTAGE

INDICATOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

INTERNAL

HIGH-SPEED OSCILLATOR

VOLTAGE REGULATOR

P00, P01

P20-P23

P30

P60, P61

P121, P122

POC/LVI

CONTROL

TOOLC0/X1 TOOLD0/X2

RESET X1/P121

X2/EXCLK/P122

REGC

RxD6/P61<LINSEL>

INTP0/P00

INTP1/P30

INTERRUPT

CONTROL

Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to

a stabilized GND (= 0 V).

2. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

F).

3. ANI0/P20, ANI1/P21, ANI2/P22, and ANI3/P23/CMP2+ are set in the analog input mode after release of reset.

R01UH0068EJ0203 Rev.2.03 22 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.4.2 78K0/FA2-L (20 pins)

TOX00/P31 TOX01/P32

16-bit TIMER

PORT 0

P00, P01

TO00/TI010/P01

RxD6/P61<LINSEL>

INTP1/P30, INTP2/P31, INTP3/P32

TI000/P00

TI51/P30

TOH1/P30

RxD6/P61

TxD6/P60

SDAA0/P61 SCLA0/P60

REF

ANI0/P20-ANI5/P25

CMP+/P24, CMP1+/P25, CMP2+/P23

RxD6/P61<LINSEL>

INTP0/P00

16-bit TIMER/ EVENT COUNTER 00

8-bit TIMER

LOW-SPEED

OSCILLATOR

WATCHDOG TIMER

SERIAL INTERFACE UART6

SERIAL INTERFACE IICA

A/D CONVERTER

COMPARATOR

INTERRUPT

CONTROL

INTERNAL

LINSEL

78K/0

CPU

CORE

INTERNAL

HIGH-SPEED

RAM

FLASH

MEMORY

PORT 2

PORT 3

PORT 6

PORT 12

POWER ON CLEAR/

LOW VOLTAGE

INDICATOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

INTERNAL

HIGH-SPEED OSCILLATOR

VOLTAGE REGULATOR

P20-P25

P30-P32

P60, P61

P121, P122

POC/LVI

CONTROL

TOOLC0/X1, TOOLC1/P31 TOOLD0/X2, TOOLD1/P32

RESET X1/P121

X2/EXCLK/P122

REGC

Cautions 1. V

SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to

a stabilized GND (= 0 V).

2. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

F).

3. ANI0/P20, ANI1/P21, ANI2/P22, ANI3/P23/CMP2+, ANI4/P24/CMP0+, and ANI5/P25/CMP1+ are set in the analog input mode after release of reset.

R01UH0068EJ0203 Rev.2.03 23 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.4.3 78K0/FB2-L (30 pins)

TOX00/P31 TOX01/P32

16-bit TIMER

PORT 0

P00 to P02

TOX10/P33 TOX11/P34

TO00/TI010/P01

<TI000>/P121

TI000/P00

RxD6/P61 (LINSEL)

TI51/P30

TOH1/P30

RxD6/P61

TxD6/P60

SDAA0/P61 SCLA0/P60

SCK11/P35

SI11/P36

SO11/P37

SSI11/P02

ANI0/P20 to ANI7/P27

ANI8/P70

CMP0+/P24, CMP1+/P25,

CMP2+/P23

CMPCOM/P26

REF

16-bit TIMER

16-bit TIMER/ EVENT COUNTER 00

8-bit TIMER/ EVENT COUNTER 51

8-bit TIMER

LOW-SPEED

OSCILLATOR

WATCHDOG TIMER

SERIAL INTERFACE UART6

SERIAL INTERFACE IICA

SERIAL INTERFACE CSI11

A/D CONVERTER

COMPARATOR

INTERNAL

LINSEL

78K/0

CPU

CORE

INTERNAL

HIGH-SPEED

RAM

FLASH

MEMORY

PORT 2

PORT 3

PORT 6

PORT 7

PORT 12

POWER ON CLEAR/

LOW VOLTAGE

INDICATOR

RESET CONTROL

ON-CHIP DEBUG

SYSTEM

CONTROL

INTERNAL

HIGH-SPEED OSCILLATOR

VOLTAGE REGULATOR

P20 to P27

P30 to P37

P60, P61

P70

P121, P122

POC/LVI

CONTROL

TOOLC0/X1, TOOLC1/P31 TOOLD0/X2, TOOLD1/P32

RESET X1/P121

X2/EXCLK/P122

REGC

TxD6/P60 (LINSEL)

INTP0/P00

INTP1/P30 to INTP3/P32,

<INTP0>/P121

INTP4/P34, INTP5/P02

INTERRUPT

CONTROL

Cautions 1. Connect the REGC pin to V

SS via a capacitor (0.47 to 1

F).

2. ANI0/P20, ANI1/P21, ANI2/P22, ANI3/P23/CMP2+, ANI4/P24/CMP0+, ANI5/P25/CMP1+, ANI6/P26/CMPCOM, ANI7/P27, and ANI8/P70 are set in the analog input mode after release of reset.

Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL).

R01UH0068EJ0203 Rev.2.03 24 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

1.5 Outline of Functions

(1/2)

78K0/FY2-L 78K0/FA2-L 78K0/FB2-L Item

16 pins 20 pins 30 pins

Internal memory

Memory space

General-purpose registers Instruction set

I/O ports

Flash memory

4 KB to 16 KB 8 KB and 16 KB

(self-programming supported)

High-Speed RAM

384 bytes to 768 bytes 512 bytes and 768 bytes 64 KB

High-speed system (crystal/ceramic oscillation, external clock input)

Main

Internal high-

Clock

speed oscillation

Internal low-speed

2 to 20 MHz 2 to 5 MHz: V

4 MHz ±2% (T to +85°C): V

30 kHz (TYP.): V

Note 1

: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 2.7 to 5.5 V, or

DD = 1.8 to 5.5 V

A = −20 to +70°C)

DD = 1.8 to 5.5 V

Note 2

Note 1

, 4 MHz ±3% (TA = −40 to +85°C)

Note 2

Note 1

oscillation

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

• 8-bit operation, 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

16 bits (TMX) 16 bits (TM0)

11 (CMOS I/O: 9, CMOS input: 2)

1 ch 1 ch (PWM output: 2) 2 ch (PWM output: 4) 1 ch (capture input: 1)

15 (CMOS I/O: 13, CMOS input: 2)

24 (CMOS I/O: 22, CMOS input: 2)

1 ch (PPG output: 1, capture input: 2)

8 bits (TM51)

Timer

8 bits (TMH1) Watchdog (WDT)

1 ch 1 ch (PWM output: 1) 1 ch

Notes 1. When using a 4 MHz clock, operation at 20 MHz is possible by using PLL.

2. This is applicable to a (A) grade product. See CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) for products with (A2) grade product.

, or 8 MHz ±3% (TA = −40

R01UH0068EJ0203 Rev.2.03 25 Jun 29, 2012

78K0/Fx2-L CHAPTER 1 OUTLINE

(2/2)

78K0/FY2-L 78K0/FA2-L 78K0/FB2-L Item

16 pins 20 pins 30 pins

Serial interface

10-bit A/D converter Comparator Multiplier Vectored interrupt

sources

Reset

On-chip debug function

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature

Package

UART6 IICA CSI11

External Internal

1 ch 1 ch

– 1 ch 4 ch 6 ch 9 ch 1 ch 3 ch 8 bits × 8 bits = 16 bits, 16 bits × 16 bits = 32 bits 3 7 9 11 11 13

• Reset using RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-clear (POC)

• Internal reset by low-voltage detector (LVI) Provided

(A) grade products: TA = –40 to +85°C, (A2) grade products: TA = −40 to +125°C

16-pin plastic SSOP (5.72 mm (225))

20-pin plastic SSOP (7.62 mm (300))

30-pin plastic SSOP (7.62 mm (300))

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78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

There are two types of pin I/O buffer power supplies: AV

and the pins is shown below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins AVREF VDD

P20 to P27, P70 Pins other than P20 to P27, P70

Note 78K0/FY2-L: P20 to P23 78K0/FA2-L: P20 to P25 78K0/FB2-L: P20 to P27, P70

REF and VDD. The relationship between these power supplies

Note

R01UH0068EJ0203 Rev.2.03 27 Jun 29, 2012

78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS

2.1.1 78K0/FY2-L

(1) Port functions: 78K0/FY2-L

Function Name I/O Function After Reset Alternate Function P00 TI000/INTP0 P01

P20 ANI0 P21 ANI1 P22 ANI2 P23 P30 I/O

P60 SCLA0/TxD6

P61

P121 X1/TOOLC0 P122

I/O

Input

Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 2. 4-bit I/O port. Input/output can be specified in 1-bit units.

Port 3. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 6. 2-bit I/O port. Input/output can be specified in 1-bit units. Input can be set to SMBus input buffer in 1-bit units. Output can be set to N-ch open-drain output (V tolerance). Use of an on-chip pull-up resistor can be specified by a software setting.

Port 12. 2-bit input-only port.

Input port

TO00/TI010

Analog input

ANI3/CMP2+

Input port TOH1/TI51/INTP1

Input port

SDAA0/RxD6

Input port

X2/EXCLK/TOOLD0

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78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS

(2) Non-port functions: 78K0/FY2-L

Function Name I/O Function After Reset Alternate Function ANI0 P20 ANI1 P21

ANI2 P22 ANI3 CMP2+ Input Comparator input Analog input P23/ANI31 INTP0 P00/TI000 INTP1

REGC

RESET Input System reset input Reset Input RxD6 Input Serial data input to UART6 P61/SDAA0 TxD6 Output SCLA0 Clock input/output for I2C P60/TxD6 SDAA0 TI000 External count clock input to 16-bit timer/event counter

TI010

TI51 Input External count clock input to 8-bit timer/event counter 51 Input port P30/TOH1/INTP1 TO00 Output 16-bit timer/event counter 00 output Input port P01/TI010 TOH1 Output 8-bit timer H1 output Input port P30/TI51/INTP1 X1 P121/TOOLC0 X2 EXCLK Input External clock input for main system clock Input port P122/X2/TOOLD0 VDD Positive power supply for pins other than port 2 AVREF

VSS TOOLC0 Input Clock input for flash memory programmer/on-chip

TOOLD0 I/O Data I/O for flash memory programmer/on-chip debugger

Input A/D converter analog input Analog input

Input

I/O

Input

External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified

Connecting regulator output (2.0 V/2.4 V) stabilization

− capacitance for internal operation. Connect to V

Serial data output from UART6

Serial data I/O for I2C

00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00

Capture trigger input to capture register (CR000) of 16bit timer/event counter 00

Connecting resonator for main system clock Input port

−

A/D converter reference voltage input and positive power supply for port 2 and A/D converter

Ground potential

−

debugger

SS via a capacitor (0.47 to 1

F).

Input port

− −

Input port

− −

Input port

P23

P30/TOH1/TI51

−

P60/SCLA0

P61/RxD6 P00/INTP0

P01/TO00

P122/EXCLK/TOOLD0

P121/X1

P122/X2/EXCLK

R01UH0068EJ0203 Rev.2.03 29 Jun 29, 2012

78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS

2.1.2 78K0/FA2-L

(1) Port functions: 78K0/FA2-L

Function Name I/O Function After Reset Alternate Function P00 TI000/INTP0 P01

P20 ANI0 P21 ANI1 P22 ANI2 P23 ANI3/CMP2+ P24 ANI4/CMP0+ P25 P30 TOH1/TI51/INTP1 P31 TOX00/INTP2/

P32

P60 SCLA0/TxD6

P61

P121 X1/TOOLC0 P122

I/O

Input

(2) Non-port functions : 78K0/FA2-L (1/2)

Port 0. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 2. 6-bit I/O port. Input/output can be specified in 1-bit units.

Port 3. 3-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 12. 2-bit input-only port.

Input port

TO00/TI010

Analog input

ANI5/CMP1+

Input port

TOOLC1 TOX01/INTP3/ TOOLD1

Input port

SDAA0/RxD6

Input port

X2/EXCLK/TOOLD0

Function Name I/O Function After Reset Alternate Function ANI0 P20 ANI1 P21

ANI2 P22 ANI3 P23 ANI4 P24 ANI5

Input A/D converter analog input Analog input

P25

R01UH0068EJ0203 Rev.2.03 30 Jun 29, 2012

+ 690 hidden pages

Renesas 78K0/FB2-L, 78K0/FA2-L, 78K0/FY2-L User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Notice

NOTES FOR CMOS DEVICES

How to Use This Manual

CONTENTS

CHAPTER 1 OUTLINE

1.1 Features

1.2 Ordering Information

1.3 Pin Configuration (Top View)

1.3.1 78K0/FY2-L (16 pins)

1.3.2 78K0/FA2-L (20 pins)

1.3.3 78K0/FB2-L (30 pins)

1.4 Block Diagram

1.4.1 78K0/FY2-L (16 pins)

1.4.2 78K0/FA2-L (20 pins)

1.4.3 78K0/FB2-L (30 pins)

1.5 Outline of Functions

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

2.1.1 78K0/FY2-L

2.1.2 78K0/FA2-L