To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
7700 FAMILY / 7751 SERIES
7751
Group
User’s Manual
Preface
This manual describes the hardware of the Mitsubishi
CMOS 16-bit microcomputers 7751 Group. After
reading this manual, the users will be able to
understand the functions, so that they can utilize their
capabilities fully.
For details concerning the software, refer to the 7751
Series Software Manual. For details concerning the
development support tools (assembler, emulation
pods), refer to the respective user’s manuals.
Table of Contents
Table of Contents
CHAPTER 1. DESCRIPTION
1.1 Performance overview.......................................................................................................... 1-3
1.2 Pin configuration................................................................................................................... 1- 4
1.3 Pin description ...................................................................................................................... 1- 5
1.4 Block diagram ........................................................................................................................ 1- 8
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit ....................................................................................................... 2 -2
2.1.1 Accumulator (Acc) ......................................................................................................... 2 -3
2.1.2 Index register X (X) ....................................................................................................... 2-3
2.1.3 Index register Y (Y) ....................................................................................................... 2-3
2.1.4 Stack pointer (S) ............................................................................................................ 2-4
2.1.5 Program counter (PC) ................................................................................................... 2- 5
2.1.6 Program bank register (PG) ......................................................................................... 2- 5
2.1.7 Data bank register (DT) ................................................................................................ 2-6
2.1.8 Direct page register (DPR) ........................................................................................... 2-6
2.1.9 Processor status register (PS) ..................................................................................... 2-8
2.2 Bus interface unit ............................................................................................................... 2-10
2.2.1 Overview ....................................................................................................................... 2-10
2.2.2 Functions of bus interface unit (BIU) ........................................................................2-12
2.2.3 Operation of bus interface unit (BIU)........................................................................ 2-15
2.3 Access space ....................................................................................................................... 2-17
2.3.1 Banks ............................................................................................................................ 2- 18
2.3.2 Direct page ................................................................................................................... 2-18
2.4 Memory assignment ........................................................................................................... 2-19
2.4.1 Memory assignment in internal area .........................................................................2-19
2.5 Processor modes ................................................................................................................ 2-22
2.5.1 Single-chip mode ......................................................................................................... 2-23
2.5.2 Memory expansion and microprocessor modes ....................................................... 2-23
2.5.3 Setting processor modes ............................................................................................ 2-26
[Precautions when operating in single-chip mode] ............................................................ 2-28
CHAPTER 3. INPUT/OUTPUT PINS
3.1 Programmable I/O ports ...................................................................................................... 3- 2
3.1.1 Direction register ............................................................................................................ 3- 3
3.1.2 Port register .................................................................................................................... 3 -4
3.2 I/O pins of internal peripheral devices ............................................................................ 3-8
7751 Group User’s Manual
i
Table of Contents
CHAPTER 4. INTERRUPTS
4.1 Overview .................................................................................................................................. 4-2
4.2 Interrupt sources................................................................................................................... 4- 4
4.3 Interrupt control .................................................................................................................... 4- 6
4.3.1 Interrupt disable flag (I) ................................................................................................ 4 -8
4.3.2 Interrupt request bit ....................................................................................................... 4- 8
4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ....... 4- 8
4.4 Interrupt priority level ........................................................................................................ 4-10
4.5 Interrupt priority level detection circuit ........................................................................ 4-11
4.6 Interrupt priority level detection time ............................................................................ 4-13
4.7
Sequence from acceptance of interrupt request to execution of interrupt routine ...........................
4.7.1 Change in IPL at acceptance of interrupt request ..................................................4-16
4.7.2 Storing registers ........................................................................................................... 4-17
4.8 Return from interrupt routine........................................................................................... 4-18
4.9 Multiple interrupts ............................................................................................................... 4-18
4.10 External interrupts (INTi interrupt) ................................................................................ 4-20
4.10.1 Function of INTi interrupt request bit ...................................................................... 4-23
4.10.2 Switch of occurrence factor of INTi interrupt request ...........................................4-25
4-14
___
___
___
CHAPTER 5. TIMER A
5.1 Overview .................................................................................................................................. 5-2
5.2 Block description .................................................................................................................. 5-3
5.2.1 Counter and reload register (timer Ai register) ......................................................... 5-4
5.2.2 Count start register........................................................................................................ 5 -5
5.2.3 Timer Ai mode register ................................................................................................. 5 -6
5.2.4 Timer Ai interrupt control register ............................................................................... 5- 7
5.2.5 Port P5 and port P6 direction registers ..................................................................... 5-8
5.3 Timer mode ............................................................................................................................ 5 -9
5.3.1 Setting for timer mode ................................................................................................ 5-11
5.3.2 Count source ................................................................................................................ 5-13
5.3.3 Operation in timer mode ............................................................................................. 5-14
5.3.4 Select function ............................................................................................................. 5-15
5.4 Event counter mode ........................................................................................................... 5-19
5.4.1 Setting for event counter mode .................................................................................5-22
5.4.2 Operation in event counter mode .............................................................................. 5-24
5.4.3 Select functions............................................................................................................ 5-26
5.5 One-shot pulse mode ......................................................................................................... 5-30
5.5.1 Setting for one-shot pulse mode ............................................................................... 5-32
5.5.2 Count source ................................................................................................................ 5-34
5.5.3 Trigger ........................................................................................................................... 5-35
5.5.4 Operation in one-shot pulse mode ............................................................................ 5-36
5.6 Pulse width modulation (PWM) mode ............................................................................ 5-39
5.6.1 Setting for PWM mode ............................................................................................... 5-41
5.6.2 Count source ................................................................................................................ 5-43
5.6.3 Trigger ........................................................................................................................... 5-43
5.6.4 Operation in PWM mode ............................................................................................ 5-44
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7751 Group User’s Manual
Table of Contents
CHAPTER 6. TIMER B
6.1 Overview .................................................................................................................................. 6-2
6.2 Block description .................................................................................................................. 6 -2
6.2.1 Counter and reload register (timer Bi register) ......................................................... 6-3
6.2.2 Count start register........................................................................................................ 6 -4
6.2.3 Timer Bi mode register ................................................................................................. 6 -5
6.2.4 Timer Bi interrupt control register ............................................................................... 6- 6
6.2.5 Port P6 direction register ............................................................................................. 6- 7
6.3 Timer mode ............................................................................................................................ 6 -8
6.3.1 Setting for timer mode ................................................................................................ 6-10
6.3.2 Count source ................................................................................................................ 6-11
6.3.3 Operation in timer mode ............................................................................................. 6-12
6.4 Event counter mode ........................................................................................................... 6-14
6.4.1 Setting for event counter mode.................................................................................6-16
6.4.2 Operation in event counter mode .............................................................................. 6-17
6.5 Pulse period/pulse width measurement mode ............................................................. 6-19
6.5.1 Setting for pulse period/pulse width measurement mode ......................................6-21
6.5.2 Count source ................................................................................................................ 6-23
6.5.3 Operation in pulse period/pulse width measurement mode ...................................6-24
CHAPTER 7. SERIAL I/O
7.1 Overview .................................................................................................................................. 7-2
7.2 Block description .................................................................................................................. 7 -3
7.2.1 UARTi transmit/receive mode register ........................................................................ 7- 4
7.2.2 UARTi transmit/receive control register 0 .................................................................. 7 -6
7.2.3 UARTi transmit/receive control register 1 .................................................................. 7 -7
7.2.4 UARTi transmit register and UARTi transmit buffer register ................................... 7-9
7.2.5 UARTi receive register and UARTi receive buffer register ....................................7-11
7.2.6 UARTi baud rate register (BRGi) .............................................................................. 7-13
7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers 7-14
7.2.8 Port P8 direction register ........................................................................................... 7-16
7.3 Clock synchronous serial I/O mode ............................................................................... 7-17
7.3.1 Transfer clock (synchronizing clock) ......................................................................... 7-18
7.3.2 Transfer data format.................................................................................................... 7-19
7.3.3 Method of transmission ............................................................................................... 7-20
7.3.4 Transmit operation ....................................................................................................... 7-24
7.3.5 Method of reception .................................................................................................... 7-26
7.3.6 Receive operation ........................................................................................................ 7-30
7.3.7 Process on detecting overrun error........................................................................... 7-33
7.4 Clock asynchronous serial I/O (UART) mode ............................................................... 7-35
7.4.1 Transfer rate (frequency of transfer clock) ..............................................................7-36
7.4.2 Transfer data format.................................................................................................... 7-38
7.4.3 Method of transmission ............................................................................................... 7-40
7.4.4 Transmit operation ....................................................................................................... 7-44
7.4.5 Method of reception .................................................................................................... 7-46
7.4.6 Receive operation ........................................................................................................ 7-49
7.4.7 Process on detecting error ......................................................................................... 7-51
7.4.8 Sleep mode .................................................................................................................. 7-52
7751 Group User’s Manual
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Table of Contents
CHAPTER 8. A-D CONVERTER
8.1 Overview .................................................................................................................................. 8-2
8.2 Block description .................................................................................................................. 8-3
8.2.1 A-D control register 0 ................................................................................................... 8- 4
8.2.2 A-D control register 1 ................................................................................................... 8- 6
8.2.3 A-D register i (i = 0 to 7) ............................................................................................. 8- 7
8.2.4 A-D conversion interrupt control register .................................................................... 8-8
8.2.5 Port P7 direction register ............................................................................................. 8- 9
8.3 A-D conversion method (successive approximation conversion method) ............ 8-10
8.4 Absolute accuracy and differential non-linearity error ..............................................8-13
8.4.1 Absolute accuracy ....................................................................................................... 8-13
8.4.2 Differential non-linearity error .....................................................................................8-14
8.5 Comparison voltage in 8-bit mode ................................................................................. 8-15
8.6 One-shot mode .................................................................................................................... 8-16
8.6.1 Settings for one-shot mode ........................................................................................ 8-16
8.6.2 One-shot mode operation description .......................................................................8-18
8.7 Repeat mode ........................................................................................................................ 8-20
8.7.1 Settings for repeat mode ............................................................................................ 8-20
8.7.2 Repeat mode operation description .......................................................................... 8-22
8.8 Single sweep mode ............................................................................................................ 8-23
8.8.1 Settings for single sweep mode ................................................................................ 8-23
8.8.2 Single sweep mode operation description ................................................................8-25
8.9 Repeat sweep mode 0 ....................................................................................................... 8-27
8.9.1 Settings for repeat sweep mode 0 ............................................................................ 8-27
8.9.2 Repeat sweep mode 0 operation description ..........................................................8-29
8.10 Repeat sweep mode 1 ..................................................................................................... 8-31
8.10.1 Settings for repeat sweep mode 1 ..........................................................................8-31
8.10.2 Repeat sweep mode 1 operation description ........................................................ 8-34
CHAPTER 9. WATCHDOG TIMER
9.1 Block description .................................................................................................................. 9-2
9.1.1 Watchdog timer .............................................................................................................. 9-3
9.1.2 Watchdog timer frequency select register .................................................................. 9-4
9.2 Operation description .......................................................................................................... 9- 5
9.2.1 Basic operation .............................................................................................................. 9 -5
9.2.2 Operation in Stop mode ............................................................................................... 9- 7
9.2.3 Operation in Hold state................................................................................................. 9 -7
9.3 Precautions when using watchdog timer ........................................................................ 9 -8
CHAPTER 10. STOP MODE
10.1 Clock generating circuit .................................................................................................. 10-2
10.2 Operation description ...................................................................................................... 10-3
10.2.1 Termination by interrupt request occurrence ......................................................... 10-4
10.2.2 Termination by hardware reset ................................................................................ 10-5
10.3 Precautions for Stop mode ............................................................................................ 10-6
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7751 Group User’s Manual
Table of Contents
CHAPTER 11. WAIT MODE
11.1 Clock generating circuit .................................................................................................. 11-2
11.2 Operation description ...................................................................................................... 11-3
11.2.1 Termination by interrupt request occurrence ......................................................... 11-4
11.2.2 Termination by hardware reset ................................................................................ 11-4
11.3 Precautions for Wait mode ............................................................................................. 11-5
CHAPTER 12. CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices ...................................................... 12-2
12.1.1 Descriptions of signals .............................................................................................. 12-2
12.1.2 Operation of bus interface unit (BIU) ..................................................................... 12-8
12.2 Bus cycle .......................................................................................................................... 12-11
12.3 Ready function ................................................................................................................ 12-14
12.3.1 Operation description .............................................................................................. 12-15
12.4 Hold function ................................................................................................................... 12-18
12.4.1 Operation description .............................................................................................. 12-19
CHAPTER 13. RESET
13.1 Hardware reset .................................................................................................................. 13-2
13.1.1 Pin state ..................................................................................................................... 13-3
13.1.2 State of CPU, SFR area, and internal RAM area.................................................13-4
13.1.3 Internal processing sequence after reset ...............................................................13-9
13.1.4 Time supplying “L” level to RESET pin ................................................................13-10
13.2 Software reset .................................................................................................................. 13-12
______
CHAPTER 14. CLOCK GENERATING CIRCUIT
14.1 Oscillation circuit example ............................................................................................. 14-2
14.1.1 Connection example using resonator/oscillator......................................................14-2
14.1.2 Input example of externally generated clock .........................................................14-2
14.2 Clock .................................................................................................................................... 14-3
14.2.1 Clock generated in clock generating circuit ........................................................... 14-4
14.2.2 Operation clock for internal peripheral devices ..................................................... 14-5
7751 Group User’s Manual
v
Table of Contents
CHAPTER 15. ELECTRICAL CHARACTERISTICS
15.1 Absolute maximum ratings ............................................................................................. 15-2
15.2 Recommended operating conditions ............................................................................ 15-3
15.3 Electrical characteristics ................................................................................................. 15-4
15.4 A-D converter characteristics ........................................................................................ 15-5
15.5 Internal peripheral devices ............................................................................................. 15-6
15.6 Ready and Hold ............................................................................................................... 15-13
15.7 Single-chip mode ............................................................................................................ 15-16
15.8 Memory expansion mode and microprocessor mode : When 2-φ access in
low-speed running ......................................................................................................... 15-18
15.9 Memory expansion mode and microprocessor mode : When 3-φ access in
low-speed running ......................................................................................................... 15-23
15.10 Memory expansion mode and microprocessor mode : When 4-φ access in
low-speed running ....................................................................................................... 15-28
15.11 Memory expansion mode and microprocessor mode : When 3-φ access in
high-speed running ...................................................................................................... 15-33
15.12 Memory expansion mode and microprocessor mode : When 4-φ access in
high-speed running ...................................................................................................... 15-38
15.13 Memory expansion mode and microprocessor mode : When 5-φ access in
high-speed running ...................................................................................................... 15-43
15.14 Memory expansion mode and microprocessor mode : When 2-φ access in
high-speed running (Internal RAM access) ............................................................ 15-48
15.15 Testing circuit for ports P0 to P8,
_
φ
1, and E ......................................................... 15-51
CHAPTER 16. STANDARD CHARACTERISTICS
16.1 Standard characteristics ................................................................................................. 16-2
16.1.1 Programmable I/O port (CMOS output) standard characteristics ........................ 16-2
16.1.2 Icc–f(XIN) standard characteristics .......................................................................... 16-3
16.1.3 A-D converter standard characteristics ................................................................... 16-4
CHAPTER 17. APPLICATIONS
17.1 Memory expansion ............................................................................................................ 17-2
17.1.1 Memory expansion model ......................................................................................... 17-2
17.1.2 How to calculate timing ............................................................................................ 17-4
17.1.3 Points in memory expansion .................................................................................... 17-8
17.1.4 Example of memory expansion.............................................................................. 17-26
17.1.5 Example of I/O expansion ...................................................................................... 17-37
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7751 Group User’s Manual
Table of Contents
CHAPTER 18. PROM VERSION
18.1 EPROM mode ..................................................................................................................... 18-3
18.1.1 Pin description ........................................................................................................... 18-3
18.1.2 Programming/reading to/from built-in PROM..........................................................18-4
18.1.3 Programming algorithm of built-in PROM ...............................................................18-7
18.1.4 Electrical characteristics of programming algorithm .............................................. 18-9
18.2 Usage precaution ............................................................................................................ 18-10
18.2.1 Precautions on all PROM versions ....................................................................... 18-10
18.2.2 Precautions on one time PROM version .............................................................. 18-11
18.2.3 Precautions on EPROM version ............................................................................18-11
CHAPTER 19. FLASH MEMORY VERSION
19.1 Parallel input/output mode ............................................................................................. 19-3
19.1.1 Pin description ........................................................................................................... 19-4
19.1.2 Access to built–in flash memory ............................................................................. 19-5
19.1.3 Read–only mode ........................................................................................................ 19-7
19.1.4 Read/write (software command control) mode ......................................................19-9
19.1.5 Electrical characteristics ......................................................................................... 19-18
19.1.6 Program/erase algorithm flow chart ...................................................................... 19-20
19.2 Serial input/output mode ...............................................................................................19-21
19.2.1 Pin description ......................................................................................................... 19-21
19.2.2 Access to built–in flash memory ........................................................................... 19-23
19.2.3 Electrical characteristics ......................................................................................... 19-31
19.2.4 Program algorithm flow chart ................................................................................. 19-33
APPENDIX
Appendix 1. Memory assignment ........................................................................................... 20-2
Appendix 2. Memory assignment in SFR area ................................................................... 20-5
Appendix 3. Control registers ................................................................................................. 20-9
Appendix 4. Package outlines .............................................................................................. 20-32
Appendix 5. Example for processing unused pins .......................................................... 20-34
Appendix 6. Hexadecimal instruction code table ............................................................. 20-37
Appendix 7. Machine instructions ....................................................................................... 20-40
Appendix 8. Examples of noise immunity improvement ................................................ 20-61
Appendix 9. Q & A .................................................................................................................. 20-71
7751 Group User’s Manual
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Table of Contents
MEMORANDUM
viii
7751 Group User’s Manual
CHAPTER 1
DESCRIPTION
1.1 Performance overview
1.2 Pin configuration
1.3 Pin description
1.4 Block diagram
DESCRIPTION
The 16-bit single-chip microcomputers 7751 Group is suitable for office, business, and industrial equipment
controllers that require high-speed processing of large amounts of data.
These microcomputers develop with the M37751M6C-XXXFP as the base chip. This manual describes the
functions about the M37751M6C-XXXFP unless there is a specific difference and refers to the
M37751M6C-XXXFP as “M37751.”
Notes 1: About details concerning each microcomputer’s development status of the 7751 Group, inquire of
“CONTACT ADDRESSES FOR FURTHER INFORMATION” described last.
2: How the 7751 Group’s type name see is described below.
M 3 77 51 M 6 C–XXX FP
Mitsubishi integrated prefix
Represent an original single-chip microcomputer
Series designation using 2 digits
Circuit function identification code using 2 digits
Memory identification code using a digit
M: Mask ROM
E: EPROM
F: Flash memory
S: External ROM
Memory size identification code using a digit
Difference of electrical characteristics identification code
using a digit
Mask ROM number
Package style
FP: Plastic molded QFP
FS: Ceramic QFN
1–2
7751 Group User’s Manual
DESCRIPTION
1.1 Performance overview
1.1 Performance overview
Table 1.1.1 shows the performance overview of the M37751.
Table 1.1.1 M37751 performance overview
Parameters
Number of basic instructions
Instruction execution time
Operating clock frequency f(XIN)
Memory size
Programmable Input/Output
ports
Multifunction timers
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Port Input/Output
characteristics
Memory expansion
Operating temperature range
Device structure
Package
Note: All of the 7751 Group microcomputers are the same except for the package type, memory type,
memory size, and electric characteristics.
ROM
RAM
P0–P2, P4–P8
P3
TA0–TA4
TB0–TB2
UART0, UART1
Input/Output withstand voltage
Output current
109
100 ns (the minimum instruction at f(XIN) = 40 MHz)
40 MHz (maximum at high-speed running)
49152 bytes
2048 bytes
8 bits ✕ 8
4 bits ✕ 1
16 bits ✕ 5
16 bits ✕ 3
(UART or clock synchronous serial I/O) ✕ 2
10-bit successive approximation method
12 bits ✕ 1
3 external, 16 internal (priority levels 0 to 7 can
be set for each interrupt with software)
Built-in (externally connected to a ceramic
resonator or a quartz-crystal oscillator)
5 V ±10 %
125 mW (at f(XIN) = 40 MHz frequency, typ.)
5 V
5 mA
Maximum 16 Mbytes
–20°C to 85°C
CMOS high-performance silicon gate process
80-pin plastic molded QFP
Functions
✕
1 (8 channels)
7751 Group User’s Manual
1–3
DESCRIPTION
1.2 Pin configuration
1.2 Pin configuration
Figure 1.2.1 shows the M37751 pin configuration.
3
2
1
/AN
/AN
/AN
3
2
1
P7
P7
P7
80 79 78 77 76 75 74 73 72 71 696867 66 6570
4
/AN
4
P7
5
/AN
5
P7
6
/AN
6
P7
TRG
/AD
7
/AN
7
P7
SS
V
SS
AV
REF
V
CC
AV
CC
V
0
/RTS
0
0
/CLK
/CTS
1
0
P8
P8
0
D
X
/R
2
P8
0
D
X
/T
3
P8
P70/AN
P67/TB2
P66/TB1
P65/TB0
P64/INT
P63/INT
P62/INT
P61/TA4
P60/TA4
P57/TA3
P56/TA3
P55/TA2
P54/TA2
P53/TA1
P52/TA1
P51/TA0
P50/TA0
P42/φ
P41/RDY
OUT
OUT
OUT
OUT
OUT
P4
P4
P4
P4
P4
1
0
IN
IN
IN
IN
IN
IN
IN
IN
1
2
3
4
2
5
1
6
7
0
8
9
10
11
12
13
14
15
16
17
18
7
19
6
20
5
21
4
22
3
23
24
M37751M6C-XXXFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P84/CTS1/RTS
P85/CLK
P86/RXD
P87/TXD
P00/A
P01/A
P02/A
P03/A
P04/A
P05/A
P06/A
P07/A
P10/A8/D
P11/A9/D
P12/A10/D
P13/A11/D
P14/A12/D
P15/A13/D
P16/A14/D
P17/A15/D
P20/A16/D
P21/A17/D
P22/A18/D
P23/A19/D
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
1
25 2726 28 3429 30 31 32 33 35 36 37 38 39 40
IN
SS
X
OUT
BYTE
/HOLD
0
CNV
X
RESET
P4
Outline : 80P6N-A
Fig. 1.2.1 M37751 pin configuration (top view)
1–4
7751 Group User’s Manual
4
5
6
/R/W
/BHE
0
1
P3
P3
7
/D
23
/A
7
P2
/D
22
/A
6
P2
/D
21
/A
5
P2
/D
20
/A
4
P2
E
ss
V
/ALE
2
/HLDA
3
P3
P3
1.3 Pin description
Tables 1.3.1 to 1.3.3 list the pin description.
Table 1.3.1 Pin description (1)
Pin
Vcc, Vss
CNVss
______
RESET
XIN
XOUT
_
E
BYTE
AVcc
AVss
VREF
Name
Power supply
CNVss
Reset input
Clock input
Clock output
Enable output
External data bus width
selection input
Analog supply input
Reference voltage input
Input/Output
Input
Input
Input
Output
Output
Input
Input
DESCRIPTION
1.3 Pin description
Functions
Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin.
This pin controls the processor mode.
[Single-chip mode] [Memory expansion mode]
Connect to Vss pin.
[Microprocessor mode]
Connect to Vcc pin.
The microcomputer is reset when supplying “L” level
to this pin.
These are I/O pins of the internal clock generating
circuit. Connect a ceramic resonator or quartz-crystal
oscillator between XIN and XOUT pins. When using an
external clock, the clock source should be input to XIN
pin and XOUT pin should be left open.
This pin outputs E signal.
Data/instruction code read or data write is performed
when output from this pin is “L” level.
[Memory expansion mode] [Microprocessor mode]
Input level to this pin determines whether the external
data bus has a 16-bit width or 8-bit width. The width
is 16 bits when the level is “L”, and 8 bits when the
level is “H.”
The power supply pin for the A-D converter. Externally
connect AVcc to Vcc pin.
The power supply pin for the A-D converter. Externally
connect AVss to Vss pin.
This is a reference voltage input pin for the A-D converter.
_
7751 Group User’s Manual
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DESCRIPTION
1.3 Pin description
Table 1.3.2 Pin description (2)
Pin
P00–P07
A0–A7
P10–P17
A8/D8–
A15/D15
P20–P27
A16/D0–
A23/D7
P30–P33
__
R/W,
____
BHE,
ALE,
_____
HLDA
I/O port P0
I/O port P1
I/O port P2
I/O port P3
Name
Input/Output
I/O
Output
I/O
I/O
I/O
Output
Functions
[Single-chip mode]
Port P0 is an 8-bit CMOS I/O port. This port has an
I/O direction register and each pin can be programmed
for input or output.
[Memory expansion mode] [Microprocessor mode]
Low-order 8 bits (A0–A7) of the address are output.
[Single-chip mode]
Port P1 is an 8-bit I/O port with the same function as
P0.
[Memory expansion mode] [Microprocessor mode]
●External bus width = 8 bits (When the BYTE pin is
“H” level)
Middle-order 8 bits (A8–A15) of the address are output.
●External bus width = 16 bits (When the BYTE pin is
“L” level)
Data (D8 to D15) input/output and output of the middleorder 8 bits (A8–A15) of the address are performed
with the time sharing system.
[Single-chip mode]
Port P2 is an 8-bit I/O port with the same function as P0.
[Memory expansion mode] [Microprocessor mode]
Data (D0 to D7) input/output and output of the highorder 8 bits (A16–A23) of the address are performed
with the time sharing system.
[Single-chip mode]
Port P3 is a 4-bit I/O port with the same function as P0.
[Memory expansion mode] [Microprocessor mode]
__ ____ _____
P30–P33 respectively output R/W, BHE, ALE, and HLDA
signals.
__
●R/W
The Read/Write signal indicates the data bus state.
The state is read while this signal is “H” level, and
write while this is “L” level.
____
●BHE
“L” level is output when an odd-numbered address is
accessed.
●ALE
This is used to obtain only the address from address
and data multiplex signals.
_____
●HLDA
This is the signal to externally indicate the state when
the microcomputer is in Hold state.
“L” level is output during Hold state.
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7751 Group User’s Manual
Table 1.3.3 Pin description (3)
Pin
P40–P47
_____
HOLD,
____
I/O port P4
Name
RDY,
P42–P47
_____
HOLD,
____
RDY,
φ
1,
P43–P47
P50–P57
P60–P67
P70–P77
P80–P87
I/O port P5
I/O port P6
I/O port P7
I/O port P8
Input/Output
I/O
Input
Input
I/O
Input
Input
Output
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
1.3 Pin description
Functions
[Single-chip mode]
Port P4 is an 8-bit I/O port with the same function as
P0. P42 can be programmed as the clock
[Memory expansion mode]
_____ ____
P40 functions as the HOLD input pin, P41 as the RDY
input pin. The microcomputer is in Hold state while “L”
_____
level is input to the HOLD pin.
The microcomputer is in Ready state while “L” level is
____
input to the RDY pin.
P42–P47 function as I/O ports with the same functions
as P0.
P42 can be programmed for the clock
[Microprocessor mode]
_____ ____
P40 functions as the HOLD input pin, P41 as the RDY
input pin. P42 always functions as the clock
pin.
P43–P47 function as I/O ports with the same functions
as P0.
Port P5 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
Timers A0–A3.
Port P6 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
Timer A4, input pins for external interrupt and input
pins for Timers B0–B2.
Port P7 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as input pins for
A-D converter.
Port P8 is an 8-bit I/O port with the same function as
P0. These pins can be programmed as I/O pins for
serial I/O.
φ
1 output pin.
φ
1 output pin.
φ
1 output
7751 Group User’s Manual
1–7
DESCRIPTION
Enable output
X
IN
X
OUT
E
Reset input
RESET
Reference
voltage input
V
REF
Clock generating circuit
Data Buffer DB
L
(8)
Instruction Queue Buffer Q
2
(8)
Data Bank Register DT (8)
Progtamu Counter PC (16)
Incrementer/Decrementer (24)
Program Bank Register PG (8)
Input Buffer Register IB (16)
Direct Page Register DPR (16)
Stack Pointer S (16)
Index Register X (16)
Arithmetic Logic
Unit (16)
Accumulator A (16)
Instruction Register (8)
Data Bus (Even)
Input/Output
port P0
Watchdog Timer
CNVss
BYTE
External data bus
width selection input
Timer B1 (16)
Timer B2 (16)
P0 (8)
Timer B0 (16)
Timer A1 (16)
Timer A2 (16)
Timer A3 (16)
Timer A4 (16)
Timer A0 (16)
ROM
48 Kbytes
RAM
2048 bytes
UART1 (9)
UART0 (9)
AV
SS
(0V)
AV
CC
Central Processing Unit (CPU)
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Address Bus
Bus
Interface
Unit
(BIU)
(0V)
V
SS
V
CC
Processor Status Register PS (11)
A-D Converter (10)
Clock input Clock output
Accumulator B (16)
Index Register Y (16)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
0
(8)
Data Buffer DB
H
(8)
Data Bus (Odd)
P1 (8)
Input/Output
port P1
P2 (8)
Input/Output
port P2
P3 (4)
Input/Output
port P3
P4 (8)
Input/Output
port P4
P5 (8)
Input/Output
port P5
P6 (8)
Input/Output
port P6
P7 (8)
Input/Output
port P7
P8 (8)
Input/Output
port P8
1.4 Block diagram
1.4 Block diagram
Figure 1.4.1 shows the M37751 block diagram.
Fig. 1.4.1 M37751 block diagram
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7751 Group User’s Manual
CHAPTER 2
CENTRAL
PROCESSING UNIT
(CPU)
2.1 Central processing unit
2.2 Bus interface unit
2.3 Access space
2.4 Memory assignment
2.5 Processor modes
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1 Central processing unit
The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1.
b0b7
DT
b23 b16
b7 b0
b7b8b15
AH AL
b7b8b15
BH BL
b7b8b15
XH XL
b7b8b15
YH YL
b15
b7b8
SH SL
b15 b7
b8
PCH PCLPG
b15
b7b8
b0
Accumulator A (A)
b0
Accumulator B (B)
b0
Index register X (X)
b0
Index register Y (Y)
b0
Stack pointer (S)
Data bank register (DT)
b0
Program counter (PC)
Program bank register (PG)
b0
DPRLDPRH
Direct page register (DPR)
b9b15
00000 CZIDxmVNIPL
Fig. 2.1.1 CPU registers structure
2–2
b7b8b15
PSLPSH
Negative flag
Processor interrupt priority level
7751 Group User’s Manual
b0
Processor status register (PS)
b0b1b2b3b4b5b6b7b8b10
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.1 Accumulator (Acc)
Accumulators A and B are available.
(1) Accumulator A (A)
Accumulator A is the main register of the microcomputer. The transaction of data such as calculation,
data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits,
and the low-order 8 bits can also be used separately. The data length flag (m) determines whether
the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status
register which is described later. When an 8-bit register is selected, only the low-order 8 bits of
accumulator A are used and the contents of the high-order 8 bits is unchanged.
(2) Accumulator B (B)
Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be
used instead of accumulator A. The use of accumulator B, however except for some instructions,
requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B is
also controlled by the data length flag (m) just as in accumulator A.
2.1.2 Index register X (X)
Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register
length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x
is a part of the processor status register which is described later. When an 8-bit register is selected, only
the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged.
In an addressing mode in which index register X is used as an index register, the address obtained by
adding the contents of this register to the operand’s contents is accessed.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register X indicate the
low-order 16 bits of the source address. The third byte of the instruction is the high-order 8 bits of the
source address.
In the RMPA instruction, a Repeat MultiPly and Accumulate instruction, the contents of index register X
indicate the low-order 16 bits of address in which multiplicands are stored.
Note: Refer to “7751 Series Software Manual” for addressing modes.
2.1.3 Index register Y (Y)
Index register Y is a 16-bit register with the same function as index register X. Just as in index register
X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an
8-bit register.
In the MVP or MVN instruction, a block transfer instruction, the contents of index register Y indicate the
low-order 16 bits of the destination address. The second byte of the instruction is the high-order 8 bits of
the destination address.
In the RMPA instruction, a Repeat MultiPly and Accumulate instruction, the contents of index register Y
indicate the low-order 16 bits of address in which multipliers are stored.
7751 Group User’s Manual
2–3
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.4 Stack pointer (S)
The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when
addressing modes using the stack are executed. The contents of S indicate an address (stack area) for
storing registers during subroutine calls and interrupts. Bank 016 is specified for the stack area. (Refer to
“2.1.6 Program bank register (PG).”)
When an interrupt request is accepted, the microcomputer stores the contents of the program bank register
(PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the
contents of the program counter (PC) and the processor status register (PS) are stored. The contents of
S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting
of the interrupt request. (Refer to Figure 2.1.2.)
When completing the process in the interrupt routine and returning to the original routine, the contents of
registers stored in the stack area are restored into the original registers in the reverse sequence (PS→PC→PG)
by executing the RTI instruction. The contents of S is returned to the state before accepting an interrupt
request.
The same operation is performed during a subroutine call, however, the contents of PS is not automatically
stored. (The contents of PG may not be stored. This depends on the addressing mode.)
The user should store registers other than those described above with software when the user needs them
during interrupts or subroutine calls.
Additionally, initialize S at the beginning of the program because its contents are undefined at reset. The
stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore,
make sure of the subroutine’s nesting depth not to destroy the necessary data.
Note: Refer to “7751 Series Software Manual” for addressing modes.
Stack area
Address
S–5
S–4
S–3
S–2
S–1
Processor status register’s low-order byte (PSL)
Processor status register’s high-order byte (PS
Program counter’s low-order byte (PC
Program counter’s high-order byte (PC
S
● “S” is the initial address that the stack pointer (S)
indicates at accepting an interrupt request.
The S’s contents become “S–5” after storing the
above registers.
Program bank register (PG)
L
)
H
)
H
)
Fig. 2.1.2 Stored registers of the stack area
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.5 Program counter (PC)
The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at
which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the
low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes
the contents of the reset’s vector address (addresses FFFE16, FFFF16) immediately after reset.
Figure 2.1.3 shows the program counter and the program bank register.
(b16)(b23)
b7 b0 b15 b8 b7 b0
PG
Fig. 2.1.3 Program counter and program bank register
2.1.6 Program bank register (PG)
The program bank register is an 8-bit register. This register indicates the high-order 8 bits (bank) of the
address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out
from an instruction queue buffer next) is stored. These 8 bits are called bank.
When a carry occurs after adding the contents of the program counter or adding the offset value to the
contents of the program counter in the branch instruction and others, the contents of the program bank
register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the
program counter, the contents of the program bank register is automatically decremented by 1. Accordingly,
there is no need to consider bank boundaries in programming, usually.
In the single-chip mode, make sure to prevent the program bank register from being set to the value other
than “0016” by executing the branch instructions and others. It is because the access space of the singlechip mode is the internal area within the bank 016.
This register is cleared to “0016” at reset.
PCH PCL
7751 Group User’s Manual
2–5
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.7 Data bank register (DT)
The data bank register is an 8-bit register. In the following addressing modes using the data bank register,
the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed.
Use the LDT instruction to set a value to this register.
In the single-chip mode, make sure to fix this register to “0016”. It is because the access space of the
single-chip mode is the internal area within the bank 016.
This register is cleared to “0016” at reset.
●Addressing modes using data bank register
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Absolute
•Absolute bit
•Absolute indexed X
•Absolute indexed Y
•Absolute bit relative
•Stack pointer relative indirect indexed Y
•Multiplied accumulation
2.1.8 Direct page register (DPR)
The direct page register is a 16-bit register. The contents of this register indicate the direct page area
which is allocated in bank 016 or in the space across banks 016 and 116. The following addressing modes
use the direct page register.
The contents of the direct page register indicate the base address (the lowest address) of the direct page
area. The space which extends to 256 bytes above that address is specified as a direct page.
The direct page register can contain a value from “000016” to “FFFF16.” When it contains a value equal to
or more than “FF0116,” the direct page area spans the space across banks 016 and 116.
When the contents of low-order 8 bits of the direct page register is “0016,” the number of cycles required
to generate an address is 1 cycle smaller than the number when its contents are not “0016.” Accordingly,
the access efficiency can be enhanced in this case.
This register is cleared to “000016” at reset.
Figure 2.1.4 shows a setting example of the direct page area.
●Addressing modes using direct page register
•Direct
•Direct bit
•Direct indexed X
•Direct indexed Y
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Direct indirect long
•Direct indirect long indexed Y
•Direct bit relative
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7751 Group User’s Manual
Bank 0
Bank 1
16
FFFF
10000
16
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
0
0
16
16
16
16
FF
16
123
16
222
16
FF10
1000F
16
Direct page area when DPR = “000016”
Direct page area when DPR = “012316”
Direct page area when DPR = “FF1016”
16
(Note 1)
(Note 2)
Notes 1 : The number of cycles required to generate an address is 1 cycle smaller when the
low-order 8 bits of the DPR are “0016.”
2: The direct page area spans the space across banks 016 and 116 when the DPR is
“FF0116” or more.
Fig. 2.1.4 Setting example of direct page area
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2.1.9 Processor status register (PS)
The processor status register is an 11-bit register.
Figure 2.1.5 shows the structure of the processor status register.
b15 b8 b7 b0b1b2b3b4b5b6b14 b9b10b11b12b13
0
Note: Fix bits 11–15 to “0.”
Fig. 2.1.5 Processor status register structure
(1) Bit 0: Carry flag (C)
It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic
operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction
is executed, this flag’s contents determine whether the program causes a branch or not.
Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear
it to “0.”
(2) Bit 1: Zero flag (Z)
It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when
otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the
program causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode addition (the ADC instruction).
N
Processor status
C
ZIDxmV0 IPL000
register (PS)
(3) Bit 2: Interrupt disable flag (I)
It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and
zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted,
this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set
this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset.
(4) Bit 3: Decimal mode flag (D)
It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic
is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with each word
treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically
performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP
instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared
to “0” at reset.
(5) Bit 4: Index register length flag (x)
It determines whether each of index register X and index register Y is used as a 16-bit register or
an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit
register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction
to clear it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7751 Series Software Manual” for details.
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
(6) Bit 5: Data length flag (m)
It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16bit unit when this flag is “0,” and as an 8-bit unit when it is “1.”
Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear
it to “0.” This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, the data is transferred
with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS
instructions. Refer to “7751 Series Software Manual” for details.
(7) Bit 6: Overflow flag (V)
It is used when adding or subtracting with a word regarded as signed binary. When the data length
flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the
range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag
(m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range
between –128 and +127, and cleared to “0” in all other cases.
The overflow flag is also set to “1” when a result of division exceeds the register length to be stored
in the DIV or DIVS instruction, a division instruction with unsigned or signed; and when a result of
addition exceeds the range between –2147483648 and +2147483647 in the RMPA instruction, a
Repeat MultiPly and Accumulate instruction.
When the BVC or BVS instruction is executed, this flag’s contents determine whether the program
causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(8) Bit 7: Negative flag (N)
It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result
is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m)
is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag
determines whether the program causes a branch or not. Use the SEP instruction to set this flag to
“1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The
interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each
interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in
the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request.
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
new IPL into the stack area and updating the processor status register with the PUL or PLP instruction.
The contents of IPL is cleared to “0002” at reset.
7751 Group User’s Manual
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CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2 Bus interface unit
A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices.
BIU’s function and operation are described below.
When externally connecting devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
2.2.1 Overview
Transfer operation between the CPU and memory•I/O devices is always performed via the BIU.
Figure 2.2.1 shows the bus and bus interface unit (BIU).
➀ The BIU reads an instruction from the memory before the CPU executes it.
➁ When the CPU reads data from the memory•I/O device, the CPU first specifies the address from which
data is read to the BIU. The BIU reads data from the specified address and passes it to the CPU.
➂ When the CPU writes data to the memory•I/O device, the CPU first specifies the address to which data
is written to the BIU and write data. The BIU writes the data to the specified address.
➃ To perform the above operations ➀ to ➂, the BIU inputs and outputs the control signals, and control the
bus.
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7751 Group User’s Manual
Internal
memory
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
device
External
7
15
/D
/D
23
15
A
to
0
to A
8
/D
/D
16
8
A
A
Bus
conversion
Control signals
circuit
device
Internal
peripheral
(SFR)
7
A
to
0
External bus
A
Internal bus
15
7
D
to
8
Internal bus D
23
D
A
to
to
0
0
Internal bus A
Internal bus D
unit
Bus
interface
CPU bus
Internal control signal
(BIU)
of the external bus.
unit
Central
M37751
processing
(CPU)
Fig. 2.2.1 Bus and bus interface unit (BIU)
7751 Group User’s Manual
Notes 1: The CPU bus, internal bus, and external bus are independent of one another.
SFR : Special Function Register
2: Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about control signals
2–11
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.2 Functions of bus interface unit (BIU)
The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions
of each register.
b23
b0
PA
b7
b0
Q0
Q1
Q2
b23
b0
DA
b15
b0
DBH DBL
Fig. 2.2.2 Register structure of bus interface unit (BIU)
Table 2.2.1 Functions of each register
Name
Program address register
Indicates the storage address for the instruction which is next taken into the
instruction queue buffer.
Instruction queue buffer
Data address register
Data buffer
Temporarily stores the instruction which has been taken in.
Indicates the address for the data which is next read from or written to.
Temporarily stores the data which is read from the memory•I/O device by the
BIU or which is written to the memory•I/O device by the CPU.
Program address register
Instruction queue buffer
Data address register
Data buffer
Functions
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7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
The CPU and the bus send or receive data via BIU because each operates based on different clocks
(Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory • I/O
devices that require a long access time.
The BIU’s functions are described bellow.
Note: The CPU operates based on
φ
CPU. The period of φCPU is normally the same as that of
_
_
φ
bus operates based on the E signal. The period of the E signal is twice that of φ at a minimum.
(1) Reading out instruction (Instruction prefetch)
When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU
reads instructions from the memory and stores them in the instruction queue buffer. This is called
instruction prefetch.
The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU
can operate at high speed without waiting for access to the memory which requires a long access
time.
When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU
performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes.
The contents of the instruction queue buffer is initialized when a branch or jump instruction is
executed, and the BIU reads a new instruction from the destination address.
When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU
extends the pulse duration of clock
φ
CPU in order to keep the CPU waiting until the BIU fetches the
required number of instructions or more.
(2) Reading data from memory•I/O device
The CPU specifies the storage address of data to be read to the BIU’s data address register, and
requires data. The CPU waits until data is ready in the BIU.
The BIU outputs the address received from the CPU onto the address bus, reads contents at the
specified address, and takes it into the data buffer.
The CPU continues processing, using data in the data buffer.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the
BIU keeps the CPU waiting.
. The internal
(3) Writing data to memory•I/O device
The CPU specifies the address of data to be written to the BIU’s data address register. Then, the
CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the
address bus and writes data in the data buffer into the specified address.
The CPU advances to the next processing without waiting for completion of BIU’s write operation.
However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the
BIU keeps the CPU waiting.
7751 Group User’s Manual
2–13
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(4) Bus control
To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and
controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses
the memory•I/O device is called the bus cycle. Table 2.2.2 shows the bus cycle at accessing the
internal area.
Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about the bus cycle at accessing
the external devices.
Table 2.2.2 Bus cycle at accessing internal area
RAM
ROM
SFR
In low-speed running (f(XIN) ≤ 25 MHz)
1 bus cycle = 2
E
Internal address bus
Internal data bus
Address
Data
In high-speed running (f(XIN) ≤ 40 MHz)
1 bus cycle = 2
E
Internal address bus
Internal data bus
E
Internal address bus
Internal data bus
Address
1 bus cycle = 3
Address
Data
Data
2–14
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
2.2.3 Operation of bus interface unit (BIU)
Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU).
About signals which are input/output externally when accessing external devices, refer to “Chapter 12.
CONNECTION WITH EXTERNAL DEVICES.”
(1) When fetching instructions into the instruction queue buffer
➀ When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes
at a time with the timing of waveform (a).
However, when accessing an external device which is connected with the 8-bit external data bus
width (BYTE = “H”), only 1 byte is fetched.
➁ When the instruction which is next fetched is located at an odd address, the BIU fetches only 1
byte with the timing of waveform (a). The contents at the even address are not taken.
(2) When reading or writing data to and from the memory•I/O device
➀ When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16
bits of data are accessed at a time.
➁ When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16
bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched
into the data buffer.
➂ When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd
address is not fetched into the data buffer.
➃ When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even
address is not fetched into the data buffer.
For instructions that are affected by the data length flag (m) and the index register length flag (x),
operation ➀ or ➁ is applied when flag m or x = “0”; operation ➂ or ➃ is applied when flag m or x
= “1.”
7751 Group User’s Manual
2–15
CENTRAL PROCESSING UNIT (CPU)
2.2 Bus interface unit
(a)
E
Internal address bus (A
Internal data bus (D
Internal data bus (D
(b)
Internal address bus (A
Internal data bus (D
Internal data bus (D
0
8
0
8
to
0
to
to
to
0
to
to
A23)
D7)
D15)
A23)
D7)
D15)
Address
Data (Even address)
Data (Odd address)
E
Address (Odd address) Address (Even address)
Invalid data
Data (Odd address)
Data (Even address)
Invalid data
Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU)
2–16
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3 Access space
Figure 2.3.1 shows the M37751’s access space.
By combination of the program counter (PC), which is 16 bits of structure, and the program bank register
(PG), a 16-Mbyte space from addresses 0
external area, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
The memory and I/O devices are allocated in the same access space. Accordingly, it is possible to perform
transfer and arithmetic operations using the same instructions without discrimination of the memory from
I/O devices.
00000016
SFR area
00007F16
00008016
Internal RAM area
00087F16
16 to FFFFFF16 can be accessed. For details about access of an
16
Bank 0
00400016
Internal ROM area
00FFFF16
01000016
020000
FE000016
FF000016
FFFFFF16
Note : Memory assignment of internal area varies according to the type of microcomputer. This
SFR : Special Function Register
16
figure shows the case of the M37751M6C-XXXFP.
Refer to “Appendix 1. Memory assignment” for other products.
Fig. 2.3.1 M37751’s access space
…………
Bank 116
……
Bank FE16
Bank FF16
: Indicates the memory assignment of
the internal areas.
: Indicates that nothing is assigned.
7751 Group User’s Manual
2–17
CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
2.3.1 Banks
The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of
address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank
register (DT). Each bank can be accessed efficiently by using an addressing mode that uses the data bank
register (DT).
If the program counter (PC) overflows at a bank boundary, the contents of the program bank register (PG)
is incremented by 1. If a borrow occurs in the program counter (PC) as a result of subtraction, the contents
of the program bank register (PG) is decremented by 1. Normally, accordingly, the user can program
without concern for bank boundaries.
SFR (Special Function Register), internal RAM, and internal ROM are assigned in bank 016. For details,
refer to section “2.4 Memory assignment.”
2.3.2 Direct page
A 256-byte space specified by the direct page register (DPR) is called “direct page.” A direct page is
specified by setting the base address (the lowest address) of the area to be specified as a direct page into
the direct page register (DPR).
By using a direct page addressing mode, a direct page can be accessed with less instruction cycles than
otherwise.
Note: Refer also to section “2.1 Central processing unit.”
2–18
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
2.4 Memory assignment
This section describes the internal area’s memory assignment. For more information about the external
area, refer also to section “2.5 Processor modes.”
2.4.1 Memory assignment in internal area
SFR (Special Function Register), internal RAM, and internal ROM are assigned in the internal area. Figure
2.4.1 shows the internal area’s memory assignment.
(1) SFR area
The registers for setting internal peripheral devices are assigned at addresses 016 to 7F16. This area
is called SFR (Special Function Register). Figure 2.4.2 shows the SFR area’s memory assignment.
For each register in the SFR area, refer to each functional description in this manual.
For the state of the SFR area immediately after a reset, refer to section “13.1.2 State of CPU, SFR
area, and internal RAM area.”
(2) Internal RAM area
The M37751M6C-XXXFP (See Note) assigns the 2048-byte static RAM at addresses 8016 to 87F16.
The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, note
that set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary
data.
(3) Internal ROM area
The M37751M6C-XXXFP (See Note) assigns the 48-Kbyte mask RAM at addresses 400016 to FFFF16.
Its addresses FFD616 to FFFF16 are the vector addresses, which are called the interrupt vector table,
for reset and interrupts. In the microprocessor mode where use of the internal ROM area is inhibited,
assign a ROM at addresses FFD616 to FFFF16.
Note : Refer to “Appendix 1. Memory assignment” for other products.
7751 Group User’s Manual
2–19
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
000000
00007F
000080
00087F
004000
00FFD6
00FFFF
16
16
16
SFR area
Internal RAM area
16
16
Internal ROM area
16
16
M37751M6C-XXXFP
Refer to Figure 2.4.2.
FFD6
FFD8
FFDA
FFDC
FFDE
FFE0
FFE2
FFE4
FFE6
FFE8
FFEA
FFEC
FFEE
FFF0
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
Interrupt vector table
16
A-D conversion
16
UART1 transmit
16
UART1 receive
16
UART0 transmit
16
UART0 receive
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
Watchdog timer
DBC (Note 1)
BRK instruction
zero divide
RESET
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
2
H
L
1
H
L
0
H
L
H
L
H
L
H
L
H
L
H
: The internal memory is not assigned.
Notes 1: DBC is an interrupt only for debugging; do not use this interrupt.
2: Access to the internal ROM area is disabled in the microprocessor mode.
(Refer to section “2.5 Processor modes.”)
3: Memory assignment of internal area varies according to the type of microcomputer.
Refer to “Appendix 1. Memory assignment” for other products.
Fig. 2.4.1 Internal area’s memory assignment
2–20
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Address
016
116
Port P0 register
216
Port P1 register
316
Port P0 direction register
416
Port P1 direction register
516
Port P2 register
616
Port P3 register
716
Port P2 direction register
816
Port P3 direction register
916
Port P4 register
A16
Port P5 register
B16
Port P4 direction register
C16
Port P5 direction register
D16
Port P6 register
E16
Port P7 register
F16
Port P6 direction register
1016
Port P7 direction register
1116
Port P8 register
1216
1316
Port P8 direction register
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
A-D control register 0
1E16
A-D control register 1
1F16
2016
A-D register 0
2116
2216
A-D register 1
2316
2416
A-D register 2
2516
2616
A-D register 3
2716
2816
A-D register 4
2916
2A16
A-D register 5
2B16
2C16
A-D register 6
2D16
2E16
A-D register 7
2F16
UART0 transmit/receive mode register
3016
UART0 baud rate register (BRG0)
3116
3216
UART0 transmit buffer register
3316
UART0 transmit/receive control register 0
3416
UART0 transmit/receive control register 1
3516
3616
UART0 receive buffer register
3716
UART1 transmit/receive mode register
3816
UART1 baud rate register (BRG1)
3916
3A16
UART1 transmit buffer register
3B16
UART1 transmit/receive control register 0
3C16
UART1 transmit/receive control register 1
3D16
3E16
UART1 receive buffer register
3F16
Address
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
4A16
4B16
4C16
4D16
4E16
4F16
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
Count start register
One-shot start register
Up-down register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency select register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
Fig. 2.4.2 SFR area’s memory map
7751 Group User’s Manual
2–21
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5 Processor modes
The M37751 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor
mode. Some pins’ functions, memory assignment, and access space vary according to the processor modes.
This section describes the differences between the processor modes. Figure 2.5.1 shows a memory assignment
in each processor mode.
00000016
00008016
00087F
00400016
00FFFF16
Single-chip mode
SFR area
Internal
RAM area
16
Not used
Internal
ROM area
Memory expansion mode
SFR area
Internal
RAM area
00088016
003FFF16
Internal
ROM area
01000016
Microprocessor mode
SFR area
Internal
RAM area
Memory expansion mode
Microprocessor mode
00000216
(Note 1)
00000916
FFFFFF16
: External area; Accessing this area make it possible to access external connected devices.
Notes 1: Addresses 2
2: Refer to “Appendix 1. Memory assignment” for products other than M37751M6C–XXXFP.
16 to 916 become a external area in the memory expansion mode and microprocessor mode.
Fig. 2.5.1 Memory assignment in each processor mode for M37751M6C-XXXFP
2–22
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5.1 Single-chip mode
Use this mode when not using external devices. In this mode, ports P0 to P8 function as programmable
I/O ports (when using an internal peripheral device, they function as its I/O pins).
In the single-chip mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.
2.5.2 Memory expansion and microprocessor modes
Use these modes when connecting devices externally. In these modes, an external device can be connected
to any required location in the 16-Mbyte access space. For access to external devices, refer to “Chapter
12. CONNECTION WITH EXTERNAL DEVICES.”
The memory expansion and microprocessor modes have the same functions except for the following:
•In the microprocessor mode, access to the internal ROM area is disabled by force, and the internal ROM
area is handled as an external area.
•In the microprocessor mode, port P42 always functions as the clock
In the memory expansion and microprocessor modes, P0 to P3, P40, and P41 function as the I/O pins for
the signals required for accessing external devices. Consequently, these pins cannot be used as programmable
I/O ports.
If an external device is connected with an area with which the internal area overlaps, when this overlapping
area is read, data in the internal area is taken in the CPU, but data in the external area is not taken in.
If data is written to an overlapping area, the data is written to the internal area, and a signal is output
externally at the same timing as writing to the internal area.
φ
1 output pin.
Figure 2.5.2 shows a pin configuration in each processor mode. Table 2.5.1 lists the functions of P0 to P4
in each processor mode.
For the function of each pin, refer to section “1.3 Pin description,” “Chapter 3. INPUT/OUTPUT PINS,”
and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
7751 Group User’s Manual
2–23
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
●Single-chip mode
1
/RTS
1
1
1
1
D
D
X
X
/CTS
/CLK
/R
4
P8
/T
5
6
7
P00P01P02P03P04P05P06P07P10P11P1
P8
P8
P8
2
P13P14P15P16P17P20P2
1 P22P23
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
V
V
REF
TRG
65
0
66
0
67
0
68
0
69
CC
70
CC
71
72
SS
73
SS
74
75
6
76
5
77
4
3
78
2
79
1
80
M37751M6C–XXXFP
1432
0
/AN
0
P7
IN
/TB2
7
P6
5
6 7 8 91011121314151617181920 21
2
1
IN
/TB0
5
P6
/INT
4
P6
/INT
3
P6
0
/INT
2
P6
IN
/TA4
1
P6
OUT
/TA4
0
P6
IN
/TB1
6
P6
P83/TXD
P82/RXD
P81/CLK
P80/CTS0/RTS
AV
V
AV
P77/AN7/AD
P76/AN
P75/AN
P74/AN
P73/AN
P72/AN
P71/AN
●Memory expansion/Microprocessor mode
1
/RTS
1
1
1
1
D
D
X
X
/CTS
/CLK
/R
/T
4
5
6
7
P8
P8
P8
P8
A0A1A2A3A4A5A6A7A
IN
/TA3
7
P5
OUT
/TA3
6
P5
IN
/TA2
5
P5
OUT
/TA2
4
P5
8
/D
8
IN
/TA1
3
P5
9
/D
9
A
OUT
/TA1
2
P5
10
/D
10
A
IN
/TA0
1
P5
11
/D
11
A
OUT
/TA0
0
P5
12
/D
12
A
13
/D
13
A
43 42 41
22 23 24
3
P47P46P45P44P4
14
15
0
1
/D
/D
/D
/D
14
15
16
17
A
A
A
A
1
/φ
2
P4
2
/D
18
A
40
P2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
4
P2
5
P2
6
P2
7
P3
0
P3
1
P3
2
P3
3
V
ss
E
X
OUT
X
IN
RESET
SS
CNV
BYTE
P4
0
✽
1
✽1 Connect this pin to Vss pin in the single-chip
mode.
1
: These pins have different functions between the
P4
3
/D
19
A
single-chip and the memory expansion/microprocessor modes.
P83/TXD
P82/RXD
P81/CLK
P80/CTS0/RTS
V
AV
V
AV
V
P77/AN7/AD
P76/AN
P75/AN
P74/AN
P73/AN
P72/AN
P71/AN
REF
TRG
64 63 62 61 605958 57 56 55 54 53 52 51 50 49 48 47 46 45 44
65
0
66
0
67
0
68
0
69
CC
70
CC
71
72
SS
73
SS
74
75
6
76
5
77
4
78
3
2
79
1
80
M37751M6C–XXXFP
1432
0
/AN
0
P7
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
2
1
IN
/TB0
5
P6
/INT
4
P6
/INT
3
P6
0
/INT
2
P6
IN
/TA4
1
P6
OUT
/TA4
0
P6
IN
/TA3
7
P5
OUT
/TA3
6
P5
IN
/TA2
5
P5
OUT
/TA2
4
P5
IN
/TB2
7
P6
IN
/TB1
6
P6
IN
/TA1
3
P5
OUT
/TA1
2
P5
IN
/TA0
1
P5
OUT
/TA0
0
P5
43 42 41
22 23 24
7P46P45P44P43
P4
1
/φ
2
✽2 P4
RDY
Fig. 2.5.2 Pin configuration in each processor mode (top view)
2–24
7751 Group User’s Manual
40
A20/D
A21/D
A22/D
A23/D
R/W
BHE
ALE
HLDA
V
ss
E
X
OUT
X
IN
RESET
CNV
SS
BYTE
HOLD
4
5
6
7
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
✽2 This pin functions as φ1 in the microprocessor
mode.
: These pins have different functions between the
single-chip and the memory expansion/microprocessor modes.
CENTRAL PROCESSING UNIT (CPU)
Table 2.5.1 Functions of ports P0 to P4 in each processor mode
P0
Pins
Processor
modes
Single-chip mode
P
P: Functions as a programmable
I/O port.
Memory expansion/Microprocessor mode
2.5 Processor modes
A0 – A
7
P1
P2
P3
P
P: Functions as a programmable
I/O port.
P
P: Functions as a programmable
I/O port.
P
P: Functions as a programmable
I/O port.
• When external data bus width is 16 bits (BYTE = “L”)
A8 – A
D(odd)
15
D (odd): Data at odd address
• When external data bus width is 8 bits (BYTE = “H”)
A8 – A
15
• When external data bus width is 16 bits (BYTE = “L”)
A16 – A
D(even)
23
D (even): Data at even address
• When external data bus width is 8 bits (BYTE = “H”)
D
D : Data
BHE
R/W
P3
P3
P3
P3
A16 – A
23
3
2
1
0
HLDA
ALE
P4
P: Functions as a programmable
I/O port.
Notes 1: P42 also functions as the clock
2: P42 functions as a programmable I/O port in the memory expansion mode, and that functions as the clock
selection. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”)
3: This table lists a switch of pins’ functions by switching the processor mode. Refer to the following section about the input/output
timing of each signal:
•“Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
•“Chapter 15. ELECTRICAL CHARACTERISTICS.”
1
output pin. (Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”)
P
(Note 1)
P43 – P4
7
P: Functions as a programmable I/O port.
P4
2
P4
1
P4
0
P
1
RDY
HOLD
1
output pin by software
(Note 2)
7751 Group User’s Manual
2–25
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5.3 Setting processor modes
The voltage supplied to the CNVss pin and the processor mode bits (bits 1 and 0 at address 5E16) set the
processor mode.
●When Vss level is supplied to CNVss pin
After a reset, the microcomputer starts operating in the single-chip mode. The processor mode is switched
by the processor mode bits after the microcomputer starts operating. When the processor mode bits are
set to “012,” the microcomputer enters the memory expansion mode; when these bits are set to “102,”
the microcomputer enters the microprocessor mode.
The processor mode is switched at the rising edge of signal E after writing to the processor mode bits.
Figure 2.5.3 shows the timing when pin functions are switched by switching the processor mode from the
single-chip mode to the memory expansion or microprocessor mode with the processor mode bits.
When the processor mode is switched during the program execution, the contents of the instruction
queue buffer is not initialized. (Refer to “Appendix 9. Q & A.”)
●When Vcc level is supplied to CNVss pin
After a reset, the microcomputer starts operating in the microprocessor mode. In this case, the microcomputer
cannot operate in the other modes. (Fix the processor mode bits to “102.”)
_
Table 2.5.2 lists the methods for setting processor modes. Figure 2.5.4 shows the structure of processor
mode register 0 (address 5E16).
Written to processor mode bits
E
P0
0
Note: Functions of pins P01 to P07, P1 to P3, P40 to P42 are switched at the same timing shown above.
Function of pin P4
microprocessor mode.
Programmable I/O port P0
2
is, however, switched only when the processor mode is switched to the
0
External address bus A
0
Fig. 2.5.3 Timing when pin functions are switched
2–26
7751 Group User’s Manual
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Table 2.5.2 Methods for setting processor modes
Processor mode CNVss pin level Processor mode bits
b1 b0
Single-chip mode Vss (0 V) (Note 1)
Memory expansion mode Vss (0 V) (Note 1)
Microprocessor mode Vss (0 V) (Note 1)
0
0
10
Vcc (5 V) (Note 2)
Notes 1: The microcomputer starts operating in the single-chip mode after a reset. The microcomputer can
be switched to the other processor modes by setting the processor mode bits.
2: The microcomputer starts operating in the microprocessor mode after a reset. The microcomputer
cannot operate in the other modes, so that fix the processor mode bits as follows:
•b1 = “1” and b0 = “0.”
b1 b0b2b3b4b5b6b7
0
0
Processor mode register 0 (Address 5E16)
0
1
Bit Bit name Functions
Processor mode bits
0
1
Fix this bit to “0.”
2
Software reset bit
3
Interrupt priority detection time
4
select bits
5
Fix this bit to “0.”
6
1 output select bit
Clock φ
7
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1”
after a reset. (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
(Note 2)
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
b5 b4
0 0 : 7 cycles of φ
0 1 : 4 cycles of φ
1 0 : 2 cycles of φ
1 1 : Not selected
1
0 : Clock φ
(P4
I/O port.)
1 : Clock φ
(P4
put pin.)
output disabled
2 functions as a programmable
1
output enabled
2 functions as a clock φ
1
out-
: Bits 7 to 2 are not used for setting of the processor mode.
At reset
0
0
(Note 1)
0
0
0
0
0
0
RW
RW
RW
RW
WO
RW
RW
RW
RW
Fig. 2.5.4 Structure of processor mode register 0
7751 Group User’s Manual
2–27
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
[Precautions when operating in single-chip mode]
The bus cycle select bits (bits 4 and 5 at address 5F16) is not used in the single-chip mode. However, do
not make those bits state of not selected in all cases. Especially in low-speed running, rewrite both bits
at the same time to “012,” “102” or “112.” These bits are cleared to “002” at reset.
b7 b6 b5 b4 b3 b2 b1 b0
0000
Processor mode register 1 (Address 5F16)
Bit
1, 0
Fix these bits to “0.”
Clock source for peripheral
2
devices select bit (Note)
CPU running speed select bit
3
(Note)
Bus cycle select bits
4
5
Fix these bits to “0.”
7, 6
Note: Fix this bit to “0” when f(X
Bit name
Fig. 2.5.5 Structure of processor mode register 1
IN
) > 25 MHz.
Functions
0 :
divided by 2
1 :
0 : High-speed running
1 : Low-speed running
In high-speed running
b5 b4
5 access in high-speed running
0 0 :
0 1 :
4 access in high-speed running
1 0 :
3 access in high-speed running
1 1 : Not selected
In low-speed running
b5 b4
0 0 : Not selected
0 1 :
4 access in low-speed running
1 0 :
3 access in low-speed running
1 1 :
2 access in low-speed running
At reset
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
2–28
7751 Group User’s Manual
CHAPTER 3
INPUT/OUTPUT
PINS
3.1 Programmable I/O ports
3.2
I/O pins of internal peripheral devices
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
This chapter describes the programmable I/O ports in the single-chip mode. For P0 to P4, which change
their functions according to the processor mode, refer also to the section “2.5 Processor modes” and
“Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
3.1 Programmable I/O ports
The 7751 Group has 68 programmable I/O ports, P0 to P8.
The programmable I/O ports have direction registers and port registers in the SFR area. Figure 3.1.1 shows
the memory map of direction registers and port registers.
P42 and P5 to P8 also function as the I/O pins of the internal peripheral devices. For the functions, refer
to the section “3.2 I/O pins of internal peripheral devices” and relevant sections of each internal peripheral
devices.
Addresses
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Port P0 register
16
Port P1 register
16
Port P0 direction register
16
Port P1 direction register
16
Port P2 register
16
Port P3 register
16
Port P2 direction register
16
Port P3 direction register
16
Port P4 register
16
Port P5 register
16
Port P4 direction register
16
Port P5 direction register
16
Port P6 register
16
Port P7 register
16
10
11
12
13
14
Fig. 3.1.1 Memory map of direction registers and port registers
3–2
Port P6 direction register
16
Port P7 direction register
16
Port P8 register
16
16
Port P8 direction register
16
7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
3.1.1 Direction register
This register determines the input/output direction of the programmable I/O port. Each bit of this register
corresponds one for one to each pin of the microcomputer.
Figure 3.1.2 shows the structure of port Pi (i = 0 to 8) direction register.
b1 b0b2b3b4b5b6b7
Port Pi direction register (i = 0 to 8)
(Addresses 4
16
, 516, 816, 916, C16, D16, 1016, 1116, 1416)
Bit Bit name Functions
0
1
2
3
4
5
6
7
Note: Bits 7 to 4 of the port P3 direction register cannot be written and are fixed to “0” at reading.
0
direction bit
Port Pi
Port Pi1 direction bit
Port Pi2 direction bit
3
direction bit
Port Pi
Port Pi
4
direction bit
Port Pi5 direction bit
6
direction bit
Port Pi
7
direction bit
Port Pi
Bit
Corresponding
pin
b7 b6 b5 b4 b3 b2 b1 b0
7
Pi
Pi6Pi5Pi4Pi3Pi2Pi1Pi
Fig. 3.1.2 Structure of port Pi (i = 0 to 8) direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
At reset
0
RW
0
RW
0
RW
0
RW
RW
0
RW
0
RW
0
RW
0
RW
0
7751 Group User’s Manual
3–3
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
3.1.2 Port register
Data is input/output to/from externals by writing/reading data to/from the port register. The port register
consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the
port register corresponds one for one to each pin of the microcomputer. Figure 3.1.3 shows the structure
of the port Pi (i = 0 to 8) register.
● When outputting data from programmable I/O ports set to output mode
➀ By writing data to the corresponding bit of the port register, the data is written into the port latch.
➁ The data is output from the pin according to the contents of the port latch.
By reading the port register of a port set to output mode, the contents of the port latch is read out,
instead of the pin state. Accordingly, the output data is correctly read without being affected by an
external load. (Refer to Figures 3.1.4 and 3.1.5.)
● When inputting data from programmable I/O ports set to input mode
➀ The pin which is set to input mode enters the floating state.
➁ By reading the corresponding bit of the port register, the data which is input from the pin can be
read out.
By writing data to the port register of a programmable I/O port set to input mode, the data is only
written into the port latch and is not output to externals. The pin retains floating.
3–4
7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
b1 b0b2b3b4b5b6b7
Port Pi register (i = 0 to 8)
(Addresses 2
16, 316, 616, 716, A16, B16, E16, F16, 1216)
Bit Bit name Functions
0
Port Pi
0
Port Pi
Port Pi
Port Pi3
Port Pi
Port Pi
Port Pi
Port Pi7
1
2
4
5
6
1
2
3
4
5
6
7
Note: Bits 7 to 4 of the port P3 register cannot be written and are fixed to “0” at reading.
Fig. 3.1.3 Port Pi (i = 0 to 8) register structure
Data is input/output to/from a pin by
reading/writing from/to the corresponding bit.
0 : “L” level
1 : “H” level
At reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
RW
RW
RW
RW
RW
RW
RW
RW
RW
7751 Group User’s Manual
3–5
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
Figures 3.1.4 and 3.1.5 show the port peripheral circuits.
[Inside dotted-line not included]
Ports P00 to P07, P10 to P17, P20 to P27,
P3
0
to P33, P43 to P4
6
Direction register
[Inside dotted-line included]
Ports P40, P41, P47, P51/TA0
P5
5
/TA2
IN
, P57/TA3
2
/INT0 to P64/INT2, P65/TB0IN to P67/TB2IN,
P6
P82/RxD0, P86/RxD
IN
, P53/TA1IN,
IN
, P61/TA4IN,
1
(There is no hysteresis for P82/RxD0 and P86/RxD1.)
[Inside dotted-line not included. ]
Ports P42/
1
, P83/TxD0, P87/TxD
1
[Inside dotted-line included. ]
0
/TA0
OUT
Ports P5
6
P5
[
Inside dotted-line not included]
/TA3
, P52/TA1
OUT
, P60/TA4
Ports P70/AN0 to P76/AN
6
OUT
, P54/TA2
OUT
OUT
,
Data bus
Data bus
Port latch
Direction register
“1”
Output
Port latch
Direction register
[
Inside dotted-line included]
Port P77/AN7/AD
TRG
Fig. 3.1.4 Port peripheral circuits (1)
Data bus
Port latch
Analog input
3–6
7751 Group User’s Manual
INPUT/OUTPUT PINS
3.1 Programmable I/O ports
Ports P80/CTS0/RTS0, P81/CLK0,
P84/CTS1/RTS1, P85/CLK
E output pin
1
Fig. 3.1.5 Port peripheral circuits (2)
Data bus
“1”
“0”
Direction register
Output
Port latch
7751 Group User’s Manual
3–7
INPUT/OUTPUT PINS
3.2 I/O pins of internal peripheral devices
3.2 I/O pins of internal peripheral devices (P42, P5–P8)
P42 and P5 to P8 also function as the I/O pins of the internal peripheral devices. Table 3.2.1 lists I/O pins
for the internal peripheral devices.
For their functions, refer to relevant sections of each internal peripheral device. For the clock
refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”
φ
1 output pin,
Table 3.2.1
Port
P42
P5
P60, P61
P62 to P64
P65 to P67
P7
P8
I/O pins for internal peripheral devices
I/O pins for internal peripheral devices
Clock
I/O pins of Timer A
Input pins of external interrupts
Input pins of Timer B
Input pins of A-D converter
I/O pins of Serial I/O
φ
1 output pin
3–8
7751 Group User’s Manual
CHAPTER 4
INTERRUPTS
4.1 Overview
4.2 Interrupt sources
4.3 Interrupt control
4.4 Interrupt priority level
4.5 Interrupt priority level detection circuit
4.6 Interrupt priority level detection time
4.7
Sequence from acceptance of interrupt
request to execution of interrupt routine
4.8 Return from interrupt routine
4.9 Multiple interrupts
4.10 External interrupts (INTi interrupt)
4.11 Precautions when using interrupts
____
INTERRUPTS
4.1 Overview
The suspension of the current operation in order to perform another operation owing to a certain factor is
referred to as “Interrupt.” This chapter describes the interrupts.
4.1 Overview
The M37751 has 19 interrupt sources to generate interrupt requests.
Figure 4.1.1 shows the interrupt processing sequence.
When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set
in the interrupt vector table (addresses FFD616 to FFFF16). Set the start address of each interrupt routine
at each interrupt vector address in the interrupt vector table.
Executing routine
Interrupt routine
Accept interrupt request
Suspend processing
Resume processing
Fig. 4.1.1 Interrupt processing sequence
Branch to start address
of interrupt routine
Return to original routine
Process interrupt
RTI instruction
4–2
7751 Group User’s Manual
INTERRUPTS
4.1 Overview
When an interrupt request is accepted, the contents of the registers listed below immediately preceding the
acceptance of the interrupt request are automatically saved to the stack area in order of registers ➀→➁→➂.
➀ Program bank register (PG)
➁ Program counter (PCL, PCH)
➂ Processor status register (PSL, PSH)
Figure 4.1.2 shows the state of the stack area just before entering the interrupt routine.
Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer
was executing before the interrupt request was accepted. As the RTI instruction is executed, the register
contents saved in the stack area are restored in order of registers ➂→➁→➀, and a return is made to the
routine executed before the acceptance of interrupt request and processing is resumed from it.
When an interrupt request is accepted and the RTI instruction is executed, the only above registers ➀ to
➂ are automatically saved and restored. When there are any other registers of which contents are necessary
to be kept, use software to save and restore them.
Stack area
Address
[S] – 5
[S] – 4
[S] – 3
[S] – 2
[S] – 1
[S]
[S] is an initial value that the stack pointer (S) indicates at
✽
accepting an interrupt request. The S’s contents become
[S] – 5 after saving the above registers.
Fig. 4.1.2 State of stack area just before entering interrupt routine
Processor status register’s low-order byte (PS
Processor status register’s high-order byte (PSH)
Program counter’s low-order byte (PC
Program counter’s high-order byte (PC
✽
Program bank register (PG)
L
)
L
)
H
)
7751 Group User’s Manual
4–3
INTERRUPTS
4.2 Interrupt sources
4.2 Interrupt sources
Table 4.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start
address of each interrupt routine at the vector addresses listed in this table.
Table 4.2.1 Interrupt sources and interrupt vector addresses
Interrupt source
Reset
Zero division
BRK instruction
____
DBC (Note)
Watchdog timer
____
INT0
____
INT1
____
INT2
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
A-D conversion
____
Interrupt vector address
High-order
address
FFFF16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFDB16
FFD916
FFD716
Low-order
address
FFFE16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFDA16
FFD816
FFD616
Non-maskable
Non-maskable software interrupt
Non-maskable software interrupt
Not used usually
Non-maskable interrupt
External interrupt due to INT0 pin input signal
External interrupt due to INT1 pin input signal
External interrupt due to INT2 pin input signal
Internal interrupt from Timer A0
Internal interrupt from Timer A1
Internal interrupt from Timer A2
Internal interrupt from Timer A3
Internal interrupt from Timer A4
Internal interrupt from Timer B0
Internal interrupt from Timer B1
Internal interrupt from Timer B2
Internal interrupt from UART0
Internal interrupt from UART1
Internal interrupt from A-D converter
Note: The DBC interrupt source is used exclusively for debugger control.
Remarks
____
____
____
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7751 Group User’s Manual
INTERRUPTS
4.2 Interrupt sources
Table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation.
Table 4.2.2 Occurrence factors of internal interrupt request
Interrupt
Zero division
interrupt
BRK instruction
interrupt
Watchdog timer
interrupt
Timer Ai interrupt
(i = 0 to 4)
Timer Bi interrupt
(i = 0 to 2)
UARTi receive
interrupt (i = 0, 1)
UARTi transmit
interrupt (i = 0, 1)
A-D conversion
interrupt
Interrupt request occurrence factors
Occurs when “0” is specified as the divisor for the DIV instruction (Division instruction).
(Refer to “7751 Series Software Manual.”)
Occurs when the BRK instruction is executed.
(Refer to “7751 Series Software Manual.”)
Occurs when the most significant bit of the watchdog timer becomes “0.”
(Refer to “Chapter 9. WATCHDOG TIMER.”)
Differs according to the timer Ai’s operating modes.
(Refer to “Chapter 5. TIMER A.”)
Differs according to the timer Bi’s operating modes.
(Refer to “Chapter 6. TIMER B.”)
Occurs at serial data reception. (Refer to “Chapter 7. SERIAL I/O.”)
Occurs at serial data transmission. (Refer to “Chapter 7. SERIAL I/O.”)
Occurs when A-D conversion is completed. (Refer to “Chapter 8. A-D CONVERTER.”)
7751 Group User’s Manual
4–5
INTERRUPTS
4.3 Interrupt control
4.3 Interrupt control
The enabling and disabling of maskable interrupts are controlled by the following :
•Interrupt request bit
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
•Interrupt disable flag (I)
The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor
status register (PS). The interrupt request bit and the interrupt priority level select bits are assigned to the
interrupt control register of each interrupt.
Figure 4.3.1 shows the memory assignment of the interrupt control registers, and Figure 4.3.2 shows their
structure.
●Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software.
●Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are independent of the interrupt disable flag (I).
Address
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
Fig. 4.3.1 Memory assignment of interrupt control registers
4–6
7751 Group User’s Manual
b7 b6 b5 b4 b3 b2 b1 b0
INTERRUPTS
4.3 Interrupt control
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 70
16
to 7C16)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit
3
7 to 4
Nothing is assigned.
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1 Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7 High level
0 : No interrupt request
1 : Interrupt request
Functions
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit
Interrupt priority level select bits
0
1
2
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1 Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7 High level
Functions
At reset
0
0
0
0
Undefined
At reset
0
0
0
RW
RW
RW
RW
RW
–
RW
RW
RW
RW
Interrupt request bit (Note)
3
4
Polarity select bit
Level sense/Edge sense select
5
bit
Nothing is assigned.
7, 6
Note: The INT
0 to INT2 interrupt request bits are invalid when selecting the level sense.
Fig. 4.3.2 Structure of interrupt control register
7751 Group User’s Manual
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
0 : Edge sense
1 : Level sense
0
0
0
Undefined
RW
RW
RW
–
4–7
INTERRUPTS
4.3 Interrupt control
4.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear the flag to “0” when enabling interrupts.
4.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” The bit remains set to “1” until the interrupt request
is accepted, and it is cleared to “0” when the interrupt request is accepted.
This bit also can be set to “0” or “1” by software.
For the INTi interrupt request bit (i = 0 to 2), when using the INTi interrupt with level sense, the bit is
ignored.
4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt. Use the SEB
or CLB instruction to set these bits.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0.
____ ____
Each interrupt priority level > Processor interrupt priority level (IPL)
Table 4.3.1 lists the setting of interrupt priority level, and Table 4.3.2 lists the interrupt enabled level
corresponding to IPL contents.
All the interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor
interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt
requests are accepted only when the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
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7751 Group User’s Manual
Table 4.3.1 Setting of interrupt priority level
Interrupt priority level select bits
b2
0
0
0
0
1
1
1
1
Table 4.3.2 Interrupt enabled level corresponding to IPL contents
IPL2
0
0
0
0
1
1
1
1
IPL0: Bit 8 in processor status register (PS)
IPL1: Bit 9 in processor status register (PS)
IPL2: Bit 10 in processor status register (PS)
b1
0
0
1
1
0
0
1
1
IPL1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
IPL0
0
1
0
1
0
1
0
1
Level 0 (Interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Enable level 1 and above interrupts.
Enable level 2 and above interrupts.
Enable level 3 and above interrupts.
Enable level 4 and above interrupts.
Enable level 5 and above interrupts.
Enable level 6 and level 7 interrupts.
Enable only level 7 interrupt.
Disable all maskable interrupts.
Interrupt priority level
Enabled interrupt priority level
INTERRUPTS
4.3 Interrupt control
Priority
—
Low
High
7751 Group User’s Manual
4–9
INTERRUPTS
4.4 Interrupt priority level
4.4 Interrupt priority level
When two or more interrupt requests are detected at the same sampling timing, at which whether an
interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts
enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted
first.
Among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources
except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.
Use the interrupt priority level select bits to set their priority levels. Additionally, the reset, which is handled
as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels
set by hardware. Figure 4.4.1 shows the interrupt priority levels set by hardware.
Note that software interrupts are not affected by interrupt priority levels. Whenever the instruction is executed,
a branch is certain to be made to the interrupt routine.
Reset
Priority levels determined by hardware
High LowPriority level
Fig. 4.4.1 Interrupt priority levels set by hardware
Watchdog
timer
16 interrupt sources except software interrupts
and watchdog timer interrupt
The user can set the desired priority levels inside of the dotted line.
••••••••••••••••••
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7751 Group User’s Manual
INTERRUPTS
4.5 Interrupt priority level detection circuit
4.5 Interrupt priority level detection circuit
The interrupt priority level detection circuit selects the interrupt having the highest priority level when more
than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level
detection circuit.
Interrupt priority level
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Level 0 (initial value)
Interrupt priority level
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
Timer B1
Timer B0
The highest priority level interrupt
Interrupt
disable flag (I)
Watchdog timer interrupt
Reset
Fig. 4.5.1 Interrupt priority level detection circuit
7751 Group User’s Manual
INT
1
INT
0
IPL
Processor interrupt priority level
Accepting of interrupt request
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INTERRUPTS
4.5 Interrupt priority level detection circuit
The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority
level sent from the preceding comparator (X in Figure 4.5.2); whichever interrupt of the higher priority level
is sent to the next comparator (Z in Figure 4.5.2). (Initial comparison value is “0.”) For interrupts for which
no interrupt request occurs, the priority level sent from the preceding comparator is forwarded to the next
comparator.
preceding comparator is forwarded to the next comparator. Accordingly, when the same priority level is set
by software, the interrupt requests are subject to the following relation about priority:
When the two priority levels are found the same by comparison, the priority level sent from the
A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2
____ ____ ____
> Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT2 > INT1 > INT0
Among the multiple interrupt requests sampled at the same time, one that has the highest priority level is
detectedd by the above comparison.
Then this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable
flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is retained
until it is accepted or its interrupt request bit is cleared to “0” by software.
The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch
cycle. However, when an op-code fetch cycle is generated during detection of an interrupt priority, new
detection of that does not start. (Refer to Figure 4.6.1.) Since the state of the interrupt request bit and
interrupt priority levels are latched during detection of interrupt priority, even if the bit state and priority
levels change, the detection is performed on the previous state before it has changed.
X
Y
Interrupt source Y
Time
Comparator
(Priority level
comparison)
Z
Fig. 4.5.2 Interrupt priority level detection model
X : Resultant priority level sent from the preceding
comparator (Highest priority at this point)
Y : Priority level of interrupt source Y
Z : Highest priority at this point
●When X
●When X
Y then Z = X
<
Y then Z = Y
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INTERRUPTS
4.6 Interrupt priority level detection time
4.6 Interrupt priority level detection time
After sampling had started, an interrupt priority level detection time has elapses before an interrupt request
is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the
interrupt priority level detection time.
As the interrupt priority level detection time, normally select “2 cycles of internal clock
(1) Interrupt priority detection time select bits
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Processor mode register 0 (Address 5E
Processor mode bits
Fix to “0.”
Software reset bit
b5, b4
Interrupt priority detection time select bits
16
φ
.”
(2) Interrupt priority level detection time
φ
Op code fetch cycle
Sampling pulse
(a) 7 cycles
Interrupt priority level
detection time
(b) 4 cycles
0 0
7 cycles of [(a) shown below]
4 cycles of [(b) shown below]
0 1
2 cycles of [(c) shown below]
1 0
Not selected
1 1
Fix to “0.”
φ
Clock
1 output select bit
(Note)
(c) 2 cycles
Note: Pulse exists when “2 cycles of ” is selected.
Fig. 4.6.1 Interrupt priority level detection time
φ
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INTERRUPTS
4.7
Sequence from acceptance of interrupt request to execution of interrupt routine
4.7
Sequence from acceptance of interrupt request to execution of interrupt routine
The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described
below.
When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt
is cleared to “0,” and then the interrupt processing starts from the next cycle of completion of the instruction
which is being executed at accepting the interrupt request. Figure 4.7.1 shows the sequence from acceptance
of interrupt request to execution of interrupt routine.
After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt
Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine
allocated in addresses 016 to FFFF16.
The INTACK sequence is automatically performed in the following order.
➀ The contents of the program bank register (PG) just before performing the INTACK sequence are stored
to stack.
➁ The contents of the program counter (PC) just before performing the INTACK sequence are stored to
stack.
➂ The contents of the processor status register (PS) just before performing the INTACK sequence is stored
to stack.
➃ The interrupt disable flag (I) is set to “1.”
➄ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).
➅ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt
vector address are set into the program counter (PC).
Performing the INTACK sequence requires at least 15 cycles of internal clock φ. Figure 4.7.2 shows the
INTACK sequence timing.
Execution is started beginning with an instruction at the start address of the interrupt routine after completing
the INTACK sequence.
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4.7
Sequence from acceptance of interrupt request to execution of interrupt routine
Interrupt request is accepted.
Interrupt request occurs.
INTERRUPTS
Instruction
1
➀
@
Instruction
2
➁
Interrupt response time
INTACK sequence Instructions in interrupt routine
➂
@
Time
@ : Duration for detecting interrupt priority
level
➀ Time from the occurrence of an interrupt request until the completion of executing an instruction
which is being executed at the occurrence.
➁ Time from the instruction next to ➀ (Note) until the completion of executing an instruction which is
being done at the end of priority detection
Note : At this time, interrupt priority detection starts.
➂ Time required to execute the INTACK sequence (15 cycles of φ at minimum)
Fig. 4.7.1 Sequence from acceptance of interrupt request to execution of interrupt routine
●When 2 access in low-speed running and stack pointer(S)’s content is even
φ
φ
CPU
A
H(CPU)
AMA
DATA
DATA
E
L(CPU)
H(CPU)
L(CPU)
Undefined
Undefined
Undefined
Undefined
00 0000
Vector address
(Low order)
00 00 00 00 00 00
0000 0000 [S] [S]–2 [S]–4 [S]–40000
IPL
INTACK sequence
[S] : Contents of stack pointer (S)
16
: Vector address
FFXX
Fig. 4.7.2 INTACK sequence timing (at minimum)
PG
PC
PC
AD
M
AD
FFXX
16
AD
AD
M
L
PS
PS
H
L
H
L
L
‘
Next instruction
Next instruction
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INTERRUPTS
4.7
Sequence from acceptance of interrupt request to execution of interrupt routine
4.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of multiple interrupts. (Refer
to section “4.9 Multiple interrupts.”)
When at reset or the watchdog timer or the software interrupt is accepted, the value shown in Table 4.7.1
is set in the IPL.
Table 4.7.1 Change in IPL at interrupt request acceptance
Interrupt source
Reset
Watchdog timer
Zero division
BRK instruction
Other interrupts
Level 0 (“0002”) is set.
Level 7 (“1112”) is set.
No change
No change
Interrupt priority level of the accepted interrupt request is set.
Change in IPL
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7751 Group User’s Manual
INTERRUPTS
4.7
Sequence from acceptance of interrupt request to execution of interrupt routine
4.7.2 Storing registers
The register storing operation performed during INTACK sequence depends on whether the contents of the
stack pointer (S) at accepting interrupt request are even or odd.
When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the
processor status register (PS) are stored as a 16-bit unit simultaneously at each other. When the contents
of the stack pointer (S) are odd, they are stored with twice by an 8-bit unit for each. Figure 4.7.3 shows
the register storing operation.
In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and
processor status register (PS) are stored to the stack area. The other necessary registers must be stored
by software at the beginning of the interrupt routine.
Using the PSH instruction can store all CPU registers except the stack pointer (S).
(1) Content of stack pointer (S) is even
Address
[S] – 5 (odd)
[S] – 4 (even)
[S] – 3 (odd)
[S] – 2 (even)
[S] – 1 (odd)
[S] (even)
Low-order byte of processor status register (PS
High-order byte of processor status register (PS
Low-order byte of program counter (PC
High-order byte of program counter (PC
Program bank register (PG)
(2) Content of stack pointer (S) is odd
Address
[S] – 5 (even)
[S] – 4 (odd)
[S] – 3 (even)
[S] – 2 (odd)
[S] – 1 (even)
Low-order byte of processor status register (PS
High-order byte of processor status register (PS
Low-order byte of program counter (PC
High-order byte of program counter (PC
Storing order
L
)
➂
H
)
L
)
H
)
Stores 16 bits at a time.
➁
Stores 16 bits at a time.
➀
Storing is completed with 3 times.
Storing order
L
)
H
)
L
)
H
)
➃
➄
➁
➂
Stores by each 8 bits.
[S] (odd)
✽
[S] is an initial value that the stack pointer (S) indicates at accepting an interrupt
request. The S’s contents become [S] – 5 after storing the above registers.
Program bank register (PG)
Fig. 4.7.3 Register storing operation
7751 Group User’s Manual
➀
Storing is completed with 5 times.
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INTERRUPTS
4.8 Return from interrupt routine 4.9 Multiple interrupts
4.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) immediately before performing the
INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to
the routine executed before the acceptance of interrupt request and processing is resumed from it left off.
For any register that is saved by software in the interrupt routine, restore it with the same data length and
same register length as it was saved by using the PUL instruction and others before executing the RTI
instruction.
4.9 Multiple interrupts
When a branch is made to the interrupt routine, the microcomputer becomes the following situation:
•Interrupt disable flag (I) = “1” (interrupts disabled)
•Interrupt request bit of the accepted interrupt = “0”
•Processor interrupt priority level (IPL) = interrupt priority level of the accepted interrupt
Accordingly, as long as the IPL remains unchanged, the microcomputer can accept the interrupt request that
has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (I)
to “0” in the interrupt routine. This is multiple interrupts.
Figure 4.9.1 shows the multiple interrupt mechanism.
The interrupt requests that have not been accepted owing to their low priority levels are retained. When the
RTI instruction is executed, the interrupt priority level of the routine that the microcomputer was executing
before accepting the interrupt request is restored to the IPL. Therefore, one of the interrupt requests being
retained is accepted when the following condition is satisfied at next detection of interrupt priority level:
Interrupt priority level of interrupt request being retained > Processor interrupt priority level (IPL)
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INTERRUPTS
4.9 Multiple interrupts
Time
Request
Interrupt 1
Interrupt priority level=3
Interrupt 2
Interrupt priority level=5
Interrupt 3
Interrupt priority level=2
Main routineReset
IPL = 0
I = 1
I = 0
Nesting
Interrupt 1
I = 1
IPL = 3
I = 0
Multiple interrupt
Interrupt 2
I = 1
IPL = 5
RTI
I = 0
RTI
I = 0
IPL = 0
Interrupt 3
I = 1
IPL = 2
RTI
I = 0
IPL = 0
IPL = 3
Interrupt 3
This request cannot be accepted
because its priority level is lower
than interrupt 1’s.
The instruction of main routine is not
executed then.
I : Interrupt disable flag
IPL : processor interrupt priority level
: They are set automatically.
: Set by software.
Fig. 4.9.1 Multiple interrupt mechanism
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10 External interrupts (INTi interrupt)
An external interrupt request occurs by input signals to the INTi (i = 0 to 2) pin. The occurrence factor of
interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits
5 and 4 at addresses 7D16 to 7F16) shown in Figure 4.10.1. Table 4.10.1 lists the occurrence factor of INTi
interrupt request.
When using P62/INT0 to P64/INT2 pins as input pins of external interrupts, set the corresponding bits at
address 1016 (port P6 direction register) to “0.” (Refer to Figure 4.10.2.)
The signals input to the INTi pin require “H” or “L” level width of 250 ns or more independent of the f(XIN).
Additionally, even when using the pins P62/INT0 to P64/INT2 as the input pins of external interrupt, the user
can obtain the pin’s state by reading bits 2 to 4 at address E16 (port P6 register).
Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,
make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising
or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.
Table 4.10.1 Occurrence factor of INTi interrupt request
b5
0
0
1
1
___ ___
b4
0
Interrupt request occurs at falling of the signal input to the INTi pin (edge sense).
1
Interrupt request occurs at rising of the signal input to the INTi pin (edge sense).
0
Interrupt request occurs while the INTi pin level is “H” (level sense).
1
Interrupt request occurs while the INTi pin level is “L” (level sense).
___
___ ___
___
___
INTi interrupt request occurrence factor
___
___
___
___
___
___
___ ___
The INTi interrupt request occurs by always detecting the INTi pin’s state. Accordingly, when the user does
___ ___
not use the INTi interrupt, set the INTi interrupt’s priority level to level 0.
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b7 b6 b5 b4 b3 b2 b1 b0
INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1 Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7 High level
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
“L” level for level sense and at
rising edge for edge sense.
0 : Edge sense
1 : Level sense
0 to INT2 interrupt request bits are invalid when selecting the level sense.
___
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit (Note)
3
4
Polarity select bit
Level sense/Edge sense select bit
5
Nothing is assigned.
7, 6
Note: The INT
Fig. 4.10.1 Structure of INTi (i=0 to 2) interrupt control register
Functions
At reset
0
0
0
0
0
0
Undefined
RW
RW
RW
RW
RW
RW
RW
–
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
b1 b0b2b3b4b5b6b7
Port P6 direction register (Address 1016)
Bit Corresponding pin Functions
0
1
2
3
4
5
6
7
OUT
TA4
TA4IN pin
INT0 pin
1
pin
INT
INT
2
pin
TB0IN pin
IN
pin
TB1
IN
pin
TB2
pin
0 : Input mode
1 : Output mode
When using pins as external interrupt
input pins,set the corresponding bits
to “0.”
At reset
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
: Bits 0, 1 and bits 5 to 7 are not used for external interrupts.
Fig. 4.10.2 Relationship between port P6 direction register and input pins of external interrupt
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10.1 Function of INTi interrupt request bit
(1) Selecting edge sense mode
The interrupt request bit has the same function as that of internal interrupts. That is, when an
interrupt request occurs, the interrupt request bit is set to “1.” The bit remains set to “1” until the
interrupt request is accepted; it is cleared to “0” when the interrupt request is accepted. By software,
this bit also can be set to “0” in order to clear the interrupt request or “1” in order to generate the
interrupt request.
(2) Selecting level sense mode
___
The INTi interrupt request bit becomes ignored.
In this case, the interrupt request occurs continuously while the level of the INTi pin is valid level✽1.
___ ___
When the INTi pin level changes from the valid level to the invalid level✽2 before the INTi interrupt
request is accepted, this interrupt request is not retained. (Refer to Figure 4.10.4.)
Valid level✽1: This means the level which is selected by the polarity select bit (bit 4 at addresses 7D16
to 7F16).
Invalid level✽2: This means the reversed level of a valid level.
INT
i
pin
Edge detection
circuit
___
Fig. 4.10.3 Circuit of INTi Interrupt
Data bus
Interrupt request bit
Level sense/Edge sense
select bit
“0”
“1”
___
Interrupt request
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
Interrupt request is accepted.
Valid
i
pin level
INT
Invalid
When the INTi pin’s level changes to an
invalid level before an interrupt request is
accepted, the interrupt request is not
retained.
Return to main routine.
Main routine
First interrupt routine
___
Second interrupt
routine
Third interrupt
Fig. 4.10.4 Occurrence of INTi interrupt request in level sense mode
Main routine
routine
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INTERRUPTS
___
4.10 External interrupts (INTi interrupt)
___
4.10.2 Switch of occurrence factor of INTi interrupt request
To switch the occurrence factor of INTi interrupt request from the level sense to the edge sense, set the
___
INTi interrupt control register in the sequence shown in Figure 4.10.5 (1). To change the polarity, set the
___
INTi interrupt control register in the sequence shown in Figure 4.10.5 (2).
___
(1)
Switching from level sense to edge sense
Set the interrupt priority level to level 0
( Disable INTi interrupt )
Clear level sense/edge sense select bit to “0”
( Select edge sense )
Clear interrupt request bit to “0”
Set the interrupt priority level to level 1–7
(Enable acceptance of
INTi interrupt request)
(2) Changing polarity
Set the interrupt priority level to level 0
( Disable INTi interrupt )
Set polarity select bit
Clear interrupt request bit to “0”
Set the interrupt priority level to level 1–7
(Enable acceptance of
INTi interrupt request)
Note: Follow the above procedure each. Do not perform 2 or more setting at the same
time, with 1 instruction.
___
Fig. 4.10.5 Switching flow of occurrence factor of INTi interrupt request
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INTERRUPTS
4.11 Precautions when using interrupts
4.11 Precautions when using interrupts
To change the interrupt priority level select bits (bits 0 to 2 at addresses 7016 to 7F16), 2 to 7 cycles of
are required after executing an write-instruction until completion of the interrupt priority level’s change.
Accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level
of which interrupt source is the same within a very short execution time consisting of a few instructions.
Figure 4.11.1 shows a program example to reserve time required for changing interrupt priority level. The
time for change depends on the interrupt priority detection timer select bits (bits 4 and 5 at address 5E16).
Table 4.11.1 lists the relation between the number of instructions to be inserted with program example of
Figure 4.11.1 and the interrupt priority detection time select bits.
:
LDM.B #0XH, 007XH
NOP
NOP
NOP
LDM.B #0XH, 007XH
:
; Write to interrupt priority level select bits
; Insert NOP instruction (Note)
;
;
; Write to interrupt priority level select bits
φ
Note: All instructions (other than instructions for writing to address 7X
same cycles as NOP instruction can also be inserted. Confirm the number of
instructions to be inserted by Table 4.11.1.
Fig. 4.11.1 Program example to reserve time required for changing interrupt priority level
Table 4.11.1 Relation between number of instructions to be inserted with program example of Figure
4.11.1 and interrupt priority detection time select bits
Interrupt priority detection time select bits (Note)
b5
0
0
1
1
Note: We recommend [b5 = “1”, b4 = “0”].
b4
0
1
0
1
Interrupt priority level
detection time
7 cycles of
4 cycles of
2 cycles of
Do not select.
φ
φ
φ
16
) which have the
Number of inserted
instructions
NOP instruction 4 or more
NOP instruction 2 or more
NOP instruction 1 or more
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CHAPTER 5
TIMER A
5.1 Overview
5.2 Block description
5.3 Timer mode
5.4 Event counter mode
5.5 One-shot pulse mode
5.6
Pulse width modulation (PWM) mode
TIMER A
5.1 Overview
Timer A is used primarily for output to externals. It consists of five counters, timers A0 to A4, each equipped
with a 16-bit reload function. Timers A0 to A4 operate independently of one another.
5.1 Overview
Timer Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, Timers A0
to A4 all have the same functions.
● Timer mode
The timer counts an internally generated count source. Following functions can be used in this mode:
•Gate function
•Pulse output function
● Event counter mode
The timer counts an external signal. Following functions can be used in this mode:
•Pulse output function
•Two-phase pulse signal processing function (Timers A2, A3, and A4)
● One-shot pulse mode
The timer outputs a pulse which has an arbitrary width once.
● Pulse width modulation (PWM) mode
Timer outputs pulses which have an arbitrary width in succession. The timer functions as which pulse
width modulator as follows:
•16-bit pulse width modulator
•8-bit pulse width modulator
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TIMER A
5.2 Block description
5.2 Block description
Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described
below.
f
512/f 1024
TAi
TAi
f
OUT
f 2/f
f
16/f 32
64
/f
IN
128
4
Polarity
switching
Count source
select bits
Event counter mode
Timer mode
One-shot pulse mode
PWM mode
Timer mode
(Gate function)
Trigger
Data bus (odd)
Data bus (even)
(Low-order 8 bits) (High-order 8 bits)
Timer Ai reload register (16)
Timer Ai counter (16)
Up-count/down-count
Count start bit
Down-count
Up-down bit
Pulse output
function select bit
Toggle
F.F.
switching
(Always down-count except
for event counter mode)
Timer Ai
interrupt
request bit
Fig. 5.2.1 Block diagram of Timer A
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TIMER A
5.2 Block description
5.2.1 Counter and reload register (timer Ai register)
Each of timer Ai counter and reload register consists of 16 bits.
The counter down-counts each time the count source is input. In the event counter mode, it can also
function as an up-counter.
The reload register is used to store the initial value of the counter. When the counter underflows or
overflows, the reload register’s contents are reloaded into the counter.
Values are set to the counter and reload register by writing a value to the timer Ai register. Table 5.2.1
lists the memory assignment of the timer Ai register.
The value written into the timer Ai register when counting is not in progress is set to the counter and reload
register. The value written into the timer Ai register when counting is in progress is set to only the reload
register. In this case, the reload register’s updated contents are transferred to the counter at the next
reload time. The value got when reading out the timer Ai register varies according to the operating mode.
Table 5.2.2 lists reading and writing from and to the timer Ai register.
Table 5.2.1 Memory assignment of timer Ai register
Timer Ai register High-order byte Low-order byte
Timer A0 register Address 4716 Address 4616
Timer A1 register Address 4916 Address 4816
Timer A2 register Address 4B16 Address 4A16
Timer A3 register Address 4D16 Address 4C16
Timer A4 register Address 4F16 Address 4E16
Note: When reset, the contents of the timer Ai
register are undefined.
Table 5.2.2 Reading and writing from and to timer Ai register
Operating mode
Timer mode
Event counter mode
One-shot pulse mode
Pulse width modulation (PWM) mode
Notes 1: Also refer to “[Precautions when operating in timer mode]” and “[Precautions when oper-
ating in event counter mode].”
2: When reading and writing to/from the timer Ai register, perform them in a unit of 16 bits.
Counter value is read out.
(Note 1)
Undefined value is read out.
Read
<During counting>
Written to only reload register.
<When not counting>
Written to both counter and
reload register.
Write
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TIMER A
5.2 Block description
5.2.2 Count start register
This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure
5.2.2 shows the structure of the count start register.
b7 b6 b5 b4 b3 b2 b1 b0
Count start register (Address 4016)
Bit
Timer A0 count start bit
0
Timer A1 count start bit
1
2
Timer A2 count start bit
3
Timer A3 count start bit
Timer A4 count start bit
4
5
Timer B0 count start bit
6
Timer B1 count start bit
7
Timer B2 count start bit
: Bits 7 to 5 are not used for Timer A.
Fig. 5.2.2 Structure of count start register
Bit name
0 : Stop counting
1 : Start counting
At reset
0
0
0
0
0
0
0
0
RWFunctions
RW
RW
RW
RW
RW
RW
RW
RW
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TIMER A
5.2 Block description
5.2.3 Timer Ai mode register
Figure 5.2.3 shows the structure of the timer Ai mode register. Operating mode select bits are used to
select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode.
These bits are described in the paragraph of each operating mode.
b7 b6 b5 b4 b3 b2 b1 b0
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Operating mode select bits
0
1
2
These bits have different functions according to the operating mode.
3
4
5
6
7
Bit name
Fig. 5.2.3 Structure of timer Ai mode register
Functions
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
Pulse width modulation (PWM) mode
1 1 :
At reset
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
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7751 Group User’s Manual
TIMER A
5.2 Block description
5.2.4 Timer Ai interrupt control register
Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer
to “Chapter 4. INTERRUPTS.”
b7 b6 b5 b4 b3 b2 b1 b0
Timer Ai interrupt control registers (i = 0 to 4) (Addresses 7516 to 7916)
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit
3
7 to 4
Nothing is assigned.
Bit name
Fig. 5.2.4 Structure of timer Ai interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select priority
levels 1 to 7. When a timer Ai interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To
disable timer Ai interrupts, set these bits to “0002” (level 0).
Functions
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1 Low level
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7 High level
0 : No interrupt request
1 : Interrupt request
At reset
0
0
0
0
Undefined
RW
RW
RW
RW
RW
–
(2) Interrupt request bit (bit 3)
This bit is set to “1” when the timer Ai interrupt request occurs. This bit is automatically cleared to
“0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or “0” by software.
7751 Group User’s Manual
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TIMER A
5.2 Block description
5.2.5 Port P5 and port P6 direction registers
The I/O pins of Timers A0 to A3 are shared with port P5, and the I/O pins of Timer A4 are shared with
port P6. When using these pins as Timer Ai’s input pins, set the corresponding bits of the port P5 and port
P6 direction registers to “0” to set these ports for the input mode. When used as Timer Ai’s output pins,
these pins are forcibly set to output pins of Timer Ai regardless of the direction registers’s contents. Figure
5.2.5 shows the relationship between the port P5 and port P6 direction registers and the Timer Ai’s I/O
pins.
b1 b0b2b3b4b5b6b7
Port P5 direction register (Address D
16
)
Bit Corresponding pin name Functions
TA0
OUT
TA0IN pin
OUT
TA1
IN
pin
TA1
OUT
TA2
TA2IN pin
OUT
TA3
IN
pin
TA3
pin
pin
pin
pin
0: Input mode
1: Output mode
When using these pins as
Timer Ai’s input pins, set the
corresponding bits to “0.”
16
)
0
1
2
3
4
5
6
7
b1 b0b2b3b4b5b6b7
Port P6 direction register (Address 10
Corresponding pin name FunctionsBit
TA4
OUT
TA4IN pin
INT0 pin
1
pin
INT
INT
2
pin
TB0
IN
pin
IN
pin
TB1
IN
pin
TB2
pin
0: Input mode
1: Output mode
When using these pins as
Timer Ai’s input pins, set the
corresponding bits to “0.”
0
1
2
3
4
5
6
7
At reset
At reset
RW
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
: Bits 7 to 2 are not used for Timer A.
Fig. 5.2.5 Relationship between port P5 and port P6 direction registers and Timer Ai’s I/O pins
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7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3 Timer mode
In this mode, the timer counts an internally generated count source. (Refer to Table 5.3.1.) Figure 5.3.1
shows the structures of the timer Ai mode register and timer Ai register in the timer mode.
Table 5.3.1 Specifications of timer mode
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin function
TAiOUT pin function
Read from timer Ai register
Write to timer Ai register
f2/f4, f16/f32, f64/f128, or f512/f1024
• Down-count
• When the counter underflows, reload register’s contents are reloaded
and counting continues.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When the counter underflows.
Programmable I/O port or gate input
Programmable I/O port or pulse output
Counter value can be read out.
● While counting is stopped
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only
reload register. (Transferred to counter at next reload timing.)
Specifications
7751 Group User’s Manual
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TIMER A
5.3 Timer mode
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Bit
Operating mode select bits
0
Bit name Functions
1
2
Pulse output function select bit
Gate function select bits
3
4
5
Fix this bit to “0” in the timer mode.
Count source select bits
6
7
b1 b0
0 0 : Timer mode
0 : No pulse output
(TAi
OUT
pin functions as a programmable
I/O port.)
1 : Pulse output
(TAi
OUT
pin functions as a pulse output
pin.)
b4 b3
0 0 : No gate function
IN
0 1 : (TAi
pin functions as a prog-
rammable I/O port.)
1 0 : Gate function
(Counter counts only while TAi
pin’s input signal is “L” level.)
1 1 : Gate function
(Counter counts only while TAi
pin’s input signal is “H” level.)
b7 b6
0 0 : f2/f
4
0 1 : f16/f
1 0 : f64/f
1 1 : f
32
128
512/f1024
At reset
0RW
0RW
0
0RW
IN
0
IN
0
0RW
0
RW
RW
RW
RW
RW
(b15) (b8)
b7 b0 b7 b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 49
Timer A2 register (Addresses 4B
Timer A3 register (Addresses 4D
Timer A4 register (Addresses 4F
16
, 4816)
16
, 4A16)
16
, 4C16)
16
, 4E16)
FunctionsBit
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter
divides the count source frequency by n + 1.
When reading, the register indicates the
counter value.
Fig. 5.3.1 Structures of timer Ai mode register and timer Ai register in timer mode
At reset
Undefined
RW
RW
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7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3.1 Setting for timer mode
Figures 5.3.2 and 5.3.3 show an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4.
INTERRUPTS.”
Selecting timer mode and each function
b7 b0
0
00
Timer Ai mode register (i = 0 to 4) (Addresses 56
16 to 5A16)
Selection of timer mode
Pulse output function select bit
0: No pulse output.
1: Pulses output.
Gate function select bits
b4 b3
0 0:
0 1:
1 0: Gate function (Counter counts only while TAiIN pin’s input signal is “L” level.)
1 1: Gate function (Counter counts only while TAiIN pin’s input signal is “H” level.)
No gate function
Count source select bits
b7 b6
0 0: f2/f4
0 1: f16/f32
1 0: f64/f128
1 1: f512/f1024
Setting divide ratio
(b15) (b8)
b7 b0
Timer A0 register (Addresses 4716, 4616)
b7 b0
Timer A1 register (Addresses 49
Timer A2 register (Addresses 4B
Timer A3 register (Addresses 4D
Timer A4 register (Addresses 4F
Can be set to “000016” to “FFFF16” (n).
Note : Counter divides the count source frequency by n + 1.
Continue to Figure 5.3.3 on next page.
16, 4816)
16, 4A16)
16, 4C16)
16, 4E16)
Fig. 5.3.2 Initial setting example for registers relevant to timer mode (1)
7751 Group User’s Manual
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TIMER A
5.3 Timer mode
From preceding Figure 5.3.2.
Setting interrupt priority level
b7 b0
Setting port P5 and port P6 direction registers
b7 b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Port P5 direction register (Address D16)
16 to 7916)
TA0IN pin
IN pin
TA1
TA2IN pin
TA3
IN pin
b7 b0
Port P6 direction register (Address 1016)
TA4IN pin
When gate function is selected, set the bit corresponding to the TAi
Setting count start bit to “1.”
b7 b0
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
IN pin to “0.”
Count starts
Fig. 5.3.3 Initial setting example for registers relevant to timer mode (2)
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TIMER A
5.3 Timer mode
5.3.2 Count source
In the timer mode, the count source select bits (bits 6 and 7 at addresses 5616 to 5A16) select the count
source. Table 5.3.2 lists the count source frequency.
Table 5.3.2 Count source frequency
Count source
select bits
b7
0
0
1
1
Clock source for peripheral devices select bit : bit 2 at address 5F16
b6
0
1
0
1
Clock source for peripheral
devices select bit = “0”
Count source
f4
f32
f128
f1024
195.3125 kHz
24.4141 kHz
f(XIN) = 25 MHz
Frequency
6.25 MHz
781.25 kHz
Clock source for peripheral
devices select bit = “1”
Count source
f2
f16
f64
f512
Frequency
12.5 MHz
1.5625 MHz
390.625 kHz
48.8281 kHz
f(XIN) = 40 MHz
Clock source for peripheral
devices select bit = “0”
Count source
f4
f32
f128
f1024
Frequency
10 MHz
1.25 MHz
312.5 kHz
39.0625 kHz
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TIMER A
5.3 Timer mode
5.3.3 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➁ When the counter underflows, the reload register’s contents are reloaded and counting continues.
➂ The timer Ai interrupt request bit is set to “1” when the counter underflows in ➁. The interrupt request
bit remains set to “1” until the interrupt request is accepted or the interrupt request bit is cleared to “0”
by software.
Figure 5.3.4 shows an example of operation in the timer mode.
n = Reload register’s contents
FFFF
16
Starts counting.
1 / fi ✕ (n+1)
Stops counting.
Counter contents (Hex.)
0000
Count start bit
Timer Ai interrupt
request bit
fi = frequency of count source
(f
n
16
“1”
“0”
“1”
“0”
2/f4
, f16/f32, f64/f
Set to “1” by software.
128
, f
512/f1024
)
Cleared to “0” by software.
Cleared to “0” when interrupt request is
accepted or cleared by software.
Restarts counting.
Set to “1” by software.
Fig. 5.3.4 Example of operation in timer mode (without pulse output and gate functions)
Time
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7751 Group User’s Manual
TIMER A
5.3 Timer mode
5.3.4 Select function
The following describes the selective gate and pulse output functions.
(1) Gate function
The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616
to 5A16 ) to “102” or “112.” The gate function makes it possible to start or stop counting depending on
the TAiIN pin’s input signal. Table 5.3.3 lists the count valid levels.
Figure 5.3.5 shows an example of operation selecting the gate function.
When selecting the gate function, set the port P5 and port P6 direction registers’ bits which correspond
to the TAiIN pin for the input mode. Additionally, make sure that the TAiIN pin’s input signal has a pulse
width equal to or more than two cycles of the count source.
Table 5.3.3 Count valid levels
Gate function select bits
b4 b3
1 0 While TAiIN pin’s input signal is “L” level
1 1 While TAiIN pin’s input signal is “H” level
Note: The counter does not count while the TAiIN pin’s input signal is not at the count valid level.
Count valid level (Duration when counter counts)
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TIMER A
5.3 Timer mode
Count start bit
TAi
IN
pin’s
input signal
Timer Ai interrupt
request bit
n = Reload register’s contents
FFFF
16
n
Counter contents (Hex.)
16
0000
“1”
“0”
Count valid
level
Invalid level
“1”
“0”
➀ Starts counting.
Set to “1” by software.
➁ Stops counting.
Time
IN
➀ The counter counts when the count start bit = “1” and the TAi
level.
➁ The counter stops counting while the TAi
counter value is retained.
IN
pin’s input signal is not at the count valid level, and the
pin’s input signal is at the count valid
Fig. 5.3.5 Example of operation selecting gate function
Cleared to “0” when
interrupt request is
accepted or cleared
by software.
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TIMER A
5.3 Timer mode
(2) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin
outputs pulses of which polarity is inverted each time the counter underflows.
When the count start bit (address 4016) is “0” (count stopped), the TAiOUT pin outputs “L” level. Figure
5.3.6 shows an example of operation selecting the pulse output function.
n = Reload register’s contents
FFFF
16
Starts counting.
Starts counting.
counter contents (Hex.)
0000
Count start bit
Pulse output from
TAiout pin
Timer Ai interrupt
request bit
n
“H”
“L”
“1”
“0”
“1”
“0”
Restarts
counting.
16
Time
Set to “1” by software.
Cleared to “0” when interrupt request is accepted or cleared by software.
Cleared to “0” by software.
Set to “1” by software.
Fig. 5.3.6 Example of operation selecting pulse output function
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TIMER A
5.3 Timer mode
[Precautions when operating in timer mode]
By reading the timer Ai register, the counter value can be read out at any timing while counting is in
progress. However, if the timer Ai register is read at the reload timing shown in Figure 5.3.7, the value
“FFFF16” is read out. When reading the timer Ai register after setting a value to the register while counting
is not in progress and before the counter starts counting, the set value is read out correctly.
Reload
Counter value
(Hex.)
Read value
(Hex.)
n = Reload register’s contents
Fig. 5.3.7 Reading timer Ai register
210
21 0
FFFF
n n – 1
n – 1
Time
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7751 Group User’s Manual
TIMER A
5.4 Event counter mode
5.4 Event counter mode
In this mode, the timer counts an external signal. (Refer to Tables 5.4.1 and 5.4.2.) Figure 5.4.1 shows the
structures of the timer Ai mode register and timer Ai register in the event counter mode.
Table 5.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing
function)
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin function
TAiOUT pin function
Read from timer Ai register
Write to timer Ai register
● External signal input to the TAiIN pin
● The count source’s valid edge can be selected between the falling
and the rising edges by software.
●
Up-count or down-count can be switched by external signal or software.
● When the counter overflows or underflows, reload register’s contents
are reloaded and counting continues.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When the counter overflows or underflows.
Count source input
Programmable I/O port, pulse output, or up-count/down-count switch
signal input
Counter value can be read out.
● While counting is stopped
When a value is written to timer Ai register, it is written to both
reload register and counter.
● While counting is in progress
When a value is written to timer Ai register, it is written to only reload
register. (Transferred to counter at next reload time.)
Specifications
7751 Group User’s Manual
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